From b2c634d1bb3b763054709febfbb7c954860b87d2 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 2 May 2019 16:26:33 -0700 Subject: [PATCH] gpu: nvgpu: fix MISRA 16.x errors in gr falcon Fixed issues related to switch case formatting. JIRA NVGPU-3226 Change-Id: I969ff3f56857ed0a523fb353ff07532ed50a114a Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2110734 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 934a9254f..0d47f0a43 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -347,7 +347,24 @@ void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g, nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); - /* fallthrough */ + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), + addr_code32); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), + code_size); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), + addr_data32); + nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), + data_size); + break; case FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED: case FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED: case FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED: @@ -395,6 +412,7 @@ void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g, " with reg_offset 0x%08x", boot_signature, reg_offset); BUG(); + break; } }