From b2c8827c65d4a6bbb61ccaa9f267c10198f10c6f Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 13 Feb 2023 11:26:52 +0530 Subject: [PATCH] gpu: nvgpu: fix tex rd coalesce disable logic NETLIST_REGIONID_SW_CTX_LOAD writes update gr_gpcs_tpcs_tex_m_dbg2_r to default value that keeps rd coalesce enabled for LG & SU. Disable rd coalesce for tex, lg and su after NETLIST_REGIONID_SW_CTX_LOAD writes during gr init and golden ctx init for it to take effect. For gr sw method handling, don't update the tex rd coalesce on interrupt with offset *_SET_RD_COALESCE as we want to keep rd coalescing disabled. Bug 3881919 Change-Id: Ie7e6616d48f84547ce3380bfa395910b7995c05b Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857141 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 14 +++++++++----- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 16 +++++----------- .../nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 10 +++++++++- 3 files changed, 23 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d042bd7b9..1eda85365 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics * - * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1662,6 +1662,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, sw_ctx_load->l[i].value); } + if (g->ops.gr.disable_rd_coalesce) { + g->ops.gr.disable_rd_coalesce(g); + } + if (g->ops.gr.init_preemption_state) { g->ops.gr.init_preemption_state(g); } @@ -4704,16 +4708,16 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) g->ops.fb.init_cbc(g, gr); } - if (g->ops.gr.disable_rd_coalesce) { - g->ops.gr.disable_rd_coalesce(g); - } - /* load ctx init */ for (i = 0; i < sw_ctx_load->count; i++) { gk20a_writel(g, sw_ctx_load->l[i].addr, sw_ctx_load->l[i].value); } + if (g->ops.gr.disable_rd_coalesce) { + g->ops.gr.disable_rd_coalesce(g); + } + err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g), GR_IDLE_CHECK_DEFAULT); if (err != 0U) { diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index dacef7840..23950ed16 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1,7 +1,7 @@ /* * GM20B GPC MMU * - * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -275,16 +275,7 @@ void gr_gm20b_commit_global_pagepool(struct gk20a *g, void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data) { - u32 val; - - nvgpu_log_fn(g, " "); - - val = gk20a_readl(g, gr_gpcs_tpcs_tex_m_dbg2_r()); - val = set_field(val, gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(), - gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(data)); - gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), val); - - nvgpu_log_fn(g, "done"); + nvgpu_log_info(g, "Not updating rd coalesce"); } int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, @@ -1447,6 +1438,9 @@ void gm20a_gr_disable_rd_coalesce(struct gk20a *g) dbg2_reg = set_field(dbg2_reg, gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(), gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(0)); + dbg2_reg = set_field(dbg2_reg, + gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_m(), + gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_f(0)); gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index 80663c2e5..79ad32693 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -2348,6 +2348,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) { return 0x1U << 4U; } +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_m(void) +{ + return 0x1U << 5U; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0acU;