gpu: nvgpu: Move intr data members from MC to CIC

Move interrupt specific data-members from common.mc to common.cic
Some of these data members like sw_irq_stall_last_handled_cond need
To be initialized much earlier during the OS specific init/probe stage.
Also, some more members from struct nvgpu_interrupts(like stall_size,
stall_lines[]), which will soon be moved to CIC will also need to be
initialized early during the OS specific probe stage.
However, the chip specific LUT can only be initialized after the
hal_init stage where the HALs are all initialized.
Split the CIC init to accommodate the above initialization requirements.

JIRA NVGPU-6899

Change-Id: I9333db4cde59bb0aa8f6eb9f8472f00369817a5d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552535
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

userspace/required_tests.ini

@@ -331,7 +331,6 @@ test_mc_free_env.mc_free_env=0
 test_mc_setup_env.mc_setup_env=0
 test_pause_resume_mask.pause_resume_mask=0
 test_unit_config.unit_config=2
-test_wait_for_deferred_interrupts.wait_for_deferred_interrupts=0
 
 [mm.as]
 test_as_alloc_share.as_alloc_share_0k_um=0

userspace/units/fifo/nvgpu-fifo-common.c

@@ -33,6 +33,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/device.h>
 #include <nvgpu/cic_mon.h>
+#include <nvgpu/cic_rm.h>
 
 #include <nvgpu/posix/io.h>
 
@@ -199,6 +200,16 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args)
 		unit_return_fail(m, "CIC LUT init failed\n");
 	}
 
+	err = nvgpu_cic_rm_setup(g);
+	if (err != 0) {
+		unit_return_fail(m, "CIC-rm init failed\n");
+	}
+
+	err = nvgpu_cic_rm_init_vars(g);
+	if (err != 0) {
+		unit_return_fail(m, "CIC-rm vars init failed\n");
+	}
+
 	return UNIT_SUCCESS;
 
 fail:

userspace/units/gr/nvgpu-gr.c

@@ -34,6 +34,7 @@
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/gr_falcon.h>
 #include <nvgpu/cic_mon.h>
+#include <nvgpu/cic_rm.h>
 
 #include "common/gr/gr_falcon_priv.h"
 
@@ -180,6 +181,15 @@ int test_gr_init_setup_ready(struct unit_module *m,
 		unit_return_fail(m, "CIC LUT init failed\n");
 	}
 
+	err = nvgpu_cic_rm_setup(g);
+	if (err != 0) {
+		unit_return_fail(m, "CIC-rm init failed\n");
+	}
+
+	err = nvgpu_cic_rm_init_vars(g);
+	if (err != 0) {
+		unit_return_fail(m, "CIC-rm vars init failed\n");
+	}
 	/* Allocate and Initialize GR */
 	err = test_gr_init_setup(m, g, args);
 	if (err != 0) {

userspace/units/mc/nvgpu-mc.c

@@ -653,37 +653,6 @@ int test_enable_disable_reset(struct unit_module *m, struct gk20a *g, void *args
 	return UNIT_SUCCESS;
 }
 
-int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
-					void *args)
-{
-	struct nvgpu_posix_fault_inj *cond_fi =
-					nvgpu_cond_get_fault_injection();
-
-	nvgpu_cond_init(&g->mc.sw_irq_stall_last_handled_cond);
-	nvgpu_cond_init(&g->mc.sw_irq_nonstall_last_handled_cond);
-
-	/* immediate completion */
-	nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
-	nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
-	nvgpu_cic_rm_wait_for_deferred_interrupts(g);
-
-	/* cause timeout */
-	nvgpu_posix_enable_fault_injection(cond_fi, true, 0);
-
-	/* wait on stall until timeout for branch coverage */
-	nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 1);
-	nvgpu_cic_rm_wait_for_deferred_interrupts(g);
-
-	/* wait on nonstall until timeout for branch coverage */
-	nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
-	nvgpu_cic_rm_wait_for_deferred_interrupts(g);
-
-	/* disable the fault injection */
-	nvgpu_posix_enable_fault_injection(cond_fi, false, 0);
-
-	return UNIT_SUCCESS;
-}
-
 struct unit_module_test mc_tests[] = {
 	UNIT_TEST(mc_setup_env,			test_mc_setup_env,			NULL, 0),
 	UNIT_TEST(unit_config,			test_unit_config,			NULL, 2),
@@ -695,7 +664,6 @@ struct unit_module_test mc_tests[] = {
 	UNIT_TEST(isr_nonstall,			test_isr_nonstall,			NULL, 2),
 	UNIT_TEST(is_intr1_pending,		test_is_intr1_pending,			NULL, 0),
 	UNIT_TEST(enable_disable_reset,		test_enable_disable_reset,		NULL, 0),
-	UNIT_TEST(wait_for_deferred_interrupts,	test_wait_for_deferred_interrupts,	NULL, 0),
 	UNIT_TEST(mc_free_env,			test_mc_free_env,			NULL, 0),
 };
 

userspace/units/mc/nvgpu-mc.h

@@ -329,35 +329,6 @@ int test_enable_disable_reset(struct unit_module *m, struct gk20a *g, void *args
  */
 int test_reset_mask(struct unit_module *m, struct gk20a *g, void *args);
 
-/**
- * Test specification for: test_wait_for_deferred_interrupts
- *
- * Description: Validate functionality of waiting for deferred interrupts.
- *
- * Test Type: Feature
- *
- * Targets: nvgpu_cic_wait_for_deferred_interrupts
- *
- * Input: test_mc_setup_env must have been run.
- *
- * Steps:
- * - Initialize cond structures required by the API.
- * - Set the irq count states in the gk20a struct to 0 to cause immediate
- *   completion.
- * - Call the API.
- * - Enable cond fault injection to simulate a timeouts.
- * - Set the irq count states in the gk20a struct to simulate pending stall
- *   interrupts.
- * - Call the API.
- * - Set the irq count states in the gk20a struct to simulate pending non-stall
- *   interrupts.
- * - Disable cond fault injection.
- *
- * Output: Returns PASS if expected result is met, FAIL otherwise.
- */
-int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
-					void *args);
-
 /**
  * @}
  */

userspace/units/rc/nvgpu-rc.c

@@ -38,6 +38,7 @@
 #include <nvgpu/rc.h>
 #include <nvgpu/pbdma_status.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/cic_rm.h>
 
 #include "../fifo/nvgpu-fifo-common.h"
 #include "../fifo/nvgpu-fifo-gv11b.h"
@@ -96,6 +97,16 @@ int test_rc_init(struct unit_module *m, struct gk20a *g, void *args)
 
 	nvgpu_device_init(g);
 
+	ret = nvgpu_cic_rm_setup(g);
+	if (ret != 0) {
+		unit_return_fail(m, "CIC-rm init failed\n");
+	}
+
+	ret = nvgpu_cic_rm_init_vars(g);
+	if (ret != 0) {
+		unit_return_fail(m, "CIC-rm vars init failed\n");
+	}
+
 	g->ops.gr.init.get_no_of_sm = stub_gv11b_gr_init_get_no_of_sm;
 
 	g->ops.ecc.ecc_init_support(g);