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gpu: nvgpu: Move intr data members from MC to CIC

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Move interrupt specific data-members from common.mc to common.cic
Some of these data members like sw_irq_stall_last_handled_cond need
To be initialized much earlier during the OS specific init/probe stage.
Also, some more members from struct nvgpu_interrupts(like stall_size,
stall_lines[]), which will soon be moved to CIC will also need to be
initialized early during the OS specific probe stage.
However, the chip specific LUT can only be initialized after the
hal_init stage where the HALs are all initialized.
Split the CIC init to accommodate the above initialization requirements.

JIRA NVGPU-6899

Change-Id: I9333db4cde59bb0aa8f6eb9f8472f00369817a5d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552535
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2021-05-27 03:22:47 +00:00
committed by mobile promotions
parent 695dcab297
commit b33079d47e
23 changed files with 477 additions and 133 deletions
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32
userspace/units/mc/nvgpu-mc.c
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@@ -653,37 +653,6 @@ int test_enable_disable_reset(struct unit_module *m, struct gk20a *g, void *args
return UNIT_SUCCESS;
}
int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
void *args)
{
struct nvgpu_posix_fault_inj *cond_fi =
nvgpu_cond_get_fault_injection();
nvgpu_cond_init(&g->mc.sw_irq_stall_last_handled_cond);
nvgpu_cond_init(&g->mc.sw_irq_nonstall_last_handled_cond);
/* immediate completion */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* cause timeout */
nvgpu_posix_enable_fault_injection(cond_fi, true, 0);
/* wait on stall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 1);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* wait on nonstall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* disable the fault injection */
nvgpu_posix_enable_fault_injection(cond_fi, false, 0);
return UNIT_SUCCESS;
}
struct unit_module_test mc_tests[] = {
UNIT_TEST(mc_setup_env, test_mc_setup_env, NULL, 0),
UNIT_TEST(unit_config, test_unit_config, NULL, 2),
@@ -695,7 +664,6 @@ struct unit_module_test mc_tests[] = {
UNIT_TEST(isr_nonstall, test_isr_nonstall, NULL, 2),
UNIT_TEST(is_intr1_pending, test_is_intr1_pending, NULL, 0),
UNIT_TEST(enable_disable_reset, test_enable_disable_reset, NULL, 0),
UNIT_TEST(wait_for_deferred_interrupts, test_wait_for_deferred_interrupts, NULL, 0),
UNIT_TEST(mc_free_env, test_mc_free_env, NULL, 0),
};