From b38b8a794dc2298c017d86ce036f8e5754209c64 Mon Sep 17 00:00:00 2001 From: Ramesh Mylavarapu Date: Tue, 9 Feb 2021 16:41:02 +0530 Subject: [PATCH] gpu: nvgpu-next: Update pg pre and post init structs SECURITY_HARDENING feature in pmu ucode leads to failure in pg pre and post init rpcs due to mismatch is interface struct size. This change will update pg pre and post init nvgpu-pmu interface structs as per pmu ucode. NVGPU-6421 Signed-off-by: Ramesh Mylavarapu Change-Id: Ied9179b3a7ee1923dba56e792979115f3a19f7e5 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551026 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h index 05bc90d42..0d6893635 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h @@ -23,6 +23,7 @@ #define NVGPU_PMU_PG_SW_GA10B_H #include +#include struct gk20a; @@ -37,6 +38,7 @@ enum { NV_PMU_LPWR_GRP_CTRL_ID_GR = 0, NV_PMU_LPWR_GRP_CTRL_ID_MS, + NV_PMU_LPWR_GRP_CTRL_ID_EI, NV_PMU_LPWR_GRP_CTRL_ID__COUNT, }; @@ -76,11 +78,23 @@ struct pmu_rpc_struct_lpwr_loading_pre_init */ struct pmu_rpc_struct_lpwr_loading_post_init { - /* [IN/OUT] Must be first field in RPC structure */ + /* + * [IN/OUT] Must be first field in RPC structure + */ struct nv_pmu_rpc_header hdr; - /* Must be last field in RPC structure.*/ - u32 scratch[5]; -}; + /* + * Voltage rail data in LPWR + */ + struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; + /* + * [IN] Dummy array to match with pmu struct + */ + bool dummy; + /* + * Must be last field in RPC structure. + */ + u32 scratch[1]; + }; struct pmu_rpc_struct_lpwr_loading_pg_ctrl_init {