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gpu: nvgpu: move regops to separate unit
Move regops (gk20a/regops_gk20a.c) to separate unit common/regops/regops.c Move corresponding header (gk20a/regops_gk20a.h) to include/nvgpu/regops.h Move rest of the platform HAL files to common/regops/ as well Fix all the header includes to include new public header Remove *_apply_smpc_war() declarations from headers. Corresponding functions were cleaned up already, and declarations were left somehow Jira NVGPU-620 Change-Id: I8b8065b9c91f69809bdeb1b4caecdc7582c8a992 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1998723 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
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mobile promotions
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parent
eb887094e4
commit
b40c655e12
472
drivers/gpu/nvgpu/common/regops/regops.c
Normal file
472
drivers/gpu/nvgpu/common/regops/regops.c
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@@ -0,0 +1,472 @@
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/*
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* Tegra GK20A GPU Debugger Driver Register Ops
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*
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* Copyright (c) 2013-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gk20a/gr_gk20a.h"
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#include <nvgpu/log.h>
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#include <nvgpu/bsearch.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/regops.h>
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static int regop_bsearch_range_cmp(const void *pkey, const void *pelem)
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{
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const u32 key = *(const u32 *)pkey;
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const struct regop_offset_range *prange =
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(const struct regop_offset_range *)pelem;
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if (key < prange->base) {
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return -1;
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} else if (prange->base <= key && key < (U32(prange->base) +
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(U32(prange->count) * U32(4)))) {
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return 0;
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}
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return 1;
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}
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static inline bool linear_search(u32 offset, const u32 *list, int size)
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{
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int i;
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for (i = 0; i < size; i++) {
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if (list[i] == offset) {
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return true;
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}
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}
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return false;
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}
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/*
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* In order to perform a context relative op the context has
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* to be created already... which would imply that the
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* context switch mechanism has already been put in place.
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* So by the time we perform such an opertation it should always
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* be possible to query for the appropriate context offsets, etc.
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*
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* But note: while the dbg_gpu bind requires the a channel fd,
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* it doesn't require an allocated gr/compute obj at that point...
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*/
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static bool gr_context_info_available(struct gr_gk20a *gr)
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{
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int err;
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nvgpu_mutex_acquire(&gr->ctx_mutex);
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err = !gr->ctx_vars.golden_image_initialized;
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nvgpu_mutex_release(&gr->ctx_mutex);
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if (err != 0) {
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return false;
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}
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return true;
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}
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static bool validate_reg_ops(struct gk20a *g,
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u32 *ctx_rd_count, u32 *ctx_wr_count,
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struct nvgpu_dbg_reg_op *ops,
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u32 op_count,
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bool is_profiler);
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int exec_regops_gk20a(struct gk20a *g,
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struct channel_gk20a *ch,
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struct nvgpu_dbg_reg_op *ops,
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u64 num_ops,
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bool is_profiler,
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bool *is_current_ctx)
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{
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int err = 0;
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unsigned int i;
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u32 data32_lo = 0, data32_hi = 0;
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u32 ctx_rd_count = 0, ctx_wr_count = 0;
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bool skip_read_lo, skip_read_hi;
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bool ok;
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, " ");
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/* For vgpu, the regops routines need to be handled in the
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* context of the server and support for that does not exist.
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*
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* The two users of the regops interface are the compute driver
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* and tools. The compute driver will work without a functional
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* regops implementation, so we return -ENOSYS. This will allow
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* compute apps to run with vgpu. Tools will not work in this
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* configuration and are not required to work at this time. */
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if (g->is_virtual) {
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return -ENOSYS;
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}
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ok = validate_reg_ops(g, &ctx_rd_count, &ctx_wr_count,
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ops, num_ops, is_profiler);
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if (!ok) {
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nvgpu_err(g, "invalid op(s)");
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err = -EINVAL;
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/* each op has its own err/status */
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goto clean_up;
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}
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/* be sure that ctx info is in place if there are ctx ops */
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if ((ctx_wr_count | ctx_rd_count) != 0U) {
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if (!gr_context_info_available(&g->gr)) {
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nvgpu_err(g, "gr context data not available");
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return -ENODEV;
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}
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}
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for (i = 0; i < num_ops; i++) {
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/* if it isn't global then it is done in the ctx ops... */
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if (ops[i].type != REGOP(TYPE_GLOBAL)) {
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continue;
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}
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switch (ops[i].op) {
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case REGOP(READ_32):
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ops[i].value_hi = 0;
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ops[i].value_lo = gk20a_readl(g, ops[i].offset);
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nvgpu_log(g, gpu_dbg_gpu_dbg, "read_32 0x%08x from 0x%08x",
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ops[i].value_lo, ops[i].offset);
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break;
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case REGOP(READ_64):
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ops[i].value_lo = gk20a_readl(g, ops[i].offset);
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ops[i].value_hi =
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gk20a_readl(g, ops[i].offset + 4U);
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nvgpu_log(g, gpu_dbg_gpu_dbg, "read_64 0x%08x:%08x from 0x%08x",
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ops[i].value_hi, ops[i].value_lo,
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ops[i].offset);
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break;
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case REGOP(WRITE_32):
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case REGOP(WRITE_64):
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/* some of this appears wonky/unnecessary but
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we've kept it for compat with existing
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debugger code. just in case... */
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skip_read_lo = skip_read_hi = false;
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if (ops[i].and_n_mask_lo == ~(u32)0) {
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data32_lo = ops[i].value_lo;
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skip_read_lo = true;
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}
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if ((ops[i].op == REGOP(WRITE_64)) &&
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(ops[i].and_n_mask_hi == ~(u32)0)) {
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data32_hi = ops[i].value_hi;
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skip_read_hi = true;
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}
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/* read first 32bits */
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if (skip_read_lo == false) {
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data32_lo = gk20a_readl(g, ops[i].offset);
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data32_lo &= ~ops[i].and_n_mask_lo;
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data32_lo |= ops[i].value_lo;
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}
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/* if desired, read second 32bits */
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if ((ops[i].op == REGOP(WRITE_64)) &&
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!skip_read_hi) {
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data32_hi = gk20a_readl(g, ops[i].offset + 4U);
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data32_hi &= ~ops[i].and_n_mask_hi;
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data32_hi |= ops[i].value_hi;
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}
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/* now update first 32bits */
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gk20a_writel(g, ops[i].offset, data32_lo);
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nvgpu_log(g, gpu_dbg_gpu_dbg, "Wrote 0x%08x to 0x%08x ",
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data32_lo, ops[i].offset);
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/* if desired, update second 32bits */
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if (ops[i].op == REGOP(WRITE_64)) {
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gk20a_writel(g, ops[i].offset + 4U, data32_hi);
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nvgpu_log(g, gpu_dbg_gpu_dbg, "Wrote 0x%08x to 0x%08x ",
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data32_hi, ops[i].offset + 4U);
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}
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break;
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/* shouldn't happen as we've already screened */
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default:
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BUG();
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err = -EINVAL;
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goto clean_up;
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break;
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}
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}
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if ((ctx_wr_count | ctx_rd_count) != 0U) {
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err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops,
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ctx_wr_count, ctx_rd_count,
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is_current_ctx);
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if (err != 0) {
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nvgpu_warn(g, "failed to perform ctx ops\n");
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goto clean_up;
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}
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}
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clean_up:
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nvgpu_log(g, gpu_dbg_gpu_dbg, "ret=%d", err);
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return err;
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}
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static int validate_reg_op_info(struct nvgpu_dbg_reg_op *op)
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{
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int err = 0;
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op->status = REGOP(STATUS_SUCCESS);
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switch (op->op) {
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case REGOP(READ_32):
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case REGOP(READ_64):
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case REGOP(WRITE_32):
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case REGOP(WRITE_64):
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break;
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default:
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op->status |= REGOP(STATUS_UNSUPPORTED_OP);
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err = -EINVAL;
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break;
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}
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switch (op->type) {
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case REGOP(TYPE_GLOBAL):
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case REGOP(TYPE_GR_CTX):
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case REGOP(TYPE_GR_CTX_TPC):
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case REGOP(TYPE_GR_CTX_SM):
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case REGOP(TYPE_GR_CTX_CROP):
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case REGOP(TYPE_GR_CTX_ZROP):
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case REGOP(TYPE_GR_CTX_QUAD):
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break;
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/*
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case NVGPU_DBG_GPU_REG_OP_TYPE_FB:
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*/
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default:
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op->status |= REGOP(STATUS_INVALID_TYPE);
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err = -EINVAL;
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break;
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}
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return err;
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}
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static bool check_whitelists(struct gk20a *g,
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struct nvgpu_dbg_reg_op *op,
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u32 offset,
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bool is_profiler)
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{
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bool valid = false;
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if (op->type == REGOP(TYPE_GLOBAL)) {
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/* search global list */
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valid = (g->ops.regops.get_global_whitelist_ranges != NULL) &&
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(bsearch(&offset,
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g->ops.regops.get_global_whitelist_ranges(),
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g->ops.regops.get_global_whitelist_ranges_count(),
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sizeof(*g->ops.regops.get_global_whitelist_ranges()),
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regop_bsearch_range_cmp) != NULL);
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/* if debug session, search context list */
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if ((!valid) && (!is_profiler)) {
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/* binary search context list */
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valid = (g->ops.regops.get_context_whitelist_ranges != NULL) &&
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(bsearch(&offset,
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g->ops.regops.get_context_whitelist_ranges(),
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g->ops.regops.get_context_whitelist_ranges_count(),
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sizeof(*g->ops.regops.get_context_whitelist_ranges()),
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regop_bsearch_range_cmp) != NULL);
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}
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/* if debug session, search runcontrol list */
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if ((!valid) && (!is_profiler)) {
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valid = (g->ops.regops.get_runcontrol_whitelist != NULL) &&
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linear_search(offset,
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g->ops.regops.get_runcontrol_whitelist(),
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g->ops.regops.get_runcontrol_whitelist_count());
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}
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} else if (op->type == REGOP(TYPE_GR_CTX)) {
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/* binary search context list */
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valid = (g->ops.regops.get_context_whitelist_ranges != NULL) &&
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(bsearch(&offset,
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g->ops.regops.get_context_whitelist_ranges(),
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g->ops.regops.get_context_whitelist_ranges_count(),
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sizeof(*g->ops.regops.get_context_whitelist_ranges()),
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regop_bsearch_range_cmp) != NULL);
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/* if debug session, search runcontrol list */
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if ((!valid) && (!is_profiler)) {
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valid = (g->ops.regops.get_runcontrol_whitelist != NULL) &&
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linear_search(offset,
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g->ops.regops.get_runcontrol_whitelist(),
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g->ops.regops.get_runcontrol_whitelist_count());
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}
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} else if (op->type == REGOP(TYPE_GR_CTX_QUAD)) {
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valid = (g->ops.regops.get_qctl_whitelist != NULL) &&
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linear_search(offset,
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g->ops.regops.get_qctl_whitelist(),
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g->ops.regops.get_qctl_whitelist_count());
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}
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return valid;
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}
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/* note: the op here has already been through validate_reg_op_info */
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static int validate_reg_op_offset(struct gk20a *g,
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struct nvgpu_dbg_reg_op *op,
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bool is_profiler)
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{
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int err;
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u32 buf_offset_lo, buf_offset_addr, num_offsets, offset;
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bool valid = false;
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op->status = 0;
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offset = op->offset;
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/* support only 24-bit 4-byte aligned offsets */
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if ((offset & 0xFF000003U) != 0U) {
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nvgpu_err(g, "invalid regop offset: 0x%x", offset);
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op->status |= REGOP(STATUS_INVALID_OFFSET);
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return -EINVAL;
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}
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valid = check_whitelists(g, op, offset, is_profiler);
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if ((op->op == REGOP(READ_64) || op->op == REGOP(WRITE_64)) && valid) {
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valid = check_whitelists(g, op, offset + 4U, is_profiler);
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}
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if (valid && (op->type != REGOP(TYPE_GLOBAL))) {
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err = gr_gk20a_get_ctx_buffer_offsets(g,
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op->offset,
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1,
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&buf_offset_lo,
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&buf_offset_addr,
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&num_offsets,
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op->type == REGOP(TYPE_GR_CTX_QUAD),
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op->quad);
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if (err != 0) {
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err = gr_gk20a_get_pm_ctx_buffer_offsets(g,
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op->offset,
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1,
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&buf_offset_lo,
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&buf_offset_addr,
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&num_offsets);
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if (err != 0) {
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op->status |= REGOP(STATUS_INVALID_OFFSET);
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return -EINVAL;
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}
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}
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if (num_offsets == 0U) {
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op->status |= REGOP(STATUS_INVALID_OFFSET);
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return -EINVAL;
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}
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}
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if (!valid) {
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nvgpu_err(g, "invalid regop offset: 0x%x", offset);
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op->status |= REGOP(STATUS_INVALID_OFFSET);
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return -EINVAL;
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}
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return 0;
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}
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static bool validate_reg_ops(struct gk20a *g,
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u32 *ctx_rd_count, u32 *ctx_wr_count,
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struct nvgpu_dbg_reg_op *ops,
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u32 op_count,
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bool is_profiler)
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{
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u32 i;
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bool ok = true;
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bool gr_ctx_ops = false;
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/* keep going until the end so every op can get
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* a separate error code if needed */
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for (i = 0; i < op_count; i++) {
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if (validate_reg_op_info(&ops[i]) != 0) {
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ok = false;
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break;
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}
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if (reg_op_is_gr_ctx(ops[i].type)) {
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if (reg_op_is_read(ops[i].op)) {
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(*ctx_rd_count)++;
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} else {
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(*ctx_wr_count)++;
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}
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gr_ctx_ops = true;
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}
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|
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/* context operations are not valid on profiler session */
|
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if (gr_ctx_ops && is_profiler) {
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ok = false;
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break;
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}
|
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|
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/* if "allow_all" flag enabled, dont validate offset */
|
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if (!g->allow_all) {
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if (validate_reg_op_offset(g, &ops[i],
|
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is_profiler) != 0) {
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ok = false;
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break;
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}
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}
|
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}
|
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|
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if (ok) {
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nvgpu_log(g, gpu_dbg_gpu_dbg, "ctx_wrs:%d ctx_rds:%d",
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*ctx_wr_count, *ctx_rd_count);
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}
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return ok;
|
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}
|
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|
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/* exported for tools like cyclestats, etc */
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bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset)
|
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{
|
||||
bool valid = bsearch(&offset,
|
||||
g->ops.regops.get_global_whitelist_ranges(),
|
||||
g->ops.regops.get_global_whitelist_ranges_count(),
|
||||
sizeof(*g->ops.regops.get_global_whitelist_ranges()),
|
||||
regop_bsearch_range_cmp) != NULL;
|
||||
return valid;
|
||||
}
|
||||
|
||||
bool reg_op_is_gr_ctx(u8 type)
|
||||
{
|
||||
return type == REGOP(TYPE_GR_CTX) ||
|
||||
type == REGOP(TYPE_GR_CTX_TPC) ||
|
||||
type == REGOP(TYPE_GR_CTX_SM) ||
|
||||
type == REGOP(TYPE_GR_CTX_CROP) ||
|
||||
type == REGOP(TYPE_GR_CTX_ZROP) ||
|
||||
type == REGOP(TYPE_GR_CTX_QUAD);
|
||||
}
|
||||
|
||||
bool reg_op_is_read(u8 op)
|
||||
{
|
||||
return op == REGOP(READ_32) ||
|
||||
op == REGOP(READ_64);
|
||||
}
|
||||
Reference in New Issue
Block a user