gpu: nvgpu: move regops to separate unit

Move regops (gk20a/regops_gk20a.c) to separate unit common/regops/regops.c
Move corresponding header (gk20a/regops_gk20a.h) to include/nvgpu/regops.h

Move rest of the platform HAL files to common/regops/ as well

Fix all the header includes to include new public header

Remove *_apply_smpc_war() declarations from headers. Corresponding
functions were cleaned up already, and declarations were left somehow

Jira NVGPU-620

Change-Id: I8b8065b9c91f69809bdeb1b4caecdc7582c8a992
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1998723
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -65,6 +65,12 @@ nvgpu-y += common/bus/bus_gk20a.o \
 	common/boardobj/boardobjgrpmask.o \
 	common/boardobj/boardobjgrp_e255.o \
 	common/boardobj/boardobjgrp_e32.o \
+	common/regops/regops.o \
+	common/regops/regops_gm20b.o \
+	common/regops/regops_gp10b.o \
+	common/regops/regops_gv100.o \
+	common/regops/regops_gv11b.o \
+	common/regops/regops_tu104.o \
 	common/ltc/ltc.o \
 	common/ltc/ltc_gm20b.o \
 	common/ltc/ltc_gp10b.o \
@@ -319,7 +325,6 @@ nvgpu-y += \
 	common/nvlink/nvlink_tu104.o \
 	gk20a/ce2_gk20a.o \
 	gk20a/fifo_gk20a.o \
-	gk20a/regops_gk20a.o \
 	gk20a/gr_gk20a.o \
 	gk20a/mm_gk20a.o \
 	gk20a/fence_gk20a.o \
@@ -328,8 +333,7 @@ nvgpu-y += \
 	gm20b/gr_gm20b.o \
 	gm20b/clk_gm20b.o \
 	gm20b/fifo_gm20b.o \
-	gm20b/mm_gm20b.o \
+	gm20b/mm_gm20b.o
-	gm20b/regops_gm20b.o
 
 nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \
 	tu104/fecs_trace_tu104.o \
@@ -372,7 +376,6 @@ nvgpu-y += \
 	gp10b/fifo_gp10b.o  \
 	gp10b/mm_gp10b.o \
 	gp10b/hal_gp10b.o \
-	gp10b/regops_gp10b.o \
 	gp10b/fecs_trace_gp10b.o \
 	gp10b/gp10b.o \
 	gp10b/ecc_gp10b.o \
@@ -386,13 +389,11 @@ nvgpu-y += \
 	gv11b/mm_gv11b.o \
 	gv11b/ce_gv11b.o \
 	gv11b/subctx_gv11b.o \
-	gv11b/regops_gv11b.o \
 	gv11b/ecc_gv11b.o \
 	gv100/mm_gv100.o \
 	gv100/bios_gv100.o \
 	gv100/fifo_gv100.o \
 	gv100/gr_gv100.o \
-	gv100/regops_gv100.o \
 	gv100/hal_gv100.o \
 	gv100/gsp_gv100.o \
 	gv100/clk_gv100.o \
@@ -405,5 +406,4 @@ nvgpu-y += \
 	tu104/fbpa_tu104.o \
 	tu104/sec2_tu104.o \
 	tu104/ecc_tu104.o \
-	tu104/regops_tu104.o \
 	gp106/clk_gp106.o

drivers/gpu/nvgpu/Makefile.sources

@@ -180,6 +180,12 @@ srcs += common/sim.c \
 	common/boardobj/boardobjgrpmask.c \
 	common/boardobj/boardobjgrp_e255.c \
 	common/boardobj/boardobjgrp_e32.c \
+	common/regops/regops.c \
+	common/regops/regops_gm20b.c \
+	common/regops/regops_gp10b.c \
+	common/regops/regops_gv100.c \
+	common/regops/regops_gv11b.c \
+	common/regops/regops_tu104.c \
 	common/nvdec/nvdec_gp106.c \
 	common/nvdec/nvdec_tu104.c \
 	common/pmu/pstate/pstate.c \
@@ -216,7 +222,6 @@ srcs += common/sim.c \
 	common/ptimer/ptimer_gk20a.c \
 	gk20a/ce2_gk20a.c \
 	gk20a/fifo_gk20a.c \
-	gk20a/regops_gk20a.c \
 	gk20a/gr_gk20a.c \
 	gk20a/mm_gk20a.c \
 	gk20a/fence_gk20a.c \
@@ -225,13 +230,11 @@ srcs += common/sim.c \
 	gm20b/clk_gm20b.c \
 	gm20b/fifo_gm20b.c \
 	gm20b/mm_gm20b.c \
-	gm20b/regops_gm20b.c \
 	gp10b/gr_gp10b.c  \
 	gp10b/ce_gp10b.c \
 	gp10b/fifo_gp10b.c  \
 	gp10b/mm_gp10b.c \
 	gp10b/hal_gp10b.c \
-	gp10b/regops_gp10b.c \
 	gp10b/clk_arb_gp10b.c \
 	gp10b/fecs_trace_gp10b.c \
 	gp10b/gp10b.c \
@@ -243,7 +246,6 @@ srcs += common/sim.c \
 	gv11b/mm_gv11b.c \
 	gv11b/ce_gv11b.c \
 	gv11b/subctx_gv11b.c \
-	gv11b/regops_gv11b.c \
 	gv11b/ecc_gv11b.c \
 	gp106/gr_gp106.c \
 	gp106/sec2_gp106.c \
@@ -253,7 +255,6 @@ srcs += common/sim.c \
 	gv100/bios_gv100.c \
 	gv100/fifo_gv100.c \
 	gv100/gr_gv100.c \
-	gv100/regops_gv100.c \
 	common/nvlink/nvlink_gv100.c \
 	common/nvlink/nvlink_tu104.c	\
 	gv100/hal_gv100.c \
@@ -272,7 +273,6 @@ srcs += common/sim.c \
 	tu104/hal_tu104.c	\
 	tu104/sec2_tu104.c	\
 	tu104/func_tu104.c	\
-	tu104/regops_tu104.c	\
 	tu104/fecs_trace_tu104.c \
 	vgpu/vgpu.c		\
 	vgpu/fifo_vgpu.c	\

drivers/gpu/nvgpu/common/regops/regops.c

@@ -22,14 +22,14 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include "gr_gk20a.h"
+#include "gk20a/gr_gk20a.h"
-#include "regops_gk20a.h"
 
 #include <nvgpu/log.h>
 #include <nvgpu/bsearch.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
 
 static int regop_bsearch_range_cmp(const void *pkey, const void *pelem)
 {

drivers/gpu/nvgpu/common/regops/regops_gm20b.c

@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,8 @@
  */
 
 #include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
 
-#include "gk20a/regops_gk20a.h"
 #include "regops_gm20b.h"
 
 static const struct regop_offset_range gm20b_global_whitelist_ranges[] = {

drivers/gpu/nvgpu/common/regops/regops_gm20b.h

@@ -2,7 +2,7 @@
  *
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2018 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2019 NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,10 +22,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef NVGPU_GM20B_REGOPS_GM20B_H
+#ifndef NVGPU_REGOPS_GM20B_H
-#define NVGPU_GM20B_REGOPS_GM20B_H
+#define NVGPU_REGOPS_GM20B_H
-
-struct dbg_session_gk20a;
 
 const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void);
 u64 gm20b_get_global_whitelist_ranges_count(void);
@@ -39,6 +37,5 @@ const u32 *gm20b_get_qctl_whitelist(void);
 u64 gm20b_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void);
 u64 gm20b_get_qctl_whitelist_ranges_count(void);
-int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
-#endif /* NVGPU_GM20B_REGOPS_GM20B_H */
+#endif /* NVGPU_REGOPS_GM20B_H */

drivers/gpu/nvgpu/common/regops/regops_gp10b.c

@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,8 @@
  */
 
 #include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
 
-#include "gk20a/regops_gk20a.h"
 #include "regops_gp10b.h"
 
 static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {

drivers/gpu/nvgpu/common/regops/regops_gp10b.h

@@ -2,7 +2,7 @@
  *
  * Tegra GP10B GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,8 +25,6 @@
 #ifndef NVGPU_REGOPS_GP10B_H
 #define NVGPU_REGOPS_GP10B_H
 
-struct dbg_session_gk20a;
-
 const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void);
 u64 gp10b_get_global_whitelist_ranges_count(void);
 const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void);
@@ -39,6 +37,5 @@ const u32 *gp10b_get_qctl_whitelist(void);
 u64 gp10b_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
 u64 gp10b_get_qctl_whitelist_ranges_count(void);
-int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* NVGPU_REGOPS_GP10B_H */

drivers/gpu/nvgpu/common/regops/regops_gv100.c

@@ -1,7 +1,7 @@
 /*
  * Tegra GV100 GPU Driver Register Ops
  *
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,8 @@
  */
 
 #include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
 
-#include "gk20a/regops_gk20a.h"
 #include "regops_gv100.h"
 
 static const struct regop_offset_range gv100_global_whitelist_ranges[] = {

drivers/gpu/nvgpu/common/regops/regops_gv100.h

@@ -2,7 +2,7 @@
  *
  * Tegra GV100 GPU Driver Register Ops
  *
- * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -37,6 +37,5 @@ const u32 *gv100_get_qctl_whitelist(void);
 u64 gv100_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void);
 u64 gv100_get_qctl_whitelist_ranges_count(void);
-int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* NVGPU_REGOPS_GV100_H */

drivers/gpu/nvgpu/common/regops/regops_gv11b.c

@@ -1,7 +1,7 @@
 /*
  * Tegra GV11b GPU Driver Register Ops
  *
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,8 @@
  */
 
 #include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
 
-#include "gk20a/regops_gk20a.h"
 #include "regops_gv11b.h"
 
 static const struct regop_offset_range gv11b_global_whitelist_ranges[] = {

drivers/gpu/nvgpu/common/regops/regops_gv11b.h

@@ -2,7 +2,7 @@
  *
  * Tegra GV11B GPU Driver Register Ops
  *
- * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -37,6 +37,5 @@ const u32 *gv11b_get_qctl_whitelist(void);
 u64 gv11b_get_qctl_whitelist_count(void);
 const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void);
 u64 gv11b_get_qctl_whitelist_ranges_count(void);
-int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* NVGPU_REGOPS_GV11B_H */

drivers/gpu/nvgpu/common/regops/regops_tu104.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,7 @@
  */
 
 #include <nvgpu/gk20a.h>
-
+#include <nvgpu/regops.h>
-#include "gk20a/regops_gk20a.h"
 
 #include "regops_tu104.h"
 

drivers/gpu/nvgpu/common/regops/regops_tu104.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -34,6 +34,5 @@ const u32 *tu104_get_qctl_whitelist(void);
 u64 tu104_get_qctl_whitelist_count(void);
 const struct regop_offset_range *tu104_get_qctl_whitelist_ranges(void);
 u64 tu104_get_qctl_whitelist_ranges_count(void);
-int tu104_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
 #endif /* NVGPU_REGOPS_TU104_H */

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -48,13 +48,13 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/unit.h>
 #include <nvgpu/string.h>
+#include <nvgpu/regops.h>
 #include <nvgpu/gr/global_ctx.h>
 #include <nvgpu/gr/ctx.h>
 
 #include "gr_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
 #include "gr_pri_gk20a.h"
-#include "regops_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -34,6 +34,7 @@
 #include <nvgpu/perfbuf.h>
 #include <nvgpu/cyclestats_snapshot.h>
 #include <nvgpu/fuse.h>
+#include <nvgpu/regops.h>
 
 #include "common/clock_gating/gm20b_gating_reglist.h"
 #include "common/bus/bus_gm20b.h"
@@ -53,18 +54,17 @@
 #include "common/pmu/acr_gm20b.h"
 #include "common/falcon/falcon_gk20a.h"
 #include "common/top/top_gm20b.h"
+#include "common/regops/regops_gm20b.h"
 
 #include "gk20a/ce2_gk20a.h"
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/mm_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
 #include "gr_gm20b.h"
 #include "fifo_gm20b.h"
 #include "mm_gm20b.h"
 #include "clk_gm20b.h"
-#include "regops_gm20b.h"
 #include "hal_gm20b.h"
 
 #include <nvgpu/hw/gm20b/hw_proj_gm20b.h>

drivers/gpu/nvgpu/gp10b/gr_gp10b.c

@@ -35,10 +35,10 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/regops.h>
 #include <nvgpu/gr/ctx.h>
 
 #include "gk20a/gr_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 
 #include "gm20b/gr_gm20b.h"
 #include "gp10b/gr_gp10b.h"

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -35,6 +35,7 @@
 #include <nvgpu/perfbuf.h>
 #include <nvgpu/cyclestats_snapshot.h>
 #include <nvgpu/fuse.h>
+#include <nvgpu/regops.h>
 
 #include "common/bus/bus_gk20a.h"
 #include "common/clock_gating/gp10b_gating_reglist.h"
@@ -64,11 +65,11 @@
 #include "common/falcon/falcon_gk20a.h"
 #include "common/top/top_gm20b.h"
 #include "common/top/top_gp10b.h"
+#include "common/regops/regops_gp10b.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
 #include "gk20a/mm_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
 #include "gp10b/gr_gp10b.h"
@@ -76,7 +77,6 @@
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
-#include "gp10b/regops_gp10b.h"
 #include "gp10b/ecc_gp10b.h"
 #include "gp10b/clk_arb_gp10b.h"
 

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -71,10 +71,10 @@
 #include "common/nvlink/nvlink_gv100.h"
 #include "common/nvlink/nvlink_tu104.h"
 #include "common/pmu/perf/perf_gv100.h"
+#include "common/regops/regops_gv100.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 #include "gk20a/mm_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
@@ -98,7 +98,6 @@
 #include "gv11b/ce_gv11b.h"
 #include "gv11b/mm_gv11b.h"
 #include "gv11b/fifo_gv11b.h"
-#include "gv11b/regops_gv11b.h"
 #include "gv11b/subctx_gv11b.h"
 
 #include "gv100.h"
@@ -108,7 +107,6 @@
 #include "gv100/fifo_gv100.h"
 #include "gv100/gr_gv100.h"
 #include "gv100/mm_gv100.h"
-#include "gv100/regops_gv100.h"
 #include "gv100/clk_gv100.h"
 
 #include <nvgpu/ptimer.h>
@@ -123,6 +121,7 @@
 #include <nvgpu/runlist.h>
 #include <nvgpu/perfbuf.h>
 #include <nvgpu/cyclestats_snapshot.h>
+#include <nvgpu/regops.h>
 
 #include <nvgpu/hw/gv100/hw_proj_gv100.h>
 #include <nvgpu/hw/gv100/hw_fifo_gv100.h>

drivers/gpu/nvgpu/gv11b/gr_gv11b.c

@@ -37,12 +37,12 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/bitops.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/nvgpu_err.h>
 
 #include "gk20a/gr_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 #include "gk20a/gr_pri_gk20a.h"
 
 #include "gm20b/gr_gm20b.h"

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -23,6 +23,7 @@
  */
 #include <nvgpu/gk20a.h>
 #include <nvgpu/fuse.h>
+#include <nvgpu/regops.h>
 
 #include "common/bus/bus_gk20a.h"
 #include "common/bus/bus_gp10b.h"
@@ -61,11 +62,11 @@
 #include "common/falcon/falcon_gk20a.h"
 #include "common/top/top_gm20b.h"
 #include "common/top/top_gp10b.h"
+#include "common/regops/regops_gv11b.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
 #include "gk20a/mm_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
 #include "gm20b/gr_gm20b.h"
@@ -87,7 +88,6 @@
 #include "ce_gv11b.h"
 #include "mm_gv11b.h"
 #include "fifo_gv11b.h"
-#include "regops_gv11b.h"
 #include "subctx_gv11b.h"
 #include "ecc_gv11b.h"
 

drivers/gpu/nvgpu/include/nvgpu/regops.h

@@ -21,8 +21,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef REGOPS_GK20A_H
+#ifndef NVGPU_REGOPS_H
-#define REGOPS_GK20A_H
+#define NVGPU_REGOPS_H
 
 /*
  * Register operations
@@ -89,4 +89,4 @@ bool reg_op_is_gr_ctx(u8 type);
 bool reg_op_is_read(u8 op);
 bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset);
 
-#endif /* REGOPS_GK20A_H */
+#endif /* NVGPU_REGOPS_H */

drivers/gpu/nvgpu/os/linux/driver_common.c

@@ -29,13 +29,13 @@
 #include <nvgpu/debug.h>
 #include <nvgpu/sizes.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/regops.h>
 
 #include "platform_gk20a.h"
 #include "module.h"
 #include "os_linux.h"
 #include "sysfs.h"
 #include "ioctl.h"
-#include "gk20a/regops_gk20a.h"
 
 #define EMC3D_DEFAULT_RATIO 750
 

drivers/gpu/nvgpu/os/linux/ioctl_dbg.c

@@ -34,11 +34,11 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/tsg.h>
+#include <nvgpu/regops.h>
 
 #include <nvgpu/linux/vm.h>
 
 #include "gk20a/gr_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 #include "os_linux.h"
 #include "platform_gk20a.h"
 #include "ioctl_dbg.h"

drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c

@@ -33,12 +33,12 @@
 #include <nvgpu/defaults.h>
 #include <nvgpu/ltc.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/regops.h>
 #include <nvgpu/clk_arb.h>
 
 #include "vgpu_linux.h"
 #include "vgpu/fecs_trace_vgpu.h"
 #include "vgpu/clk_vgpu.h"
-#include "gk20a/regops_gk20a.h"
 #include "gm20b/hal_gm20b.h"
 
 #include "os/linux/module.h"

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -76,10 +76,10 @@
 #include "common/top/top_gp10b.h"
 #include "common/nvlink/nvlink_gv100.h"
 #include "common/nvlink/nvlink_tu104.h"
+#include "common/regops/regops_tu104.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
-#include "gk20a/regops_gk20a.h"
 #include "gk20a/mm_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
@@ -107,14 +107,12 @@
 #include "gv11b/ce_gv11b.h"
 #include "gv11b/mm_gv11b.h"
 #include "gv11b/fifo_gv11b.h"
-#include "gv11b/regops_gv11b.h"
 #include "gv11b/subctx_gv11b.h"
 
 #include "gv100/bios_gv100.h"
 #include "gv100/fifo_gv100.h"
 #include "gv100/gr_gv100.h"
 #include "gv100/mm_gv100.h"
-#include "gv100/regops_gv100.h"
 #include "gv100/clk_arb_gv100.h"
 
 #include "tu104/fifo_tu104.h"
@@ -124,7 +122,6 @@
 #include "tu104/sec2_tu104.h"
 #include "tu104/ecc_tu104.h"
 #include "tu104/hal_tu104.h"
-#include "tu104/regops_tu104.h"
 #include "tu104/fecs_trace_tu104.h"
 
 #include <nvgpu/ptimer.h>
@@ -139,6 +136,7 @@
 #include <nvgpu/runlist.h>
 #include <nvgpu/perfbuf.h>
 #include <nvgpu/cyclestats_snapshot.h>
+#include <nvgpu/regops.h>
 
 #include <nvgpu/hw/tu104/hw_proj_tu104.h>
 #include <nvgpu/hw/tu104/hw_fifo_tu104.h>

drivers/gpu/nvgpu/vgpu/dbg_vgpu.c

@@ -28,8 +28,8 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/string.h>
+#include <nvgpu/regops.h>
 
-#include "gk20a/regops_gk20a.h"
 #include "dbg_vgpu.h"
 
 int vgpu_exec_regops(struct gk20a *g,

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -36,6 +36,7 @@
 #include "common/ltc/ltc_gp10b.h"
 #include "common/fuse/fuse_gm20b.h"
 #include "common/fuse/fuse_gp10b.h"
+#include "common/regops/regops_gp10b.h"
 
 #include "vgpu/fifo_vgpu.h"
 #include "vgpu/gr_vgpu.h"
@@ -57,7 +58,6 @@
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/gr_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
-#include "gp10b/regops_gp10b.h"
 #include "gp10b/clk_arb_gp10b.h"
 
 #include "gm20b/gr_gm20b.h"

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -40,6 +40,7 @@
 #include "common/ltc/ltc_gv11b.h"
 #include "common/fuse/fuse_gm20b.h"
 #include "common/fuse/fuse_gp10b.h"
+#include "common/regops/regops_gv11b.h"
 
 #include <nvgpu/gk20a.h>
 #include <gv11b/hal_gv11b.h>
@@ -72,7 +73,6 @@
 #include <gv11b/mm_gv11b.h>
 #include <gv11b/ce_gv11b.h>
 #include <gv11b/fifo_gv11b.h>
-#include <gv11b/regops_gv11b.h>
 #include <gv11b/gr_gv11b.h>
 
 #include <gv100/gr_gv100.h>