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gpu: nvgpu: fix MISRA 11.2 and 16.x in nvgpu_mem

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MISRA Rule 11.2 doesn't allow conversion to or from an incomplete type
pointer, as it may result incorrect point alignment and may further lead
to undefined behavior.

MISRA Rule 16.x requires all switch statements to be well-formed with
terminating break statement for every switch-clause.

This patch fixes 11.2 and 16.x violations in common.mm.nvgpu_mem.

Jira NVGPU-3339

Change-Id: I002393cc64d44826e6954d1bf6af71bd569e862f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-05-06 11:15:21 -07:00
committed by mobile promotions
parent b96ac290c8
commit b4590adae4
6 changed files with 47 additions and 43 deletions
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4
userspace/units/mm/nvgpu_sgt/nvgpu_sgt.c
View File

@@ -31,13 +31,13 @@
/* nvgpu_sgt_ops overrides for basic api testing */
#define EXPECTED_U64 0x123456789ABCDEF0ULL
static u64 ops_sgl_gpu_addr(struct gk20a *g, struct nvgpu_sgl *sgl,
static u64 ops_sgl_gpu_addr(struct gk20a *g, void *sgl,
struct nvgpu_gmmu_attrs *attrs)
{
return EXPECTED_U64;
}
static u64 ops_sgl_ipa(struct gk20a *g, struct nvgpu_sgl *sgl)
static u64 ops_sgl_ipa(struct gk20a *g, void *sgl)
{
return EXPECTED_U64;
}