diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c
index 72bd5ea81..328b34b84 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel.c
+++ b/drivers/gpu/nvgpu/common/fifo/channel.c
@@ -2716,3 +2716,80 @@ void nvgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch)
 {
 	nvgpu_free_inst_block(g, &ch->inst_block);
 }
+
+void nvgpu_channel_debug_dump_all(struct gk20a *g,
+		 struct gk20a_debug_output *o)
+{
+	struct fifo_gk20a *f = &g->fifo;
+	u32 chid;
+	struct nvgpu_channel_dump_info **infos;
+
+	infos = nvgpu_kzalloc(g, sizeof(*infos) * f->num_channels);
+	if (infos == NULL) {
+		gk20a_debug_output(o, "cannot alloc memory for channels");
+		return;
+	}
+
+	for (chid = 0U; chid < f->num_channels; chid++) {
+		struct channel_gk20a *ch = gk20a_channel_from_id(g, chid);
+
+		if (ch != NULL) {
+			struct nvgpu_channel_dump_info *info;
+
+			info = nvgpu_kzalloc(g, sizeof(*info));
+
+			/*
+			 * ref taken stays to below loop with
+			 * successful allocs
+			 */
+			if (info == NULL) {
+				gk20a_channel_put(ch);
+			} else {
+				infos[chid] = info;
+			}
+		}
+	}
+
+	for (chid = 0U; chid < f->num_channels; chid++) {
+		struct channel_gk20a *ch = &f->channel[chid];
+		struct nvgpu_channel_dump_info *info = infos[chid];
+		struct nvgpu_hw_semaphore *hw_sema = ch->hw_sema;
+
+		/* if this info exists, the above loop took a channel ref */
+		if (info == NULL) {
+			continue;
+		}
+
+		info->chid = ch->chid;
+		info->tsgid = ch->tsgid;
+		info->pid = ch->pid;
+		info->refs = nvgpu_atomic_read(&ch->ref_count);
+		info->deterministic = ch->deterministic;
+
+		if (hw_sema != NULL) {
+			info->sema.value = nvgpu_hw_semaphore_read(hw_sema);
+			info->sema.next =
+				(u32)nvgpu_hw_semaphore_read_next(hw_sema);
+			info->sema.addr = nvgpu_hw_semaphore_addr(hw_sema);
+		}
+
+		g->ops.channel.read_state(g, ch, &info->hw_state);
+		g->ops.ramfc.capture_ram_dump(g, ch, info);
+
+		gk20a_channel_put(ch);
+	}
+
+	gk20a_debug_output(o, "Channel Status - chip %-5s", g->name);
+	gk20a_debug_output(o, "---------------------------");
+	for (chid = 0U; chid < f->num_channels; chid++) {
+		struct nvgpu_channel_dump_info *info = infos[chid];
+
+		if (info != NULL) {
+			g->ops.channel.debug_dump(g, o, info);
+			nvgpu_kfree(g, info);
+		}
+	}
+	gk20a_debug_output(o, " ");
+
+	nvgpu_kfree(g, infos);
+}
diff --git a/drivers/gpu/nvgpu/common/fifo/channel_gk20a.c b/drivers/gpu/nvgpu/common/fifo/channel_gk20a.c
index 9e1340ac0..c50db89e3 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/common/fifo/channel_gk20a.c
@@ -28,6 +28,8 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/gk20a.h>
 
+#include "hal/fifo/pbdma_gm20b.h"
+
 #include "channel_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
@@ -103,3 +105,52 @@ void gk20a_channel_read_state(struct gk20a *g, struct channel_gk20a *ch,
 		status_v == ccsr_channel_status_on_eng_pending_acquire_v();
 	state->status_string = ccsr_chan_status_str[status_v];
 }
+
+void gk20a_channel_debug_dump(struct gk20a *g,
+				struct gk20a_debug_output *o,
+				struct nvgpu_channel_dump_info *info)
+{
+	gk20a_debug_output(o, "Channel ID: %d, TSG ID: %u, pid %d, refs %d; "
+				"deterministic = %s",
+			   info->chid,
+			   info->tsgid,
+			   info->pid,
+			   info->refs,
+			   info->deterministic ? "yes" : "no");
+	gk20a_debug_output(o, "  In use: %-3s  busy: %-3s  status: %s",
+			   info->hw_state.enabled ? "yes" : "no",
+			   info->hw_state.busy ? "yes" : "no",
+			   info->hw_state.status_string);
+	gk20a_debug_output(o,
+			   "  TOP       %016llx"
+			   "  PUT       %016llx  GET %016llx",
+			   info->inst.pb_top_level_get,
+			   info->inst.pb_put,
+			   info->inst.pb_get);
+	gk20a_debug_output(o,
+			   "  FETCH     %016llx"
+			   "  HEADER    %08x          COUNT %08x",
+			   info->inst.pb_fetch,
+			   info->inst.pb_header,
+			   info->inst.pb_count);
+	gk20a_debug_output(o,
+			   "  SYNCPOINT %08x %08x "
+			   "SEMAPHORE %08x %08x %08x %08x",
+			   info->inst.syncpointa,
+			   info->inst.syncpointb,
+			   info->inst.semaphorea,
+			   info->inst.semaphoreb,
+			   info->inst.semaphorec,
+			   info->inst.semaphored);
+
+	if (info->sema.addr == 0ULL) {
+		gk20a_debug_output(o,
+			"  SEMA STATE: val: %u next_val: %u addr: 0x%010llx",
+			info->sema.value,
+			info->sema.next,
+			info->sema.addr);
+	}
+	gm20b_pbdma_syncpoint_debug_dump(g, o, info);
+
+	gk20a_debug_output(o, " ");
+}
diff --git a/drivers/gpu/nvgpu/common/fifo/channel_gk20a.h b/drivers/gpu/nvgpu/common/fifo/channel_gk20a.h
index 812643afb..244d43d63 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/common/fifo/channel_gk20a.h
@@ -23,9 +23,11 @@
 #ifndef FIFO_CHANNEL_GK20A_H
 #define FIFO_CHANNEL_GK20A_H
 
-struct channel_gk20a;
 struct gk20a;
+struct channel_gk20a;
 struct nvgpu_channel_hw_state;
+struct gk20a_debug_output;
+struct nvgpu_channel_dump_info;
 
 void gk20a_channel_enable(struct channel_gk20a *ch);
 void gk20a_channel_disable(struct channel_gk20a *ch);
@@ -33,4 +35,7 @@ void gk20a_channel_unbind(struct channel_gk20a *ch);
 void gk20a_channel_read_state(struct gk20a *g, struct channel_gk20a *ch,
 		struct nvgpu_channel_hw_state *state);
 
+void gk20a_channel_debug_dump(struct gk20a *g,
+	     struct gk20a_debug_output *o,
+	     struct nvgpu_channel_dump_info *info);
 #endif /* FIFO_CHANNEL_GK20A_H */
diff --git a/drivers/gpu/nvgpu/common/fifo/channel_gv11b.c b/drivers/gpu/nvgpu/common/fifo/channel_gv11b.c
index 559759c09..0c033d4c1 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel_gv11b.c
+++ b/drivers/gpu/nvgpu/common/fifo/channel_gv11b.c
@@ -88,3 +88,45 @@ void gv11b_channel_free_subctx_header(struct channel_gk20a *ch)
 		nvgpu_gr_subctx_free(ch->g, ch->subctx, ch->vm);
 	}
 }
+
+void gv11b_channel_debug_dump(struct gk20a *g,
+			     struct gk20a_debug_output *o,
+			     struct nvgpu_channel_dump_info *info)
+{
+	gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ",
+			info->chid,
+			g->name,
+			info->tsgid,
+			info->pid,
+			info->refs,
+			info->deterministic ? ", deterministic" : "");
+	gk20a_debug_output(o, "channel status: %s in use %s %s\n",
+			info->hw_state.enabled ? "" : "not",
+			info->hw_state.status_string,
+			info->hw_state.busy ? "busy" : "not busy");
+	gk20a_debug_output(o,
+			"RAMFC : TOP: %016llx PUT: %016llx GET: %016llx "
+			"FETCH: %016llx\n"
+			"HEADER: %08x COUNT: %08x\n"
+			"SEMAPHORE: addr %016llx\n"
+			"payload %016llx execute %08x\n",
+			info->inst.pb_top_level_get,
+			info->inst.pb_put,
+			info->inst.pb_get,
+			info->inst.pb_fetch,
+			info->inst.pb_header,
+			info->inst.pb_count,
+			info->inst.sem_addr,
+			info->inst.sem_payload,
+			info->inst.sem_execute);
+
+	if (info->sema.addr != 0ULL) {
+		gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
+				   "next_val: 0x%08x addr: 0x%010llx\n",
+				  info->sema.value,
+				  info->sema.next,
+				  info->sema.addr);
+	}
+
+	gk20a_debug_output(o, "\n");
+}
diff --git a/drivers/gpu/nvgpu/common/fifo/channel_gv11b.h b/drivers/gpu/nvgpu/common/fifo/channel_gv11b.h
index c4609a532..5535de12b 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel_gv11b.h
+++ b/drivers/gpu/nvgpu/common/fifo/channel_gv11b.h
@@ -25,9 +25,11 @@
 
 #include <nvgpu/types.h>
 
-struct channel_gk20a;
 struct gk20a;
+struct channel_gk20a;
 struct nvgpu_channel_hw_state;
+struct gk20a_debug_output;
+struct nvgpu_channel_dump_info;
 
 void gv11b_channel_unbind(struct channel_gk20a *ch);
 u32 gv11b_channel_count(struct gk20a *g);
@@ -37,4 +39,7 @@ void gv11b_channel_reset_faulted(struct gk20a *g, struct channel_gk20a *ch,
 		bool eng, bool pbdma);
 void gv11b_channel_free_subctx_header(struct channel_gk20a *ch);
 
+void gv11b_channel_debug_dump(struct gk20a *g,
+	     struct gk20a_debug_output *o,
+	     struct nvgpu_channel_dump_info *info);
 #endif /* FIFO_CHANNEL_GV11B_H */
diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
index 98c9c00e8..6c89533fd 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -416,7 +416,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.preempt_channel = vgpu_fifo_preempt_channel,
 		.preempt_tsg = vgpu_fifo_preempt_tsg,
 		.tsg_set_timeslice = vgpu_tsg_set_timeslice,
-		.dump_channel_status_ramfc = NULL,
 		.is_preempt_pending = NULL,
 		.reset_enable_hw = NULL,
 		.teardown_ch_tsg = NULL,
@@ -535,6 +534,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.resume_all_serviceable_ch =
                         nvgpu_channel_resume_all_serviceable_ch,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.debug_dump = NULL,
 	},
 	.tsg = {
 		.open = vgpu_tsg_open,
diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
index a8d82654f..da16cadd8 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -499,7 +499,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.preempt_channel = vgpu_fifo_preempt_channel,
 		.preempt_tsg = vgpu_fifo_preempt_tsg,
 		.tsg_set_timeslice = vgpu_tsg_set_timeslice,
-		.dump_channel_status_ramfc = NULL,
 		.is_preempt_pending = gv11b_fifo_is_preempt_pending,
 		.reset_enable_hw = NULL,
 		.teardown_ch_tsg = NULL,
@@ -620,6 +619,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.resume_all_serviceable_ch =
                         nvgpu_channel_resume_all_serviceable_ch,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.debug_dump = NULL,
 	},
 	.tsg = {
 		.open = vgpu_tsg_open,
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index fe3ea87fa..b64c7dab8 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -980,146 +980,6 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index)
 	}
 }
 
-void gk20a_dump_channel_status_ramfc(struct gk20a *g,
-				     struct gk20a_debug_output *o,
-				     struct nvgpu_channel_dump_info *info)
-{
-	u32 syncpointa, syncpointb;
-
-	syncpointa = info->inst.syncpointa;
-	syncpointb = info->inst.syncpointb;
-
-	gk20a_debug_output(o, "Channel ID: %d, TSG ID: %u, pid %d, refs %d; deterministic = %s",
-			   info->chid,
-			   info->tsgid,
-			   info->pid,
-			   info->refs,
-			   info->deterministic ? "yes" : "no");
-	gk20a_debug_output(o, "  In use: %-3s  busy: %-3s  status: %s",
-			   info->hw_state.enabled ? "yes" : "no",
-			   info->hw_state.busy ? "yes" : "no",
-			   info->hw_state.status_string);
-	gk20a_debug_output(o,
-			   "  TOP       %016llx"
-			   "  PUT       %016llx  GET %016llx",
-			   info->inst.pb_top_level_get,
-			   info->inst.pb_put,
-			   info->inst.pb_get);
-	gk20a_debug_output(o,
-			   "  FETCH     %016llx"
-			   "  HEADER    %08x          COUNT %08x",
-			   info->inst.pb_fetch,
-			   info->inst.pb_header,
-			   info->inst.pb_count);
-	gk20a_debug_output(o,
-			   "  SYNCPOINT %08x %08x "
-			   "SEMAPHORE %08x %08x %08x %08x",
-			   syncpointa,
-			   syncpointb,
-			   info->inst.semaphorea,
-			   info->inst.semaphoreb,
-			   info->inst.semaphorec,
-			   info->inst.semaphored);
-
-	if (info->sema.addr == 0ULL) {
-		gk20a_debug_output(o,
-			"  SEMA STATE: val: %u next_val: %u addr: 0x%010llx",
-			info->sema.value,
-			info->sema.next,
-			info->sema.addr);
-	}
-
-#ifdef CONFIG_TEGRA_GK20A_NVHOST
-	if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v())
-		&& (pbdma_syncpointb_wait_switch_v(syncpointb) ==
-			pbdma_syncpointb_wait_switch_en_v())) {
-		gk20a_debug_output(o, "%s on syncpt %u (%s) val %u",
-			info->hw_state.pending_acquire ? "Waiting" : "Waited",
-			pbdma_syncpointb_syncpt_index_v(syncpointb),
-			nvgpu_nvhost_syncpt_get_name(g->nvhost_dev,
-				pbdma_syncpointb_syncpt_index_v(syncpointb)),
-			pbdma_syncpointa_payload_v(syncpointa));
-	}
-#endif
-
-	gk20a_debug_output(o, " ");
-}
-
-void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
-		 struct gk20a_debug_output *o)
-{
-	struct fifo_gk20a *f = &g->fifo;
-	u32 chid;
-	struct nvgpu_channel_dump_info **infos;
-
-	infos = nvgpu_kzalloc(g, sizeof(*infos) * f->num_channels);
-	if (infos == NULL) {
-		gk20a_debug_output(o, "cannot alloc memory for channels\n");
-		return;
-	}
-
-	for (chid = 0; chid < f->num_channels; chid++) {
-		struct channel_gk20a *ch = gk20a_channel_from_id(g, chid);
-
-		if (ch != NULL) {
-			struct nvgpu_channel_dump_info *info;
-
-			info = nvgpu_kzalloc(g, sizeof(*info));
-
-			/* ref taken stays to below loop with
-			 * successful allocs */
-			if (info == NULL) {
-				gk20a_channel_put(ch);
-			} else {
-				infos[chid] = info;
-			}
-		}
-	}
-
-	for (chid = 0; chid < f->num_channels; chid++) {
-		struct channel_gk20a *ch = &f->channel[chid];
-		struct nvgpu_channel_dump_info *info = infos[chid];
-		struct nvgpu_hw_semaphore *hw_sema = ch->hw_sema;
-
-		/* if this info exists, the above loop took a channel ref */
-		if (info == NULL) {
-			continue;
-		}
-
-		info->chid = ch->chid;
-		info->tsgid = ch->tsgid;
-		info->pid = ch->pid;
-		info->refs = nvgpu_atomic_read(&ch->ref_count);
-		info->deterministic = ch->deterministic;
-
-		if (hw_sema != NULL) {
-			info->sema.value = nvgpu_hw_semaphore_read(hw_sema);
-			info->sema.next =
-				(u32)nvgpu_hw_semaphore_read_next(hw_sema);
-			info->sema.addr = nvgpu_hw_semaphore_addr(hw_sema);
-		}
-
-		g->ops.channel.read_state(g, ch, &info->hw_state);
-		g->ops.ramfc.capture_ram_dump(g, ch, info);
-
-		gk20a_channel_put(ch);
-	}
-
-	gk20a_debug_output(o, "Channel Status - chip %-5s", g->name);
-	gk20a_debug_output(o, "---------------------------");
-	for (chid = 0; chid < f->num_channels; chid++) {
-		struct nvgpu_channel_dump_info *info = infos[chid];
-
-		if (info != NULL) {
-			g->ops.fifo.dump_channel_status_ramfc(g, o, info);
-			nvgpu_kfree(g, info);
-		}
-	}
-	gk20a_debug_output(o, " ");
-
-	nvgpu_kfree(g, infos);
-}
-
 static void nvgpu_fifo_pbdma_init_intr_descs(struct fifo_gk20a *f)
 {
 	struct gk20a *g = f->g;
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 7173bbbda..53347cd2c 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -213,37 +213,6 @@ struct fifo_gk20a {
 	u32 channel_base;
 };
 
-struct nvgpu_channel_dump_info {
-	u32 chid;
-	u32 tsgid;
-	int pid;
-	int refs;
-	bool deterministic;
-	struct nvgpu_channel_hw_state hw_state;
-	struct {
-		u64 pb_top_level_get;
-		u64 pb_put;
-		u64 pb_get;
-		u64 pb_fetch;
-		u32 pb_header;
-		u32 pb_count;
-		u64 sem_addr;
-		u64 sem_payload;
-		u32 sem_execute;
-		u32 syncpointa;
-		u32 syncpointb;
-		u32 semaphorea;
-		u32 semaphoreb;
-		u32 semaphorec;
-		u32 semaphored;
-	} inst;
-	struct {
-		u32 value;
-		u32 next;
-		u64 addr;
-	} sema;
-};
-
 int gk20a_init_fifo_setup_hw(struct gk20a *g);
 
 void gk20a_fifo_isr(struct gk20a *g);
@@ -297,11 +266,6 @@ static inline void gk20a_fifo_profile_snapshot(
 }
 #endif
 
-void gk20a_dump_channel_status_ramfc(struct gk20a *g,
-				     struct gk20a_debug_output *o,
-				     struct nvgpu_channel_dump_info *info);
-void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
-		 struct gk20a_debug_output *o);
 const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index);
 
 int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 7a5e99966..c1f028d08 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -629,7 +629,6 @@ static const struct gpu_ops gm20b_ops = {
 		.preempt_tsg = gk20a_fifo_preempt_tsg,
 		.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
 		.init_pbdma_info = gk20a_fifo_init_pbdma_info,
-		.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
 		.is_preempt_pending = gk20a_fifo_is_preempt_pending,
 		.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
 		.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
@@ -759,6 +758,7 @@ static const struct gpu_ops gm20b_ops = {
 		.resume_all_serviceable_ch =
                         nvgpu_channel_resume_all_serviceable_ch,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.debug_dump = gk20a_channel_debug_dump,
 	},
 	.tsg = {
 		.enable = gk20a_tsg_enable,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 3828a3ca2..8881f03af 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -718,7 +718,6 @@ static const struct gpu_ops gp10b_ops = {
 		.preempt_tsg = gk20a_fifo_preempt_tsg,
 		.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
 		.init_pbdma_info = gk20a_fifo_init_pbdma_info,
-		.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
 		.is_preempt_pending = gk20a_fifo_is_preempt_pending,
 		.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
 		.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
@@ -851,6 +850,7 @@ static const struct gpu_ops gp10b_ops = {
 		.resume_all_serviceable_ch =
                         nvgpu_channel_resume_all_serviceable_ch,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.debug_dump = gk20a_channel_debug_dump,
 	},
 	.tsg = {
 		.enable = gk20a_tsg_enable,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index f7daaf11a..c26720f20 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -900,7 +900,6 @@ static const struct gpu_ops gv100_ops = {
 		.preempt_tsg = gv11b_fifo_preempt_tsg,
 		.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
 		.init_pbdma_info = gk20a_fifo_init_pbdma_info,
-		.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
 		.is_preempt_pending = gv11b_fifo_is_preempt_pending,
 		.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
 		.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
@@ -1034,6 +1033,7 @@ static const struct gpu_ops gv100_ops = {
                         nvgpu_channel_resume_all_serviceable_ch,
 		.set_error_notifier = nvgpu_set_error_notifier_if_empty,
 		.reset_faulted = gv11b_channel_reset_faulted,
+		.debug_dump = gv11b_channel_debug_dump,
 	},
 	.tsg = {
 		.enable = gv11b_tsg_enable,
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 484cfbd1d..7f5df9aca 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -93,48 +93,6 @@ void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
 		usermode_notify_channel_pending_id_f(hw_chid));
 }
 
-void gv11b_dump_channel_status_ramfc(struct gk20a *g,
-				     struct gk20a_debug_output *o,
-				     struct nvgpu_channel_dump_info *info)
-{
-	gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ",
-			info->chid,
-			g->name,
-			info->tsgid,
-			info->pid,
-			info->refs,
-			info->deterministic ? ", deterministic" : "");
-	gk20a_debug_output(o, "channel status: %s in use %s %s\n",
-			info->hw_state.enabled ? "" : "not",
-			info->hw_state.status_string,
-			info->hw_state.busy ? "busy" : "not busy");
-	gk20a_debug_output(o,
-			"RAMFC : TOP: %016llx PUT: %016llx GET: %016llx "
-			"FETCH: %016llx\n"
-			"HEADER: %08x COUNT: %08x\n"
-			"SEMAPHORE: addr %016llx\n"
-			"payload %016llx execute %08x\n",
-			info->inst.pb_top_level_get,
-			info->inst.pb_put,
-			info->inst.pb_get,
-			info->inst.pb_fetch,
-			info->inst.pb_header,
-			info->inst.pb_count,
-			info->inst.sem_addr,
-			info->inst.sem_payload,
-			info->inst.sem_execute);
-
-	if (info->sema.addr != 0ULL) {
-		gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
-				   "next_val: 0x%08x addr: 0x%010llx\n",
-				  info->sema.value,
-				  info->sema.next,
-				  info->sema.addr);
-	}
-
-	gk20a_debug_output(o, "\n");
-}
-
 u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g)
 {
 	/* using gr_idle_timeout for polling pdma/eng/runlist
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
index 5687871e7..337402a23 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
@@ -42,9 +42,6 @@ void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
 void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
 	u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id);
 
-void gv11b_dump_channel_status_ramfc(struct gk20a *g,
-				     struct gk20a_debug_output *o,
-				     struct nvgpu_channel_dump_info *info);
 int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
 		 unsigned int id_type);
 int gv11b_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 5afe390a3..0e374dc93 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -855,7 +855,6 @@ static const struct gpu_ops gv11b_ops = {
 		.preempt_tsg = gv11b_fifo_preempt_tsg,
 		.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
 		.init_pbdma_info = gk20a_fifo_init_pbdma_info,
-		.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
 		.is_preempt_pending = gv11b_fifo_is_preempt_pending,
 		.reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
 		.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
@@ -991,6 +990,7 @@ static const struct gpu_ops gv11b_ops = {
                         nvgpu_channel_resume_all_serviceable_ch,
 		.set_error_notifier = nvgpu_set_error_notifier_if_empty,
 		.reset_faulted = gv11b_channel_reset_faulted,
+		.debug_dump = gv11b_channel_debug_dump,
 	},
 	.tsg = {
 		.enable = gv11b_tsg_enable,
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
index 590fbb14b..5e8baa492 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
@@ -26,6 +26,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/debug.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/nvhost.h>
 #include <nvgpu/fifo.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pbdma_status.h>
@@ -458,3 +459,28 @@ bool gm20b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id,
 
 	return recover;
 }
+
+void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
+			     struct gk20a_debug_output *o,
+			     struct nvgpu_channel_dump_info *info)
+{
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+
+	u32 syncpointa, syncpointb;
+
+	syncpointa = info->inst.syncpointa;
+	syncpointb = info->inst.syncpointb;
+
+
+	if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v())
+		&& (pbdma_syncpointb_wait_switch_v(syncpointb) ==
+			pbdma_syncpointb_wait_switch_en_v())) {
+		gk20a_debug_output(o, "%s on syncpt %u (%s) val %u",
+			info->hw_state.pending_acquire ? "Waiting" : "Waited",
+			pbdma_syncpointb_syncpt_index_v(syncpointb),
+			nvgpu_nvhost_syncpt_get_name(g->nvhost_dev,
+				pbdma_syncpointb_syncpt_index_v(syncpointb)),
+			pbdma_syncpointa_payload_v(syncpointa));
+	}
+#endif
+}
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h
index 83c69371b..027408f7b 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h
@@ -27,6 +27,7 @@
 
 struct gk20a;
 struct gk20a_debug_output;
+struct nvgpu_channel_dump_info;
 
 void gm20b_pbdma_intr_enable(struct gk20a *g, bool enable);
 
@@ -50,5 +51,8 @@ u32 gm20b_pbdma_restartable_0_intr_descs(void);
 
 void gm20b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
 void gm20b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
+void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
+		     struct gk20a_debug_output *o,
+		     struct nvgpu_channel_dump_info *info);
 
 #endif /* NVGPU_PBDMA_GM20B_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h
index cabeea489..07adf3244 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h
@@ -30,6 +30,7 @@
 #include <nvgpu/atomic.h>
 #include <nvgpu/nvgpu_mem.h>
 #include <nvgpu/allocator.h>
+#include <nvgpu/debug.h>
 
 struct gk20a;
 struct dbg_session_gk20a;
@@ -39,6 +40,7 @@ struct nvgpu_channel_sync;
 struct nvgpu_gpfifo_userdata;
 struct nvgpu_gr_subctx;
 struct nvgpu_gr_ctx;
+struct gk20a_debug_output;
 
 /* Flags to be passed to nvgpu_channel_setup_bind() */
 #define NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR		BIT32(0)
@@ -93,6 +95,47 @@ struct gpfifo_desc {
 	void *pipe;
 };
 
+struct nvgpu_channel_hw_state {
+	bool enabled;
+	bool next;
+	bool ctx_reload;
+	bool busy;
+	bool pending_acquire;
+	bool eng_faulted;
+	const char *status_string;
+};
+
+struct nvgpu_channel_dump_info {
+	u32 chid;
+	u32 tsgid;
+	int pid;
+	int refs;
+	bool deterministic;
+	struct nvgpu_channel_hw_state hw_state;
+	struct {
+		u64 pb_top_level_get;
+		u64 pb_put;
+		u64 pb_get;
+		u64 pb_fetch;
+		u32 pb_header;
+		u32 pb_count;
+		u64 sem_addr;
+		u64 sem_payload;
+		u32 sem_execute;
+		u32 syncpointa;
+		u32 syncpointb;
+		u32 semaphorea;
+		u32 semaphoreb;
+		u32 semaphorec;
+		u32 semaphored;
+	} inst;
+	struct {
+		u32 value;
+		u32 next;
+		u64 addr;
+	} sema;
+};
+
 struct nvgpu_setup_bind_args {
 	u32 num_gpfifo_entries;
 	u32 num_inflight_jobs;
@@ -503,4 +546,6 @@ void nvgpu_channel_set_error_notifier(struct gk20a *g, struct channel_gk20a *ch,
 int nvgpu_channel_set_syncpt(struct channel_gk20a *ch);
 struct channel_gk20a *nvgpu_channel_refch_from_inst_ptr(struct gk20a *g,
 			u64 inst_ptr);
+void nvgpu_channel_debug_dump_all(struct gk20a *g,
+		 struct gk20a_debug_output *o);
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
index 68c22f765..0edeb1bc6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
@@ -41,16 +41,6 @@
 
 struct gk20a;
 
-struct nvgpu_channel_hw_state {
-	bool enabled;
-	bool next;
-	bool ctx_reload;
-	bool busy;
-	bool pending_acquire;
-	bool eng_faulted;
-	const char *status_string;
-};
-
 int nvgpu_fifo_init_support(struct gk20a *g);
 int nvgpu_fifo_setup_sw(struct gk20a *g);
 int nvgpu_fifo_setup_sw_common(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index f796b9983..4e0c3fff6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -99,6 +99,7 @@ typedef void (*global_ctx_mem_destroy_fn)(struct gk20a *g,
 #include <nvgpu/nvlink.h>
 #include <nvgpu/sim.h>
 #include <nvgpu/ecc.h>
+#include <nvgpu/channel.h>
 #include <nvgpu/tsg.h>
 #include <nvgpu/sec2/sec2.h>
 #include <nvgpu/cbc.h>
@@ -960,9 +961,6 @@ struct gpu_ops {
 		int (*init_engine_info)(struct fifo_gk20a *f);
 		u32 (*get_engines_mask_on_id)(struct gk20a *g,
 			u32 id, bool is_tsg);
-		void (*dump_channel_status_ramfc)(struct gk20a *g,
-				struct gk20a_debug_output *o,
-				struct nvgpu_channel_dump_info *info);
 		int (*is_preempt_pending)(struct gk20a *g, u32 id,
 			unsigned int id_type);
 		int (*reset_enable_hw)(struct gk20a *g);
@@ -1142,6 +1140,9 @@ struct gpu_ops {
 		void (*reset_faulted)(struct gk20a *g, struct channel_gk20a *ch,
 				bool eng, bool pbdma);
 		int (*set_syncpt)(struct channel_gk20a *ch);
+		void (*debug_dump)(struct gk20a *g,
+				struct gk20a_debug_output *o,
+				struct nvgpu_channel_dump_info *info);
 	} channel;
 	struct {
 		int (*open)(struct tsg_gk20a *tsg);
diff --git a/drivers/gpu/nvgpu/os/linux/debug.c b/drivers/gpu/nvgpu/os/linux/debug.c
index b0fd11e02..d1b832087 100644
--- a/drivers/gpu/nvgpu/os/linux/debug.c
+++ b/drivers/gpu/nvgpu/os/linux/debug.c
@@ -65,7 +65,7 @@ void gk20a_debug_output(struct gk20a_debug_output *o, const char *fmt, ...)
 
 void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
 {
-	gk20a_debug_dump_all_channel_status_ramfc(g, o);
+	nvgpu_channel_debug_dump_all(g, o);
 	g->ops.pbdma.dump_status(g, o);
 	g->ops.engine_status.dump_engine_status(g, o);
 }
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index 8ee54bbad..d217917e4 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -932,7 +932,6 @@ static const struct gpu_ops tu104_ops = {
 		.preempt_tsg = gv11b_fifo_preempt_tsg,
 		.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
 		.init_pbdma_info = gk20a_fifo_init_pbdma_info,
-		.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
 		.is_preempt_pending = gv11b_fifo_is_preempt_pending,
 		.reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
 		.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
@@ -1068,6 +1067,7 @@ static const struct gpu_ops tu104_ops = {
                         nvgpu_channel_resume_all_serviceable_ch,
 		.set_error_notifier = nvgpu_set_error_notifier_if_empty,
 		.reset_faulted = gv11b_channel_reset_faulted,
+		.debug_dump = gv11b_channel_debug_dump,
 	},
 	.tsg = {
 		.enable = gv11b_tsg_enable,