gpu: nvgpu: Falcon IMEM/DMEM dump support

- Added falcon interface/HAL for IMEM-copy-from
to read data from IMEM from given location with requested
size
-Added falcon interface to print data of IMEM/DMEM
from given location with requested size using falcon HAL.

JIRA NVGPU-105

Change-Id: I84cf7b5769b84a2baee2c7e65027539598ec1295
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514536
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

drivers/gpu/nvgpu/common/falcon/falcon.c

@@ -180,6 +180,21 @@ int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn,
 	return flcn_ops->copy_to_dmem(flcn, dst, src, size, port);
 }
 
+int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn,
+	u32 src, u8 *dst, u32 size, u8 port)
+{
+	struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
+	int status = -EINVAL;
+
+	if (flcn_ops->copy_from_imem)
+		status = flcn_ops->copy_from_imem(flcn, src, dst, size, port);
+	else
+		nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
+			flcn->flcn_id);
+
+	return status;
+}
+
 int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn,
 	u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag)
 {
@@ -196,6 +211,58 @@ int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn,
 	return status;
 }
 
+static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src,
+	u32 size, u32 mem_type)
+{
+	u32 buff[64] = {0};
+	u32 total_block_read = 0;
+	u32 byte_read_count = 0;
+	u32 i = 0;
+	u32 status = 0;
+
+	nvgpu_info(flcn->g, " offset 0x%x  size %d bytes", src, size);
+
+	total_block_read = size >> 8;
+	do {
+		byte_read_count = total_block_read ? sizeof(buff) : size;
+
+		if (!byte_read_count)
+			break;
+
+		if (mem_type == MEM_DMEM)
+			status = nvgpu_flcn_copy_from_dmem(flcn, src,
+				(u8 *)buff, byte_read_count, 0);
+		else
+			status = nvgpu_flcn_copy_from_imem(flcn, src,
+				(u8 *)buff, byte_read_count, 0);
+
+		if (status) {
+			nvgpu_err(flcn->g, "MEM print failed");
+			break;
+		}
+
+		for (i = 0; i < (byte_read_count >> 2); i += 4)
+			nvgpu_info(flcn->g, "%#06x: %#010x %#010x %#010x %#010x",
+			src + (i << 2), buff[i], buff[i+1],
+			buff[i+2], buff[i+3]);
+
+		src += byte_read_count;
+		size -= byte_read_count;
+	} while (total_block_read--);
+}
+
+void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size)
+{
+	nvgpu_info(flcn->g, " PRINT DMEM ");
+	nvgpu_flcn_print_mem(flcn, src, size, MEM_DMEM);
+}
+
+void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size)
+{
+	nvgpu_info(flcn->g, " PRINT IMEM ");
+	nvgpu_flcn_print_mem(flcn, src, size, MEM_IMEM);
+}
+
 int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
 {
 	struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;

drivers/gpu/nvgpu/gk20a/flcn_gk20a.c

@@ -269,6 +269,54 @@ static int gk20a_flcn_copy_to_dmem(struct nvgpu_falcon *flcn,
 	return 0;
 }
 
+static int gk20a_flcn_copy_from_imem(struct nvgpu_falcon *flcn, u32 src,
+	u8 *dst, u32 size, u8 port)
+{
+	struct gk20a *g = flcn->g;
+	u32 base_addr = flcn->flcn_base;
+	u32 *dst_u32 = (u32 *)dst;
+	u32 words = 0;
+	u32 bytes = 0;
+	u32 data = 0;
+	u32 blk = 0;
+	u32 i = 0;
+
+	nvgpu_log_info(g, "download %d bytes from 0x%x", size, src);
+
+	if (flcn_mem_overflow_check(flcn, src, size, MEM_IMEM)) {
+		nvgpu_err(g, "incorrect parameters");
+		return -EINVAL;
+	}
+
+	nvgpu_mutex_acquire(&flcn->copy_lock);
+
+	words = size >> 2;
+	bytes = size & 0x3;
+	blk = src >> 8;
+
+	nvgpu_log_info(g, "download %d words from 0x%x block %d",
+			words, src, blk);
+
+	gk20a_writel(g, base_addr + falcon_falcon_imemc_r(port),
+		falcon_falcon_imemc_offs_f(src >> 2) |
+		falcon_falcon_imemc_blk_f(blk) |
+		falcon_falcon_dmemc_aincr_f(1));
+
+	for (i = 0; i < words; i++)
+		dst_u32[i] = gk20a_readl(g,
+			base_addr + falcon_falcon_imemd_r(port));
+
+	if (bytes > 0) {
+		data = gk20a_readl(g, base_addr + falcon_falcon_imemd_r(port));
+		for (i = 0; i < bytes; i++)
+			dst[(words << 2) + i] = ((u8 *)&data)[i];
+	}
+
+	nvgpu_mutex_release(&flcn->copy_lock);
+
+	return 0;
+}
+
 static int gk20a_flcn_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
 		u8 *src, u32 size, u8 port, bool sec, u32 tag)
 {
@@ -551,6 +599,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
 	flcn_ops->copy_from_dmem = gk20a_flcn_copy_from_dmem;
 	flcn_ops->copy_to_dmem = gk20a_flcn_copy_to_dmem;
 	flcn_ops->copy_to_imem = gk20a_flcn_copy_to_imem;
+	flcn_ops->copy_from_imem = gk20a_flcn_copy_from_imem;
 	flcn_ops->bootstrap = gk20a_falcon_bootstrap;
 	flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats;
 

drivers/gpu/nvgpu/include/nvgpu/falcon.h

@@ -189,6 +189,8 @@ u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index);
 void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index,
 	u32 data);
 int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
+void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size);
+void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size);
 void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn);
 
 void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);