video: tegra: host: flexible to select fw per chip

Decouple the firmware selection of different gpu architecture.

Change-Id: I62bf6b3bc51a8606c5973e475988cd5987a65a1a
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/389793
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -191,6 +191,10 @@ struct gpu_ops {
 		void *(*get_pmu_seq_out_a_ptr)(
 				struct pmu_sequence *seq);
 	} pmu_ver;
+	struct {
+		int (*get_netlist_name)(int index, char *name);
+		bool (*is_fw_defined)(void);
+	} gr_ctx;
 };
 
 struct gk20a {

drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c

@@ -96,6 +96,15 @@ static int gr_gk20a_get_netlist_name(int index, char *name)
 	return -1;
 }
 
+bool gr_gk20a_is_firmware_defined(void)
+{
+#ifdef GK20A_NETLIST_IMAGE_FW_NAME
+	return true;
+#else
+	return false;
+#endif
+}
+
 static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr)
 {
 	struct device *d = dev_from_gk20a(g);
@@ -107,21 +116,21 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr)
 
 	gk20a_dbg_fn("");
 
-#ifdef GK20A_NETLIST_IMAGE_FW_NAME
+	if (g->ops.gr_ctx.is_fw_defined()) {
 		net = NETLIST_FINAL;
 		max = 0;
 		major_v_hw = ~0;
 		g->gr.ctx_vars.dynamic = false;
-#else
+	} else {
 		net = NETLIST_SLOT_A;
 		max = MAX_NETLIST;
-	major_v_hw = gk20a_readl(g, gr_fecs_ctx_state_store_major_rev_id_r());
+		major_v_hw = gk20a_readl(g,
+				gr_fecs_ctx_state_store_major_rev_id_r());
 		g->gr.ctx_vars.dynamic = true;
-#endif
+	}
 
 	for (; net < max; net++) {
-
+		if (g->ops.gr_ctx.get_netlist_name(net, name) != 0) {
-		if (gr_gk20a_get_netlist_name(net, name) != 0) {
 			gk20a_warn(d, "invalid netlist index %d", net);
 			continue;
 		}
@@ -331,3 +340,9 @@ int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr)
 	else
 		return gr_gk20a_init_ctx_vars_fw(g, gr);
 }
+
+void gk20a_init_gr_ctx(struct gpu_ops *gops)
+{
+	gops->gr_ctx.get_netlist_name = gr_gk20a_get_netlist_name;
+	gops->gr_ctx.is_fw_defined = gr_gk20a_is_firmware_defined;
+}

drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h

@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics Context
  *
- * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,10 +18,10 @@
 #ifndef __GR_CTX_GK20A_H__
 #define __GR_CTX_GK20A_H__
 
-
 /* production netlist, one and only one from below */
 /*#undef GK20A_NETLIST_IMAGE_FW_NAME*/
 #define GK20A_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B
+
 /* emulation netlists, match majorV with HW */
 #define GK20A_NETLIST_IMAGE_A	"NETA_img.bin"
 #define GK20A_NETLIST_IMAGE_B	"NETB_img.bin"
@@ -146,4 +146,7 @@ struct gr_ucode_gk20a {
 int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr);
 int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr);
 
+struct gpu_ops;
+void gk20a_init_gr_ctx(struct gpu_ops *gops);
+
 #endif /*__GR_CTX_GK20A_H__*/

drivers/gpu/nvgpu/gk20a/hal_gk20a.c

@@ -21,6 +21,7 @@
 #include "gk20a.h"
 #include "gk20a_gating_reglist.h"
 #include "channel_gk20a.h"
+#include "gr_ctx_gk20a.h"
 
 struct gpu_ops gk20a_ops = {
 	.clock_gating = {
@@ -44,6 +45,7 @@ int gk20a_init_hal(struct gpu_ops *gops)
 	gk20a_init_gr(gops);
 	gk20a_init_fb(gops);
 	gk20a_init_fifo(gops);
+	gk20a_init_gr_ctx(gops);
 	gops->name = "gk20a";
 
 	return 0;