diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 600676983..bea6b93c5 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -309,10 +309,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .add_depth = NULL, .set_table = vgpu_gr_add_zbc, .query_table = vgpu_gr_query_zbc, - .stencil_query_table = NULL, - .load_stencil_default_tbl = NULL, - .add_type_stencil = NULL, - .load_stencil_tbl = NULL, .add_stencil = NULL, .get_gpcs_swdx_dss_zbc_c_format_reg = NULL, .get_gpcs_swdx_dss_zbc_z_format_reg = NULL, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c index 1bfcd0d43..4c221cb3a 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c @@ -39,4 +39,5 @@ void vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true); + nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); } diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index e8c693ca6..0d65da9d6 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -350,12 +350,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .add_depth = NULL, .set_table = vgpu_gr_add_zbc, .query_table = vgpu_gr_query_zbc, - .stencil_query_table = - nvgpu_gr_zbc_stencil_query_table, - .load_stencil_default_tbl = - nvgpu_gr_zbc_load_stencil_default_tbl, - .add_type_stencil = nvgpu_gr_zbc_add_type_stencil, - .load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl, .add_stencil = gv11b_gr_zbc_add_stencil, .get_gpcs_swdx_dss_zbc_c_format_reg = NULL, .get_gpcs_swdx_dss_zbc_z_format_reg = NULL, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 319f7a110..18f6b38f5 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2667,8 +2667,8 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, } break; case T19X_ZBC: - if (g->ops.gr.zbc.add_type_stencil != NULL) { - added = g->ops.gr.zbc.add_type_stencil(g, gr, + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL)) { + added = nvgpu_gr_zbc_add_type_stencil(g, gr, zbc_val, &ret); } else { nvgpu_err(g, @@ -2739,8 +2739,8 @@ int nvgpu_gr_zbc_query_table(struct gk20a *g, struct gr_gk20a *gr, query_params->ref_cnt = gr->zbc_dep_tbl[index].ref_cnt; break; case T19X_ZBC: - if (g->ops.gr.zbc.stencil_query_table != NULL) { - return g->ops.gr.zbc.stencil_query_table(g, gr, + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL)) { + return nvgpu_gr_zbc_stencil_query_table(g, gr, query_params); } else { nvgpu_err(g, @@ -2792,8 +2792,8 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr) } } - if (g->ops.gr.zbc.load_stencil_tbl != NULL) { - ret = g->ops.gr.zbc.load_stencil_tbl(g, gr); + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL)) { + ret = nvgpu_gr_zbc_load_stencil_tbl(g, gr); if (ret != 0) { return ret; } @@ -2873,8 +2873,8 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) gr->max_default_depth_index = 2; - if (g->ops.gr.zbc.load_stencil_default_tbl != NULL) { - err = g->ops.gr.zbc.load_stencil_default_tbl(g, gr); + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL)) { + err = nvgpu_gr_zbc_load_stencil_default_tbl(g, gr); if (err != 0) { return err; } diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 580aff26b..34caeba8a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -457,6 +457,14 @@ int nvgpu_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index); int nvgpu_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *color_val, u32 index); +int nvgpu_gr_zbc_stencil_query_table(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_query_params *query_params); +bool nvgpu_gr_zbc_add_type_stencil(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *zbc_val, int *ret_val); +int nvgpu_gr_zbc_load_stencil_default_tbl(struct gk20a *g, + struct gr_gk20a *gr); +int nvgpu_gr_zbc_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr); + /* pmu */ int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size); int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 7b04a28ad..1139d848a 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -415,10 +415,6 @@ static const struct gpu_ops gm20b_ops = { .add_depth = gk20a_gr_zbc_add_depth, .set_table = nvgpu_gr_zbc_set_table, .query_table = nvgpu_gr_zbc_query_table, - .stencil_query_table = NULL, - .load_stencil_default_tbl = NULL, - .add_type_stencil = NULL, - .load_stencil_tbl = NULL, .add_stencil = NULL, .get_gpcs_swdx_dss_zbc_c_format_reg = NULL, .get_gpcs_swdx_dss_zbc_z_format_reg = NULL, @@ -913,6 +909,7 @@ int gm20b_init_hal(struct gk20a *g) gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; } + nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false); nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); g->pmu_lsf_pmu_wpr_init_done = 0; diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 29a6eb8ba..0a51cb444 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -458,10 +458,6 @@ static const struct gpu_ops gp10b_ops = { .add_depth = gp10b_gr_zbc_add_depth, .set_table = nvgpu_gr_zbc_set_table, .query_table = nvgpu_gr_zbc_query_table, - .stencil_query_table = NULL, - .load_stencil_default_tbl = NULL, - .add_type_stencil = NULL, - .load_stencil_tbl = NULL, .add_stencil = NULL, .get_gpcs_swdx_dss_zbc_c_format_reg = gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg, @@ -985,6 +981,7 @@ int gp10b_init_hal(struct gk20a *g) gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; } + nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false); nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); g->pmu_lsf_pmu_wpr_init_done = false; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 6efc6e35e..28d9e8b7e 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -584,12 +584,6 @@ static const struct gpu_ops gv100_ops = { .add_depth = gp10b_gr_zbc_add_depth, .set_table = nvgpu_gr_zbc_set_table, .query_table = nvgpu_gr_zbc_query_table, - .stencil_query_table = - nvgpu_gr_zbc_stencil_query_table, - .load_stencil_default_tbl = - nvgpu_gr_zbc_load_stencil_default_tbl, - .add_type_stencil = nvgpu_gr_zbc_add_type_stencil, - .load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl, .add_stencil = gv11b_gr_zbc_add_stencil, .get_gpcs_swdx_dss_zbc_c_format_reg = gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg, @@ -1230,6 +1224,7 @@ int gv100_init_hal(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_RTOS_FBQ, true); + nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); /* for now */ nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 8eb73c8bb..72e1e06c9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -107,15 +107,8 @@ u32 gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g); u32 gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g); int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event); -int nvgpu_gr_zbc_stencil_query_table(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_query_params *query_params); -bool nvgpu_gr_zbc_add_type_stencil(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *zbc_val, int *ret_val); int gv11b_gr_zbc_add_stencil(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *stencil_val, u32 index); -int nvgpu_gr_zbc_load_stencil_default_tbl(struct gk20a *g, - struct gr_gk20a *gr); -int nvgpu_gr_zbc_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr); u32 gr_gv11b_pagepool_default_size(struct gk20a *g); u32 gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g); int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 539e4613e..fb484a1e5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -543,12 +543,6 @@ static const struct gpu_ops gv11b_ops = { .add_depth = gp10b_gr_zbc_add_depth, .set_table = nvgpu_gr_zbc_set_table, .query_table = nvgpu_gr_zbc_query_table, - .stencil_query_table = - nvgpu_gr_zbc_stencil_query_table, - .load_stencil_default_tbl = - nvgpu_gr_zbc_load_stencil_default_tbl, - .add_type_stencil = nvgpu_gr_zbc_add_type_stencil, - .load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl, .add_stencil = gv11b_gr_zbc_add_stencil, .get_gpcs_swdx_dss_zbc_c_format_reg = gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg, @@ -1114,6 +1108,7 @@ int gv11b_init_hal(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); + nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); g->name = "gv11b"; diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 6a78fa722..6dc21d675 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -177,10 +177,13 @@ struct gk20a; /* PMU RTOS FBQ support*/ #define NVGPU_SUPPORT_PMU_RTOS_FBQ 70 +/* ZBC STENCIL support*/ +#define NVGPU_SUPPORT_ZBC_STENCIL 71 + /* * Must be greater than the largest bit offset in the above list. */ -#define NVGPU_MAX_ENABLED_BITS 71U +#define NVGPU_MAX_ENABLED_BITS 72U /** * nvgpu_is_enabled - Check if the passed flag is enabled. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index fade907a0..f563c4ed4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -620,18 +620,8 @@ struct gpu_ops { int (*query_table)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_query_params *query_params); - int (*stencil_query_table)(struct gk20a *g, - struct gr_gk20a *gr, - struct zbc_query_params *query_params); - int (*load_stencil_default_tbl)(struct gk20a *g, - struct gr_gk20a *gr); - int (*load_stencil_tbl)(struct gk20a *g, - struct gr_gk20a *gr); int (*add_stencil)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *s_val, u32 index); - bool (*add_type_stencil)(struct gk20a *g, - struct gr_gk20a *gr, - struct zbc_entry *zbc_val, int *ret_val); u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)( struct gk20a *g); u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)( diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 7be565733..ebfd29ab5 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -608,12 +608,6 @@ static const struct gpu_ops tu104_ops = { .add_depth = gp10b_gr_zbc_add_depth, .set_table = nvgpu_gr_zbc_set_table, .query_table = nvgpu_gr_zbc_query_table, - .stencil_query_table = - nvgpu_gr_zbc_stencil_query_table, - .load_stencil_default_tbl = - nvgpu_gr_zbc_load_stencil_default_tbl, - .add_type_stencil = nvgpu_gr_zbc_add_type_stencil, - .load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl, .add_stencil = gv11b_gr_zbc_add_stencil, .get_gpcs_swdx_dss_zbc_c_format_reg = gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg, @@ -1270,6 +1264,7 @@ int tu104_init_hal(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_RTOS_FBQ, true); + nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); /* for now */ gops->clk.support_clk_freq_controller = false;