gpu: nvgpu: MISRA 10.1 boolean fixes

MISRA rule 10.1 doesn't allow the usage of non-boolean variables as
booleans. Fix violations where a variable of type non-boolean is used
as a boolean.

JIRA NVGPU-646

Change-Id: If451037ada9a5f41b0cddb50778de57f60864f5c
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1815742
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/clk/clk_prog.c

@@ -1125,7 +1125,7 @@ static int clk_prog_construct_1x_master_ratio(struct gk20a *g,
 	pclkprog->p_slave_entries =
 		(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *)
 		nvgpu_kzalloc(g, slavesize);
-	if (!pclkprog->p_slave_entries) {
+	if (pclkprog->p_slave_entries == NULL) {
 		return -ENOMEM;
 	}
 
@@ -1214,7 +1214,7 @@ static int clk_prog_construct_1x_master_table(struct gk20a *g,
 		(struct ctrl_clk_clk_prog_1x_master_table_slave_entry *)
 		nvgpu_kzalloc(g, slavesize);
 
-	if (!pclkprog->p_slave_entries) {
+	if (pclkprog->p_slave_entries == NULL) {
 		status = -ENOMEM;
 		goto exit;
 	}

drivers/gpu/nvgpu/clk/clk_vin.c

@@ -297,7 +297,7 @@ static int devinit_get_vin_device_table(struct gk20a *g,
 				NV_VIN_DESC_FLAGS0_DISABLE_CONTROL);
 	cal_type = BIOS_GET_FIELD(vin_desc_table_header.flags0,
 				NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE);
-	if (!cal_type) {
+	if (cal_type == 0U) {
 		cal_type = CTRL_CLK_VIN_CAL_TYPE_V10;
 	}
 

drivers/gpu/nvgpu/common/mc/mc_tu104.c

@@ -270,7 +270,7 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g)
 	u32 i;
 	u32 nonstall_intr_base = 0;
 	u64 nonstall_intr_mask = 0;
-	u64 nonstall_intr_mask_lo, nonstall_intr_mask_hi;
+	u32 nonstall_intr_mask_lo, nonstall_intr_mask_hi;
 	u32 intr_leaf_reg0, intr_leaf_reg1;
 	u32 active_engine_id, intr_mask;
 	u32 ops = 0;
@@ -296,8 +296,8 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g)
 		nonstall_intr_mask_lo = u64_lo32(nonstall_intr_mask);
 		nonstall_intr_mask_hi = u64_hi32(nonstall_intr_mask);
 
-		if ((nonstall_intr_mask_lo & intr_leaf_reg0) ||
-		    (nonstall_intr_mask_hi & intr_leaf_reg1)) {
+		if ((nonstall_intr_mask_lo & intr_leaf_reg0) != 0U ||
+		    (nonstall_intr_mask_hi & intr_leaf_reg1) != 0U) {
 			nvgpu_log(g, gpu_dbg_intr, "nonstall intr from engine %d",
 				active_engine_id);
 

drivers/gpu/nvgpu/common/netlist/netlist.c

@@ -59,7 +59,7 @@ static int nvgpu_netlist_alloc_load_u32_list(struct gk20a *g, u8 *src, u32 len,
 			struct netlist_u32_list *u32_list)
 {
 	u32_list->count = (len + sizeof(u32) - 1) / sizeof(u32);
-	if (!nvgpu_netlist_alloc_u32_list(g, u32_list)) {
+	if (nvgpu_netlist_alloc_u32_list(g, u32_list) == NULL) {
 		return -ENOMEM;
 	}
 
@@ -72,7 +72,7 @@ static int nvgpu_netlist_alloc_load_av_list(struct gk20a *g, u8 *src, u32 len,
 			struct netlist_av_list *av_list)
 {
 	av_list->count = len / sizeof(struct netlist_av);
-	if (!nvgpu_netlist_alloc_av_list(g, av_list)) {
+	if (nvgpu_netlist_alloc_av_list(g, av_list) == NULL) {
 		return -ENOMEM;
 	}
 
@@ -85,7 +85,7 @@ static int nvgpu_netlist_alloc_load_av_list64(struct gk20a *g, u8 *src, u32 len,
 			struct netlist_av64_list *av64_list)
 {
 	av64_list->count = len / sizeof(struct netlist_av64);
-	if (!nvgpu_netlist_alloc_av64_list(g, av64_list)) {
+	if (nvgpu_netlist_alloc_av64_list(g, av64_list) == NULL) {
 		return -ENOMEM;
 	}
 
@@ -98,7 +98,7 @@ static int nvgpu_netlist_alloc_load_aiv_list(struct gk20a *g, u8 *src, u32 len,
 			struct netlist_aiv_list *aiv_list)
 {
 	aiv_list->count = len / sizeof(struct netlist_aiv);
-	if (!nvgpu_netlist_alloc_aiv_list(g, aiv_list)) {
+	if (nvgpu_netlist_alloc_aiv_list(g, aiv_list) == NULL) {
 		return -ENOMEM;
 	}
 
@@ -137,7 +137,7 @@ static int nvgpu_netlist_init_ctx_vars_fw(struct gk20a *g)
 		}
 
 		netlist_fw = nvgpu_request_firmware(g, name, 0);
-		if (!netlist_fw) {
+		if (netlist_fw == NULL) {
 			nvgpu_warn(g, "failed to load netlist %s", name);
 			continue;
 		}

drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c

@@ -152,7 +152,7 @@ void gp10b_priv_ring_isr(struct gk20a *g)
 		}
 	}
 
-	if (status1) {
+	if (status1 != 0U) {
 		gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
 		for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
 			offset = gpc * gpc_stride;

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -3651,7 +3651,7 @@ int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 chid,
 		/* Capture the last failure error code */
 		errcode = g->ops.fifo.update_runlist(g, (u32)runlist_id, chid,
 						add, wait_for_finish);
-		if (errcode) {
+		if (errcode != 0) {
 			nvgpu_err(g,
 				"failed to update_runlist %lu %d",
 				runlist_id, errcode);

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -7921,7 +7921,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g,
 	map_key.addr = addr;
 	result = bsearch(&map_key, map, count, sizeof(*map), map_cmp);
 
-	if (result) {
+	if (result != NULL) {
 		*priv_offset = result->offset;
 	} else {
 		nvgpu_err(g, "Lookup failed for address 0x%x", addr);

drivers/gpu/nvgpu/gv100/bios_gv100.c

@@ -69,7 +69,7 @@ int gv100_bios_preos_wait_for_halt(struct gk20a *g)
 	int err = -EINVAL;
 	u32 progress;
 	u32 tmp;
-	int preos_completed;
+	bool preos_completed;
 	struct nvgpu_timeout timeout;
 
 	nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
@@ -93,12 +93,13 @@ int gv100_bios_preos_wait_for_halt(struct gk20a *g)
 
 		do {
 			progress = g->ops.bus.read_sw_scratch(g, SCRATCH_PREOS_PROGRESS);
-			preos_completed = pwr_falcon_cpuctl_halt_intr_v(
-				gk20a_readl(g, pwr_falcon_cpuctl_r())) &&
+			preos_completed = (pwr_falcon_cpuctl_halt_intr_v(
+				gk20a_readl(g, pwr_falcon_cpuctl_r())) != 0U) &&
 					(PREOS_PROGRESS_MASK(progress) ==
 					PREOS_PROGRESS_EXIT);
 			nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
-		} while (!preos_completed && !nvgpu_timeout_expired(&timeout));
+		} while (!preos_completed &&
+			 (nvgpu_timeout_expired(&timeout) == 0));
 	}
 
 	return err;

drivers/gpu/nvgpu/gv100/gr_gv100.c

@@ -76,7 +76,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g,
 	u32 *num_tpc_gpc = nvgpu_kzalloc(g, sizeof(u32) *
 				nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS));
 
-	if (!num_tpc_gpc) {
+	if (num_tpc_gpc == NULL) {
 		return -ENOMEM;
 	}
 
@@ -84,8 +84,8 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g,
 	for (gpc_id = 0; gpc_id < gr->gpc_count; gpc_id++) {
 		num_tpc_mask = gpc_tpc_mask[gpc_id];
 
-		if ((gpc_id == disable_gpc_id) && num_tpc_mask &
-						(0x1 << disable_tpc_id)) {
+		if ((gpc_id == disable_gpc_id) &&
+		    ((num_tpc_mask & BIT32(disable_tpc_id)) != 0U)) {
 			/* Safety check if a TPC is removed twice */
 			if (is_tpc_removed_gpc) {
 				err = -EINVAL;
@@ -122,8 +122,8 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g,
 			num_tpc_mask = gr->pes_tpc_mask[pes_id][gpc_id] &
 					gpc_tpc_mask[gpc_id];
 
-			if ((gpc_id == disable_gpc_id) && (num_tpc_mask &
-				(0x1 << disable_tpc_id))) {
+			if ((gpc_id == disable_gpc_id) &&
+			    ((num_tpc_mask & BIT32(disable_tpc_id)) != 0U)) {
 
 				if (is_tpc_removed_pes) {
 					err = -EINVAL;
@@ -198,7 +198,7 @@ void gr_gv100_cb_size_default(struct gk20a *g)
 {
 	struct gr_gk20a *gr = &g->gr;
 
-	if (!gr->attrib_cb_default_size) {
+	if (gr->attrib_cb_default_size == 0U) {
 		gr->attrib_cb_default_size =
 			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
 	}
@@ -227,7 +227,9 @@ int gr_gv100_init_sm_id_table(struct gk20a *g)
 	gpc_tpc_mask = nvgpu_kzalloc(g, sizeof(unsigned long) *
 			nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS));
 
-	if (!gpc_table || !tpc_table || !gpc_tpc_mask) {
+	if ((gpc_table == NULL) ||
+	    (tpc_table == NULL) ||
+	    (gpc_tpc_mask == NULL)) {
 		nvgpu_err(g, "Error allocating memory for sm tables");
 		err = -ENOMEM;
 		goto exit_build_table;

drivers/gpu/nvgpu/include/nvgpu/bios.h

@@ -396,8 +396,8 @@ struct vbios_vfe_3x_var_entry_struct {
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25
 
-#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001
-#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001U
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO  0x00000000U
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0
 
@@ -455,8 +455,8 @@ struct vbios_vfe_3x_equ_entry_struct {
 
 #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000
 #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16
-#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000
-#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000U
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001U
 
 #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF
 #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0

drivers/gpu/nvgpu/lpwr/lpwr.c

@@ -244,7 +244,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
 
 	pstate_info = pstate_get_clk_set_info(g, pstate,
 			clkwhich_mclk);
-	if (!pstate_info) {
+	if (pstate_info == NULL) {
 		return -EINVAL;
 	}
 
@@ -325,7 +325,7 @@ bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num)
 
 	nvgpu_log_fn(g, " ");
 
-	if (!pstate) {
+	if (pstate == NULL) {
 		return false;
 	}
 
@@ -348,7 +348,7 @@ bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
 
 	nvgpu_log_fn(g, " ");
 
-	if (!pstate) {
+	if (pstate == NULL) {
 		return false;
 	}
 
@@ -381,7 +381,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
 	is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g,
 			present_pstate);
 	if (is_mscg_supported && g->mscg_enabled) {
-		if (!pmu->mscg_stat) {
+		if (pmu->mscg_stat == 0U) {
 			pmu->mscg_stat = PMU_MSCG_ENABLED;
 		}
 	}

drivers/gpu/nvgpu/pmgr/pmgrpmu.c

@@ -185,7 +185,7 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g)
 
 	/* Set the BA-device-independent HW information */
 	pwr_desc_table = nvgpu_kzalloc(g, sizeof(*pwr_desc_table));
-	if (!pwr_desc_table) {
+	if (pwr_desc_table == NULL) {
 		return -ENOMEM;
 	}
 
@@ -234,7 +234,7 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
 	int status = 0;
 
 	pwr_monitor_pack = nvgpu_kzalloc(g, sizeof(*pwr_monitor_pack));
-	if (!pwr_monitor_pack) {
+	if (pwr_monitor_pack == NULL) {
 		return -ENOMEM;
 	}
 
@@ -305,7 +305,7 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
 	u32 max_dmem_size;
 
 	ppwrpack = nvgpu_kzalloc(g, sizeof(struct nv_pmu_pmgr_pwr_policy_pack));
-	if (!ppwrpack) {
+	if (ppwrpack == NULL) {
 		nvgpu_err(g, "pwr policy alloc failed %x",
 			status);
 		status = -ENOMEM;

drivers/gpu/nvgpu/pmgr/pwrdev.c

@@ -249,8 +249,8 @@ static int devinit_get_pwr_device_table(struct gk20a *g,
 				pwr_sensor_table_entry.sensor_param3,
 				NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B);
 
-			if (!pwr_device_data.ina3221.curr_correct_m) {
-				pwr_device_data.ina3221.curr_correct_m = (1 << 12);
+			if (pwr_device_data.ina3221.curr_correct_m == 0U) {
+				pwr_device_data.ina3221.curr_correct_m = BIT16(12);
 			}
 			pwr_device_size = sizeof(struct pwr_device_ina3221);
 		} else {
@@ -263,7 +263,7 @@ static int devinit_get_pwr_device_table(struct gk20a *g,
 		boardobj = construct_pwr_device(g, &pwr_device_data,
 					pwr_device_size, pwr_device_data.boardobj.type);
 
-		if (!boardobj) {
+		if (boardobj == NULL) {
 			nvgpu_err(g,
 			"unable to create pwr device for %d type %d", index, pwr_device_data.boardobj.type);
 			status = -EINVAL;

drivers/gpu/nvgpu/pmgr/pwrmonitor.c

@@ -275,7 +275,7 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
 		boardobj = construct_pwr_topology(g, &pwr_topology_data,
 					pwr_topology_size, pwr_topology_data.boardobj.type);
 
-		if (!boardobj) {
+		if (boardobj == NULL) {
 			nvgpu_err(g,
 				"unable to create pwr topology for %d type %d",
 				index, pwr_topology_data.boardobj.type);

drivers/gpu/nvgpu/pmgr/pwrpolicy.c

@@ -396,7 +396,7 @@ static int _pwr_policy_construct_WAR_SW_Threshold_policy(struct gk20a *g,
 	boardobj = construct_pwr_policy(g, ppwrpolicydata,
 				pwr_policy_size, ppwrpolicydata->boardobj.type);
 
-	if (!boardobj) {
+	if (boardobj == NULL) {
 		nvgpu_err(g,
 			"unable to create pwr policy for type %d", ppwrpolicydata->boardobj.type);
 		status = -EINVAL;
@@ -672,7 +672,7 @@ static int devinit_get_pwr_policy_table(struct gk20a *g,
 		boardobj = construct_pwr_policy(g, &pwr_policy_data,
 				pwr_policy_size, pwr_policy_data.boardobj.type);
 
-		if (!boardobj) {
+		if (boardobj == NULL) {
 			nvgpu_err(g,
 				"unable to create pwr policy for %d type %d",
 				index, pwr_policy_data.boardobj.type);

drivers/gpu/nvgpu/pmu_perf/pmu_perf.c

@@ -61,7 +61,7 @@ static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg)
 		nvgpu_clk_arb_schedule_vf_table_update(g);
 		break;
 	default:
-		WARN_ON(1);
+		WARN_ON(true);
 		break;
 	}
 	return 0;

drivers/gpu/nvgpu/pmu_perf/vfe_equ.c

@@ -258,7 +258,7 @@ static int devinit_get_vfe_equ_table(struct gk20a *g,
 			equ_type = CTRL_PERF_VFE_EQU_TYPE_MINMAX;
 			equ_data.minmax.b_max = BIOS_GET_FIELD(equ.param0,
 				VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT) &&
-				VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX;
+				(VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX != 0U);
 			equ_data.minmax.equ_idx0 = (u8)BIOS_GET_FIELD(
 				equ.param0,
 				VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0);

drivers/gpu/nvgpu/pmu_perf/vfe_var.c

@@ -988,9 +988,9 @@ static int devinit_get_vfe_var_table(struct gk20a *g,
 				(u8)BIOS_GET_FIELD(var.param0,
 					VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER);
 			var_data.single_sensed_fuse.vfield_ver_info.b_use_default_on_ver_check_fail =
-				(BIOS_GET_FIELD(var.param0,
+				BIOS_GET_FIELD(var.param0,
 					VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL) &&
-					VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES);
+					(VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES != 0U);
 			var_data.single_sensed_fuse.b_fuse_value_signed =
 				(u8)BIOS_GET_FIELD(var.param0,
 					VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER);

drivers/gpu/nvgpu/pstate/pstate.c

@@ -278,7 +278,7 @@ static struct pstate *pstate_construct(struct gk20a *g, void *args)
 
 	if ((tmp->super.type != CTRL_PERF_PSTATE_TYPE_3X) ||
 	    (pstate_construct_3x(g, (struct boardobj **)&pstate,
-			    sizeof(struct pstate), args))) {
+			    sizeof(struct pstate), args) != 0)) {
 		nvgpu_err(g,
 			"error constructing pstate num=%u", tmp->num);
 	}
@@ -393,7 +393,7 @@ static int parse_pstate_table_5x(struct gk20a *g,
 		}
 
 		pstate = pstate_construct(g, &_pstate);
-		if (!pstate) {
+		if (pstate == NULL) {
 			goto done;
 		}
 
@@ -433,7 +433,7 @@ static int pstate_sw_setup(struct gk20a *g)
 			nvgpu_bios_get_perf_table_ptrs(g,
 			g->bios.perf_token, PERFORMANCE_TABLE);
 
-	if (!hdr) {
+	if (hdr == NULL) {
 		nvgpu_err(g, "performance table not found");
 		err = -EINVAL;
 		goto done;
@@ -482,7 +482,7 @@ struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g,
 
 	nvgpu_log_info(g, "pstate = %p", pstate);
 
-	if (!pstate) {
+	if (pstate == NULL) {
 		return NULL;
 	}
 

drivers/gpu/nvgpu/therm/thrmchannel.c

@@ -187,7 +187,7 @@ static int devinit_get_therm_channel_table(struct gk20a *g,
 		boardobj = construct_channel_device(g, &therm_channel_data,
 					therm_channel_size, therm_channel_data.boardobj.type);
 
-		if (!boardobj) {
+		if (boardobj == NULL) {
 			nvgpu_err(g,
 				"unable to create thermal device for %d type %d",
 				index, therm_channel_data.boardobj.type);

drivers/gpu/nvgpu/therm/thrmdev.c

@@ -301,7 +301,7 @@ static int devinit_get_therm_device_table(struct gk20a *g,
 
 		therm_device_data.boardobj.type = class_id;
 		boardobj = therm_device_construct(g, &therm_device_data);
-		if (!boardobj) {
+		if (boardobj == NULL) {
 			nvgpu_err(g,
 				"unable to create thermal device for %d type %d",
 				index, therm_device_data.boardobj.type);