gpu: nvgpu: compile out PMU members & headers for safety

-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile.sources

@@ -229,7 +229,6 @@ srcs += common/utils/enabled.c \
 	hal/fb/intr/fb_intr_ecc_gv11b.c \
 	hal/fuse/fuse_gm20b.c \
 	hal/fuse/fuse_gp10b.c \
-	hal/fuse/fuse_gp106.c \
 	hal/rc/rc_gk20a.c \
 	hal/rc/rc_gv11b.c \
 	hal/fifo/fifo_gk20a.c \
@@ -522,6 +521,7 @@ srcs += common/sec2/sec2.c \
 	hal/fifo/runlist_fifo_gv100.c \
 	hal/fifo/runlist_fifo_tu104.c \
 	hal/fifo/fifo_intr_gv100.c \
+	hal/fuse/fuse_gp106.c \
 	hal/netlist/netlist_gv100.c \
 	hal/netlist/netlist_tu104.c \
 	hal/nvdec/nvdec_tu104.c \

drivers/gpu/nvgpu/common/acr/acr.c

@@ -25,7 +25,6 @@
 #include <nvgpu/firmware.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/acr.h>
-#include <nvgpu/pmu/pmuif/cmn.h>
 
 #include "acr_priv.h"
 #ifdef NVGPU_FEATURE_ACR_LEGACY

drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c

@@ -24,7 +24,9 @@
 #include <nvgpu/firmware.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/bug.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/fw.h>
+#endif
 
 #include "acr_wpr.h"
 #include "acr_priv.h"

drivers/gpu/nvgpu/common/clk_arb/clk_arb.c

@@ -34,9 +34,11 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/worker.h>
 #include <nvgpu/gk20a.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/perf_pstate.h>
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/clk/clk.h>
+#endif
 #include <nvgpu/boardobjgrp_e255.h>
 
 int nvgpu_clk_notification_queue_alloc(struct gk20a *g,

drivers/gpu/nvgpu/common/fifo/engines.c

@@ -25,8 +25,10 @@
 #include <nvgpu/errno.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/bitops.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu.h>
 #include <nvgpu/pmu/mutex.h>
+#endif
 #include <nvgpu/runlist.h>
 #include <nvgpu/engines.h>
 #include <nvgpu/engine_status.h>

drivers/gpu/nvgpu/common/fifo/runlist.c

@@ -29,7 +29,9 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/dma.h>
 #include <nvgpu/rc.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/mutex.h>
+#endif
 
 void nvgpu_runlist_lock_active_runlists(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -30,8 +30,10 @@
 #include <nvgpu/sizes.h>
 #include <nvgpu/mm.h>
 #include <nvgpu/acr.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/lsfm.h>
 #include <nvgpu/pmu/pmu_pg.h>
+#endif
 #ifdef NVGPU_DGPU_SUPPORT
 #include <nvgpu/sec2/lsfm.h>
 #endif

drivers/gpu/nvgpu/common/gr/obj_ctx.c

@@ -24,7 +24,9 @@
 #include <nvgpu/log.h>
 #include <nvgpu/io.h>
 #include <nvgpu/mm.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/pmu_pg.h>
+#endif
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/global_ctx.h>

drivers/gpu/nvgpu/common/gr/zbc.c

@@ -25,7 +25,9 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/string.h>
 #include <nvgpu/power_features/pg.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/pmu_pg.h>
+#endif
 
 #include "zbc_priv.h"
 

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -48,7 +48,9 @@
 #include <nvgpu/gr/gr.h>
 
 #include <trace/events/gk20a.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/pmu_pstate.h>
+#endif
 
 bool is_nvgpu_gpu_state_valid(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/pmu/pmu.c

@@ -20,30 +20,32 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <nvgpu/pmu.h>
-#include <nvgpu/pmu/pmu_pg.h>
-#include <nvgpu/pmu/mutex.h>
-#include <nvgpu/pmu/seq.h>
+#include <nvgpu/gk20a.h>
 #include <nvgpu/log.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/utils.h>
-#include <nvgpu/gk20a.h>
 #include <nvgpu/power_features/cg.h>
 #include <nvgpu/nvgpu_err.h>
+#include <nvgpu/boardobj.h>
+#include <nvgpu/boardobjgrp.h>
+#include <nvgpu/pmu.h>
+#ifdef NVGPU_FEATURE_LS_PMU
+#include <nvgpu/pmu/pmu_pg.h>
+#include <nvgpu/pmu/mutex.h>
+#include <nvgpu/pmu/seq.h>
 #include <nvgpu/pmu/lsfm.h>
-#ifdef NVGPU_DGPU_SUPPORT
-#include <nvgpu/sec2/lsfm.h>
-#endif
 #include <nvgpu/pmu/super_surface.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 #include <nvgpu/pmu/pmu_pg.h>
 #include <nvgpu/pmu/fw.h>
 #include <nvgpu/pmu/debug.h>
-#include <nvgpu/boardobj.h>
-#include <nvgpu/boardobjgrp.h>
 #include <nvgpu/pmu/pmu_pstate.h>
-#include <nvgpu/nvgpu_err.h>
+#endif
+
+#ifdef NVGPU_DGPU_SUPPORT
+#include <nvgpu/sec2/lsfm.h>
+#endif
 
 #ifdef NVGPU_FEATURE_LS_PMU
 /* PMU locks used to sync with PMU-RTOS */
@@ -378,10 +380,11 @@ exit:
 void nvgpu_pmu_remove_support(struct gk20a *g, struct nvgpu_pmu *pmu)
 {
 	if(pmu != NULL) {
+#ifdef NVGPU_FEATURE_LS_PMU
 		if (pmu->remove_support != NULL) {
 			pmu->remove_support(g->pmu);
 		}
-
+#endif
 		nvgpu_kfree(g, g->pmu);
 		g->pmu = NULL;
 	}

drivers/gpu/nvgpu/common/power_features/pg/pg.c

@@ -21,8 +21,10 @@
  */
 
 #include <nvgpu/gk20a.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu.h>
 #include <nvgpu/pmu/pmu_pg.h>
+#endif
 #include <nvgpu/power_features/pg.h>
 
 bool nvgpu_pg_elpg_is_enabled(struct gk20a *g)

drivers/gpu/nvgpu/hal/clk/clk_gm20b.c

@@ -32,6 +32,7 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/therm.h>
+#include <nvgpu/pmu/pmuif/ctrlclk.h>
 
 #include "clk_gm20b.h"
 

drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c

@@ -32,7 +32,9 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/tsg.h>
 #include <nvgpu/preempt.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/mutex.h>
+#endif
 
 #include "preempt_gk20a.h"
 

drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c

@@ -37,7 +37,9 @@
 #include <nvgpu/engine_status.h>
 #include <nvgpu/preempt.h>
 #include <nvgpu/nvgpu_err.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/mutex.h>
+#endif
 
 #include "preempt_gv11b.h"
 

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c

@@ -27,6 +27,7 @@
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/soc.h>
 #include <nvgpu/safe_ops.h>
+#include <nvgpu/pmu/pmuif/ctrlclk.h>
 
 #include "gr_falcon_gm20b.h"
 #include "common/gr/gr_falcon_priv.h"

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -40,7 +40,9 @@
 #include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/gr/gr_falcon.h>
 #include <nvgpu/gr/setup.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/pmu_perfmon.h>
+#endif
 #include <nvgpu/gr/fecs_trace.h>
 
 #include "hal/mm/mm_gk20a.h"
@@ -105,7 +107,9 @@
 
 #include "hal/fifo/channel_gk20a.h"
 #include "hal/fifo/channel_gm20b.h"
+#ifdef NVGPU_FEATURE_LS_PMU
 #include "common/pmu/pg/pg_sw_gm20b.h"
+#endif
 
 #include "hal_gm20b.h"
 #include "hal_gm20b_litter.h"

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -41,7 +41,9 @@
 #include <nvgpu/gr/fecs_trace.h>
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/gr_intr.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/pmu_perfmon.h>
+#endif
 
 #include "hal/mm/mm_gk20a.h"
 #include "hal/mm/mm_gm20b.h"
@@ -112,9 +114,11 @@
 #include "hal/gr/gr/gr_gk20a.h"
 #include "hal/gr/gr/gr_gp10b.h"
 #include "hal/gr/gr/gr_gm20b.h"
+#ifdef NVGPU_FEATURE_LS_PMU
 #include "hal/pmu/pmu_gk20a.h"
 #include "hal/pmu/pmu_gm20b.h"
 #include "hal/pmu/pmu_gp10b.h"
+#endif
 #include "hal/sync/syncpt_cmdbuf_gk20a.h"
 #include "hal/sync/sema_cmdbuf_gk20a.h"
 #include "hal/falcon/falcon_gk20a.h"
@@ -123,9 +127,10 @@
 #include "hal/top/top_gm20b.h"
 #include "hal/top/top_gp10b.h"
 #include "hal/pramin/pramin_init.h"
-
+#ifdef NVGPU_FEATURE_LS_PMU
 #include "common/pmu/pg/pg_sw_gm20b.h"
 #include "common/pmu/pg/pg_sw_gp10b.h"
+#endif
 #include "hal/fifo/channel_gk20a.h"
 #include "hal/fifo/channel_gm20b.h"
 #include "common/clk_arb/clk_arb_gp10b.h"

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -28,7 +28,9 @@
 #include <nvgpu/regops.h>
 #include <nvgpu/gr/gr_falcon.h>
 #include <nvgpu/gr/gr.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/pmu_perfmon.h>
+#endif
 
 #include "hal/mm/mm_gp10b.h"
 #include "hal/mm/mm_gv11b.h"
@@ -124,10 +126,11 @@
 #include "hal/gr/gr/gr_gp10b.h"
 #include "hal/gr/gr/gr_gv100.h"
 #include "hal/gr/gr/gr_gv11b.h"
+#ifdef NVGPU_FEATURE_LS_PMU
 #include "hal/pmu/pmu_gk20a.h"
 #include "hal/pmu/pmu_gm20b.h"
+#endif
 #include "hal/pmu/pmu_gp106.h"
-#include "hal/pmu/pmu_gp10b.h"
 #include "hal/pmu/pmu_gv11b.h"
 #include "hal/sync/syncpt_cmdbuf_gv11b.h"
 #include "hal/sync/sema_cmdbuf_gv11b.h"
@@ -138,10 +141,11 @@
 #include "hal/top/top_gp10b.h"
 #include "hal/top/top_gv11b.h"
 
-
+#ifdef NVGPU_FEATURE_LS_PMU
 #include "common/pmu/pg/pg_sw_gm20b.h"
 #include "common/pmu/pg/pg_sw_gp106.h"
 #include "common/pmu/pg/pg_sw_gv11b.h"
+#endif
 #include "hal/fifo/channel_gk20a.h"
 #include "hal/fifo/channel_gm20b.h"
 #include "hal/fifo/channel_gv11b.h"

drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c

@@ -29,7 +29,9 @@
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/firmware.h>
 #include <nvgpu/bug.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/cmd.h>
+#endif
 
 #include "pmu_gv11b.h"
 

drivers/gpu/nvgpu/hal/rc/rc_gv11b.c

@@ -38,7 +38,9 @@
 #include <nvgpu/power_features/power_features.h>
 #include <nvgpu/gr/fecs_trace.h>
 #include <nvgpu/preempt.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/mutex.h>
+#endif
 
 #include "rc_gv11b.h"
 

drivers/gpu/nvgpu/include/nvgpu/pmu.h

@@ -31,6 +31,7 @@
 #include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/falcon.h>
 #include <nvgpu/timers.h>
+#ifdef NVGPU_FEATURE_LS_PMU
 #include <nvgpu/pmu/queue.h>
 #include <nvgpu/pmu/msg.h>
 #include <nvgpu/pmu/fw.h>
@@ -41,6 +42,7 @@ struct nvgpu_pmu_lsfm;
 struct pmu_super_surface;
 struct nvgpu_pmu_pg;
 struct nvgpu_pmu_perfmon;
+#endif
 
 #define nvgpu_pmu_dbg(g, fmt, args...) \
 	nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
@@ -87,6 +89,7 @@ struct nvgpu_clk_pmupstate;
 /* pmu load const defines */
 #define PMU_BUSY_CYCLES_NORM_MAX		(1000U)
 
+#ifdef NVGPU_FEATURE_LS_PMU
 struct rpc_handler_payload {
 	void *rpc_buff;
 	bool is_mem_free_set;
@@ -111,6 +114,7 @@ struct pmu_payload {
 	struct pmu_in_out_payload_desc out;
 	struct pmu_rpc_desc rpc;
 };
+#endif
 
 struct pmu_ucode_desc {
 	u32 descriptor_size;
@@ -150,6 +154,7 @@ struct nvgpu_pmu {
 	bool isr_enabled;
 	struct nvgpu_mutex isr_mutex;
 	struct nvgpu_falcon *flcn;
+#ifdef NVGPU_FEATURE_LS_PMU
 	struct nvgpu_allocator dmem;
 	struct nvgpu_mem trace_buf;
 	struct pmu_sha1_gid gid_info;
@@ -171,8 +176,10 @@ struct nvgpu_pmu {
 			struct nv_pmu_rpc_header *rpc);
 	void (*therm_event_handler)(struct gk20a *g, struct nvgpu_pmu *pmu,
 		struct pmu_msg *msg, struct nv_pmu_rpc_header *rpc);
+#endif
 };
 
+#ifdef NVGPU_FEATURE_LS_PMU
 /*!
  * Structure/object which single register write need to be done during PG init
  * sequence to set PROD values.
@@ -187,11 +194,16 @@ int nvgpu_pmu_lock_acquire(struct gk20a *g, struct nvgpu_pmu *pmu,
 	u32 id, u32 *token);
 int nvgpu_pmu_lock_release(struct gk20a *g, struct nvgpu_pmu *pmu,
 	u32 id, u32 *token);
+#endif
 
 /* PMU RTOS init/setup functions */
 int nvgpu_pmu_early_init(struct gk20a *g, struct nvgpu_pmu **pmu_p);
+
+#ifdef NVGPU_FEATURE_LS_PMU
 int nvgpu_pmu_init(struct gk20a *g, struct nvgpu_pmu *pmu);
 int nvgpu_pmu_destroy(struct gk20a *g, struct nvgpu_pmu *pmu);
+#endif
+
 void nvgpu_pmu_remove_support(struct gk20a *g, struct nvgpu_pmu *pmu);
 
 /* PMU H/W error functions */

userspace/units/fuse/nvgpu-fuse-tu104.c

@@ -27,6 +27,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/fuse.h>
 #include <nvgpu/hal_init.h>
+#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include "hal/fuse/fuse_gm20b.h"
 
 #include "nvgpu-fuse-priv.h"