From b6b56bd556f4fb6a7f99f54331558e48ac4550ca Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Wed, 6 Feb 2019 14:57:06 +0530 Subject: [PATCH] gpu: nvgpu: isolate common & hal falcon_reset functions nvgpu_falcon_reset should handle engine specific falcon reset or resort to falcon CPU reset. gk20a_falcon_reset is supposed to be hal API that will reset the falcon CPU. Hence move the dependent engine reset to nvgpu_falcon_reset. JIRA NVGPU-1459 Change-Id: I1b15f31a8bbb515736af5b0122ce206be0811bbc Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2015590 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/falcon/falcon.c | 19 +++++++++++------- .../gpu/nvgpu/common/falcon/falcon_gk20a.c | 20 ++++++------------- drivers/gpu/nvgpu/common/falcon/falcon_priv.h | 2 +- 3 files changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 681ff105e..4d91f8f01 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -109,25 +109,30 @@ exit: int nvgpu_falcon_reset(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops; + struct gk20a *g; int status = 0; if (flcn == NULL) { return -EINVAL; } + g = flcn->g; flcn_ops = &flcn->flcn_ops; - if (flcn_ops->reset != NULL) { - status = flcn_ops->reset(flcn); - if (status == 0) { - status = nvgpu_falcon_mem_scrub_wait(flcn); - } + if (flcn->flcn_engine_dep_ops.reset_eng != NULL) { + /* falcon & engine reset */ + status = flcn->flcn_engine_dep_ops.reset_eng(g); + } else if (flcn_ops->reset != NULL) { + flcn_ops->reset(flcn); } else { - nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", - flcn->flcn_id); + nvgpu_warn(g, "Invalid op on falcon 0x%x ", flcn->flcn_id); status = -EINVAL; } + if (status == 0) { + status = nvgpu_falcon_mem_scrub_wait(flcn); + } + return status; } diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c index 12759185a..0657fd896 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c @@ -28,25 +28,17 @@ #include -static int gk20a_falcon_reset(struct nvgpu_falcon *flcn) +static void gk20a_falcon_reset(struct nvgpu_falcon *flcn) { struct gk20a *g = flcn->g; u32 base_addr = flcn->flcn_base; u32 unit_status = 0; - int status = 0; - if (flcn->flcn_engine_dep_ops.reset_eng != NULL) { - /* falcon & engine reset */ - status = flcn->flcn_engine_dep_ops.reset_eng(g); - } else { - /* do falcon CPU hard reset */ - unit_status = gk20a_readl(g, base_addr + - falcon_falcon_cpuctl_r()); - gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(), - (unit_status | falcon_falcon_cpuctl_hreset_f(1))); - } - - return status; + /* do falcon CPU hard reset */ + unit_status = gk20a_readl(g, base_addr + + falcon_falcon_cpuctl_r()); + gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(), + (unit_status | falcon_falcon_cpuctl_hreset_f(1))); } static bool gk20a_falcon_clear_halt_interrupt_status(struct nvgpu_falcon *flcn) diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_priv.h b/drivers/gpu/nvgpu/common/falcon/falcon_priv.h index 9a5e5c391..b4922b5f4 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_priv.h +++ b/drivers/gpu/nvgpu/common/falcon/falcon_priv.h @@ -173,7 +173,7 @@ struct nvgpu_falcon_engine_dependency_ops { }; struct nvgpu_falcon_ops { - int (*reset)(struct nvgpu_falcon *flcn); + void (*reset)(struct nvgpu_falcon *flcn); void (*set_irq)(struct nvgpu_falcon *flcn, bool enable, u32 intr_mask, u32 intr_dest); bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);