diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig index 8f3a43b3e..bbd5f6f08 100644 --- a/drivers/gpu/nvgpu/Kconfig +++ b/drivers/gpu/nvgpu/Kconfig @@ -146,10 +146,3 @@ config NVGPU_USE_TEGRA_ALLOC_FD fd limit. It is only available in Tegra kernel. - -config TEGRA_GPU_NEXT - bool "Turing family GPU" - depends on GK20A && ARCH_TEGRA_19x_SOC - default y - help - Support for NVIDIA Turing family of GPU diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index a70786d4a..b6f0f0abd 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -4,6 +4,7 @@ ccflags-y += -I$(srctree.nvgpu)/drivers/gpu/nvgpu/include ccflags-y += -I$(srctree.nvgpu)/drivers/gpu/nvgpu ccflags-y += -I$(srctree.nvgpu)/include ccflags-y += -I$(srctree.nvgpu)/include/uapi +ccflags-y += -I$(srctree.nvgpu-next)/drivers/gpu/nvgpu ccflags-y += -I$(srctree)/drivers/devfreq @@ -369,27 +370,3 @@ nvgpu-y += \ lpwr/rppg.o \ lpwr/lpwr.o \ gv100/clk_gv100.o - -nvgpu-$(CONFIG_TEGRA_GPU_NEXT) += \ - common/bus/bus_tu104.o \ - common/fb/fb_tu104.o \ - common/ltc/ltc_tu104.o \ - common/mc/mc_tu104.o - -nvgpu-$(CONFIG_TEGRA_GPU_NEXT) += \ - tu104/hal_tu104.o \ - tu104/fifo_tu104.o \ - tu104/gr_tu104.o \ - tu104/func_tu104.o \ - tu104/bios_tu104.o \ - tu104/nvlink_tu104.o \ - tu104/fbpa_tu104.o \ - tu104/gr_ctx_tu104.o \ - tu104/flcn_tu104.o \ - tu104/sec2_tu104.o \ - tu104/ecc_tu104.o \ - tu104/regops_tu104.o \ - tu104/acr_tu104.o - -nvgpu-$(CONFIG_TEGRA_GPU_NEXT) += \ - os/linux/os_ops_tu104.o diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index cc22a50c5..6cfce2352 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -222,21 +222,4 @@ srcs := os/posix/nvgpu.c \ gv100/pmu_gv100.c \ gv100/perf_gv100.c \ gv100/gsp_gv100.c \ - gv100/clk_gv100.c \ - common/bus/bus_tu104.c \ - common/fb/fb_tu104.c \ - common/ltc/ltc_tu104.c \ - common/mc/mc_tu104.c \ - tu104/bios_tu104.c \ - tu104/ecc_tu104.c \ - tu104/fbpa_tu104.c \ - tu104/fifo_tu104.c \ - tu104/flcn_tu104.c \ - tu104/gr_ctx_tu104.c \ - tu104/gr_tu104.c \ - tu104/hal_tu104.c \ - tu104/nvlink_tu104.c \ - tu104/sec2_tu104.c \ - tu104/func_tu104.c \ - tu104/regops_tu104.c \ - tu104/acr_tu104.c + gv100/clk_gv100.c diff --git a/drivers/gpu/nvgpu/common/bus/bus_tu104.c b/drivers/gpu/nvgpu/common/bus/bus_tu104.c deleted file mode 100644 index cdc844aee..000000000 --- a/drivers/gpu/nvgpu/common/bus/bus_tu104.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include "gk20a/gk20a.h" - -#include "bus_tu104.h" - -#include "tu104/func_tu104.h" - -#include -#include - -int bus_tu104_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst) -{ - struct nvgpu_timeout timeout; - int err = 0; - u64 iova = nvgpu_inst_block_addr(g, bar2_inst); - u32 ptr_v = (u32)(iova >> bus_bar2_block_ptr_shift_v()); - - nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", ptr_v); - - err = nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); - if (err != 0) { - return err; - } - - nvgpu_func_writel(g, func_priv_bar2_block_r(), - nvgpu_aperture_mask(g, bar2_inst, - bus_bar2_block_target_sys_mem_ncoh_f(), - bus_bar2_block_target_sys_mem_coh_f(), - bus_bar2_block_target_vid_mem_f()) | - bus_bar2_block_mode_virtual_f() | - bus_bar2_block_ptr_f(ptr_v)); - - do { - u32 val = nvgpu_func_readl(g, - func_priv_bind_status_r()); - u32 pending = bus_bind_status_bar2_pending_v(val); - u32 outstanding = bus_bind_status_bar2_outstanding_v(val); - if (!pending && !outstanding) { - break; - } - - nvgpu_udelay(5); - } while (!nvgpu_timeout_expired(&timeout)); - - if (nvgpu_timeout_peek_expired(&timeout)) { - err = -EINVAL; - } - - return err; -} diff --git a/drivers/gpu/nvgpu/common/bus/bus_tu104.h b/drivers/gpu/nvgpu/common/bus/bus_tu104.h deleted file mode 100644 index 20edcfdf2..000000000 --- a/drivers/gpu/nvgpu/common/bus/bus_tu104.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_TU104_BUS__ -#define __NVGPU_TU104_BUS__ - -struct gk20a; -struct nvgpu_mem; - -int bus_tu104_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst); - -#endif diff --git a/drivers/gpu/nvgpu/common/fb/fb_tu104.c b/drivers/gpu/nvgpu/common/fb/fb_tu104.c deleted file mode 100644 index 4095cafeb..000000000 --- a/drivers/gpu/nvgpu/common/fb/fb_tu104.c +++ /dev/null @@ -1,576 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include "common/fb/fb_gv11b.h" -#include "common/mc/mc_tu104.h" - -#include "gk20a/gk20a.h" - -#include "tu104/func_tu104.h" - -#include "fb_tu104.h" - -#include "nvgpu/hw/tu104/hw_fb_tu104.h" -#include "nvgpu/hw/tu104/hw_func_tu104.h" - -void tu104_fb_enable_hub_intr(struct gk20a *g) -{ - u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r()); - u32 nonreplay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX)); - u32 replay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX)); - u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r()); - - intr_tu104_vector_en_set(g, - fb_mmu_int_vector_info_fault_vector_v(info_fault)); - intr_tu104_vector_en_set(g, - fb_mmu_int_vector_fault_notify_v(nonreplay_fault)); - intr_tu104_vector_en_set(g, - fb_mmu_int_vector_fault_error_v(nonreplay_fault)); - intr_tu104_vector_en_set(g, - fb_mmu_int_vector_fault_notify_v(replay_fault)); - intr_tu104_vector_en_set(g, - fb_mmu_int_vector_fault_error_v(replay_fault)); - intr_tu104_vector_en_set(g, - fb_mmu_int_vector_ecc_error_vector_v(ecc_error)); -} - -void tu104_fb_disable_hub_intr(struct gk20a *g) -{ - u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r()); - u32 nonreplay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX)); - u32 replay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX)); - u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r()); - - intr_tu104_vector_en_clear(g, - fb_mmu_int_vector_info_fault_vector_v(info_fault)); - intr_tu104_vector_en_clear(g, - fb_mmu_int_vector_fault_notify_v(nonreplay_fault)); - intr_tu104_vector_en_clear(g, - fb_mmu_int_vector_fault_error_v(nonreplay_fault)); - intr_tu104_vector_en_clear(g, - fb_mmu_int_vector_fault_notify_v(replay_fault)); - intr_tu104_vector_en_clear(g, - fb_mmu_int_vector_fault_error_v(replay_fault)); - intr_tu104_vector_en_clear(g, - fb_mmu_int_vector_ecc_error_vector_v(ecc_error)); -} - -bool tu104_fb_mmu_fault_pending(struct gk20a *g) -{ - u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r()); - u32 nonreplay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX)); - u32 replay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX)); - u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r()); - - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_notify_v(replay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_error_v(replay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_notify_v(nonreplay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_error_v(nonreplay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_info_fault_vector_v(info_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_ecc_error_vector_v(ecc_error))) { - return true; - } - - return false; -} - -static void tu104_fb_handle_mmu_fault(struct gk20a *g) -{ - u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r()); - u32 nonreplay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX)); - u32 replay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX)); - u32 fault_status = g->ops.fb.read_mmu_fault_status(g); - - nvgpu_log(g, gpu_dbg_intr, "mmu_fault_status = 0x%08x", fault_status); - - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_info_fault_vector_v(info_fault))) { - intr_tu104_intr_clear_leaf_vector(g, - fb_mmu_int_vector_info_fault_vector_v(info_fault)); - - gv11b_fb_handle_dropped_mmu_fault(g, fault_status); - gv11b_fb_handle_other_fault_notify(g, fault_status); - } - - if (gv11b_fb_is_fault_buf_enabled(g, - NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX)) { - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_notify_v(nonreplay_fault))) { - intr_tu104_intr_clear_leaf_vector(g, - fb_mmu_int_vector_fault_notify_v(nonreplay_fault)); - - gv11b_fb_handle_mmu_nonreplay_replay_fault(g, - fault_status, - NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX); - - /* - * When all the faults are processed, - * GET and PUT will have same value and mmu fault status - * bit will be reset by HW - */ - } - - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_error_v(nonreplay_fault))) { - intr_tu104_intr_clear_leaf_vector(g, - fb_mmu_int_vector_fault_error_v(nonreplay_fault)); - - gv11b_fb_handle_nonreplay_fault_overflow(g, - fault_status); - } - } - - if (gv11b_fb_is_fault_buf_enabled(g, - NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX)) { - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_notify_v(replay_fault))) { - intr_tu104_intr_clear_leaf_vector(g, - fb_mmu_int_vector_fault_notify_v(replay_fault)); - - gv11b_fb_handle_mmu_nonreplay_replay_fault(g, - fault_status, - NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX); - } - - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_error_v(replay_fault))) { - intr_tu104_intr_clear_leaf_vector(g, - fb_mmu_int_vector_fault_error_v(replay_fault)); - - gv11b_fb_handle_replay_fault_overflow(g, - fault_status); - } - } - - nvgpu_log(g, gpu_dbg_intr, "clear mmu fault status"); - g->ops.fb.write_mmu_fault_status(g, - fb_mmu_fault_status_valid_clear_f()); -} - -void tu104_fb_hub_isr(struct gk20a *g) -{ - u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r()); - u32 nonreplay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX)); - u32 replay_fault = nvgpu_readl(g, - fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX)); - u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r()); - u32 status; - - nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); - - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_ecc_error_vector_v(ecc_error))) { - nvgpu_info(g, "ecc uncorrected error notify"); - - intr_tu104_intr_clear_leaf_vector(g, - fb_mmu_int_vector_ecc_error_vector_v(ecc_error)); - - status = nvgpu_readl(g, fb_mmu_l2tlb_ecc_status_r()); - if (status) { - gv11b_handle_l2tlb_ecc_isr(g, status); - } - - status = nvgpu_readl(g, fb_mmu_hubtlb_ecc_status_r()); - if (status) { - gv11b_handle_hubtlb_ecc_isr(g, status); - } - - status = nvgpu_readl(g, fb_mmu_fillunit_ecc_status_r()); - if (status) { - gv11b_handle_fillunit_ecc_isr(g, status); - } - } - - if (intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_notify_v(replay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_error_v(replay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_notify_v(nonreplay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_fault_error_v(nonreplay_fault)) || - intr_tu104_vector_intr_pending(g, - fb_mmu_int_vector_info_fault_vector_v(info_fault))) { - nvgpu_log(g, gpu_dbg_intr, "MMU Fault"); - tu104_fb_handle_mmu_fault(g); - } - - nvgpu_mutex_release(&g->mm.hub_isr_mutex); -} - -void fb_tu104_write_mmu_fault_buffer_lo_hi(struct gk20a *g, u32 index, - u32 addr_lo, u32 addr_hi) -{ - nvgpu_func_writel(g, - func_priv_mmu_fault_buffer_lo_r(index), addr_lo); - nvgpu_func_writel(g, - func_priv_mmu_fault_buffer_hi_r(index), addr_hi); -} - -u32 fb_tu104_read_mmu_fault_buffer_get(struct gk20a *g, u32 index) -{ - return nvgpu_func_readl(g, - func_priv_mmu_fault_buffer_get_r(index)); -} - -void fb_tu104_write_mmu_fault_buffer_get(struct gk20a *g, u32 index, - u32 reg_val) -{ - nvgpu_func_writel(g, - func_priv_mmu_fault_buffer_get_r(index), - reg_val); -} - -u32 fb_tu104_read_mmu_fault_buffer_put(struct gk20a *g, u32 index) -{ - return nvgpu_func_readl(g, - func_priv_mmu_fault_buffer_put_r(index)); -} - -u32 fb_tu104_read_mmu_fault_buffer_size(struct gk20a *g, u32 index) -{ - return nvgpu_func_readl(g, - func_priv_mmu_fault_buffer_size_r(index)); -} - -void fb_tu104_write_mmu_fault_buffer_size(struct gk20a *g, u32 index, - u32 reg_val) -{ - nvgpu_func_writel(g, - func_priv_mmu_fault_buffer_size_r(index), - reg_val); -} - -void fb_tu104_read_mmu_fault_addr_lo_hi(struct gk20a *g, - u32 *addr_lo, u32 *addr_hi) -{ - *addr_lo = nvgpu_func_readl(g, - func_priv_mmu_fault_addr_lo_r()); - *addr_hi = nvgpu_func_readl(g, - func_priv_mmu_fault_addr_hi_r()); -} - -void fb_tu104_read_mmu_fault_inst_lo_hi(struct gk20a *g, - u32 *inst_lo, u32 *inst_hi) -{ - *inst_lo = nvgpu_func_readl(g, - func_priv_mmu_fault_inst_lo_r()); - *inst_hi = nvgpu_func_readl(g, - func_priv_mmu_fault_inst_hi_r()); -} - -u32 fb_tu104_read_mmu_fault_info(struct gk20a *g) -{ - return nvgpu_func_readl(g, - func_priv_mmu_fault_info_r()); -} - -u32 fb_tu104_read_mmu_fault_status(struct gk20a *g) -{ - return nvgpu_func_readl(g, - func_priv_mmu_fault_status_r()); -} - -void fb_tu104_write_mmu_fault_status(struct gk20a *g, u32 reg_val) -{ - nvgpu_func_writel(g, func_priv_mmu_fault_status_r(), - reg_val); -} - -int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) -{ - struct nvgpu_timeout timeout; - u32 addr_lo; - u32 data; - int err = 0; - - nvgpu_log_fn(g, " "); - - /* - * pagetables are considered sw states which are preserved after - * prepare_poweroff. When gk20a deinit releases those pagetables, - * common code in vm unmap path calls tlb invalidate that touches - * hw. Use the power_on flag to skip tlb invalidation when gpu - * power is turned off - */ - if (!g->power_on) { - return 0; - } - - addr_lo = u64_lo32(nvgpu_mem_get_addr(g, pdb) >> 12); - - err = nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); - if (err != 0) { - return err; - } - - nvgpu_mutex_acquire(&g->mm.tlb_lock); - - trace_gk20a_mm_tlb_invalidate(g->name); - - nvgpu_func_writel(g, func_priv_mmu_invalidate_pdb_r(), - fb_mmu_invalidate_pdb_addr_f(addr_lo) | - nvgpu_aperture_mask(g, pdb, - fb_mmu_invalidate_pdb_aperture_sys_mem_f(), - fb_mmu_invalidate_pdb_aperture_sys_mem_f(), - fb_mmu_invalidate_pdb_aperture_vid_mem_f())); - - nvgpu_func_writel(g, func_priv_mmu_invalidate_r(), - fb_mmu_invalidate_all_va_true_f() | - fb_mmu_invalidate_trigger_true_f()); - - do { - data = nvgpu_func_readl(g, - func_priv_mmu_invalidate_r()); - if (fb_mmu_invalidate_trigger_v(data) != - fb_mmu_invalidate_trigger_true_v()) { - break; - } - nvgpu_udelay(2); - } while (!nvgpu_timeout_expired_msg(&timeout, - "wait mmu invalidate")); - - trace_gk20a_mm_tlb_invalidate_done(g->name); - - nvgpu_mutex_release(&g->mm.tlb_lock); - return err; -} - -int fb_tu104_mmu_invalidate_replay(struct gk20a *g, - u32 invalidate_replay_val) -{ - int err = -ETIMEDOUT; - u32 reg_val; - struct nvgpu_timeout timeout; - - nvgpu_log_fn(g, " "); - - /* retry 200 times */ - err = nvgpu_timeout_init(g, &timeout, 200, NVGPU_TIMER_RETRY_TIMER); - if (err != 0) { - return err; - } - - nvgpu_mutex_acquire(&g->mm.tlb_lock); - - reg_val = nvgpu_func_readl(g, func_priv_mmu_invalidate_r()); - - reg_val |= fb_mmu_invalidate_all_va_true_f() | - fb_mmu_invalidate_all_pdb_true_f() | - invalidate_replay_val | - fb_mmu_invalidate_trigger_true_f(); - - nvgpu_func_writel(g, func_priv_mmu_invalidate_r(), reg_val); - - do { - reg_val = nvgpu_func_readl(g, - func_priv_mmu_invalidate_r()); - if (fb_mmu_invalidate_trigger_v(reg_val) != - fb_mmu_invalidate_trigger_true_v()) { - err = 0; - break; - } - nvgpu_udelay(5); - } while (!nvgpu_timeout_expired_msg(&timeout, - "invalidate replay failed on 0x%llx")); - if (err) { - nvgpu_err(g, "invalidate replay timedout"); - } - - nvgpu_mutex_release(&g->mm.tlb_lock); - return err; -} - -void fb_tu104_init_cbc(struct gk20a *g, struct gr_gk20a *gr) -{ - u64 base_divisor; - u64 compbit_store_base; - u64 compbit_store_pa; - u64 cbc_start_addr, cbc_end_addr; - u64 cbc_top; - u32 cbc_top_size; - u32 cbc_max; - - compbit_store_pa = nvgpu_mem_get_addr(g, &gr->compbit_store.mem); - base_divisor = g->ops.ltc.get_cbc_base_divisor(g); - compbit_store_base = DIV_ROUND_UP(compbit_store_pa, base_divisor); - - cbc_start_addr = (u64)g->ltc_count * (compbit_store_base << - fb_mmu_cbc_base_address_alignment_shift_v()); - cbc_end_addr = cbc_start_addr + gr->compbit_backing_size; - - cbc_top = (cbc_end_addr / g->ltc_count) >> - fb_mmu_cbc_base_address_alignment_shift_v(); - cbc_top_size = u64_lo32(cbc_top) - compbit_store_base; - - nvgpu_writel(g, fb_mmu_cbc_top_r(), - fb_mmu_cbc_top_size_f(cbc_top_size)); - - cbc_max = nvgpu_readl(g, fb_mmu_cbc_max_r()); - cbc_max = set_field(cbc_max, - fb_mmu_cbc_max_comptagline_m(), - fb_mmu_cbc_max_comptagline_f(gr->max_comptag_lines)); - nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max); - - nvgpu_writel(g, fb_mmu_cbc_base_r(), - fb_mmu_cbc_base_address_f(compbit_store_base)); - - nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, - "compbit base.pa: 0x%x,%08x cbc_base:0x%llx\n", - (u32)(compbit_store_pa >> 32), - (u32)(compbit_store_pa & 0xffffffff), - compbit_store_base); - - gr->compbit_store.base_hw = compbit_store_base; - - g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, - 0, gr->max_comptag_lines - 1); -} - -static int tu104_fb_wait_mmu_bind(struct gk20a *g) -{ - struct nvgpu_timeout timeout; - u32 val; - int err; - - err = nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); - if (err) { - return err; - } - - do { - val = nvgpu_readl(g, fb_mmu_bind_r()); - if ((val & fb_mmu_bind_trigger_true_f()) != - fb_mmu_bind_trigger_true_f()) { - return 0; - } - nvgpu_udelay(2); - } while (!nvgpu_timeout_expired_msg(&timeout, "mmu bind timedout")); - - return -ETIMEDOUT; -} - -int tu104_fb_apply_pdb_cache_war(struct gk20a *g) -{ - u64 inst_blk_base_addr; - u32 inst_blk_addr; - u32 i; - int err; - - if (!nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) { - return -EINVAL; - } - - inst_blk_base_addr = nvgpu_mem_get_addr(g, &g->pdb_cache_war_mem); - - /* Bind 256 instance blocks to unused engine ID 0x0 */ - for (i = 0U; i < 256U; i++) { - inst_blk_addr = u64_lo32((inst_blk_base_addr + (i * PAGE_SIZE)) - >> fb_mmu_bind_imb_addr_alignment_v()); - - nvgpu_writel(g, fb_mmu_bind_imb_r(), - fb_mmu_bind_imb_addr_f(inst_blk_addr) | - nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, - fb_mmu_bind_imb_aperture_sys_mem_nc_f(), - fb_mmu_bind_imb_aperture_sys_mem_c_f(), - fb_mmu_bind_imb_aperture_vid_mem_f())); - - nvgpu_writel(g, fb_mmu_bind_r(), - fb_mmu_bind_engine_id_f(0x0U) | - fb_mmu_bind_trigger_true_f()); - - err = tu104_fb_wait_mmu_bind(g); - if (err) { - return err; - } - } - - /* first unbind */ - nvgpu_writel(g, fb_mmu_bind_imb_r(), - fb_mmu_bind_imb_aperture_f(0x1U) | - fb_mmu_bind_imb_addr_f(0x0U)); - - nvgpu_writel(g, fb_mmu_bind_r(), - fb_mmu_bind_engine_id_f(0x0U) | - fb_mmu_bind_trigger_true_f()); - - err = tu104_fb_wait_mmu_bind(g); - if (err) { - return err; - } - - /* second unbind */ - nvgpu_writel(g, fb_mmu_bind_r(), - fb_mmu_bind_engine_id_f(0x0U) | - fb_mmu_bind_trigger_true_f()); - - err = tu104_fb_wait_mmu_bind(g); - if (err) { - return err; - } - - /* Bind 257th (last) instance block that reserves PDB cache entry 255 */ - inst_blk_addr = u64_lo32((inst_blk_base_addr + (256 * PAGE_SIZE)) - >> fb_mmu_bind_imb_addr_alignment_v()); - - nvgpu_writel(g, fb_mmu_bind_imb_r(), - fb_mmu_bind_imb_addr_f(inst_blk_addr) | - nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, - fb_mmu_bind_imb_aperture_sys_mem_nc_f(), - fb_mmu_bind_imb_aperture_sys_mem_c_f(), - fb_mmu_bind_imb_aperture_vid_mem_f())); - - nvgpu_writel(g, fb_mmu_bind_r(), - fb_mmu_bind_engine_id_f(0x0U) | - fb_mmu_bind_trigger_true_f()); - - err = tu104_fb_wait_mmu_bind(g); - if (err) { - return err; - } - - return 0; -} diff --git a/drivers/gpu/nvgpu/common/fb/fb_tu104.h b/drivers/gpu/nvgpu/common/fb/fb_tu104.h deleted file mode 100644 index 03442c7ed..000000000 --- a/drivers/gpu/nvgpu/common/fb/fb_tu104.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __FB_TU104_H__ -#define __FB_TU104_H__ - -#include - -struct gk20a; -struct gr_gk20a; -struct nvgpu_mem; - -void tu104_fb_enable_hub_intr(struct gk20a *g); -void tu104_fb_disable_hub_intr(struct gk20a *g); -bool tu104_fb_mmu_fault_pending(struct gk20a *g); -void tu104_fb_hub_isr(struct gk20a *g); - -void fb_tu104_write_mmu_fault_buffer_lo_hi(struct gk20a *g, u32 index, - u32 addr_lo, u32 addr_hi); -u32 fb_tu104_read_mmu_fault_buffer_get(struct gk20a *g, u32 index); -void fb_tu104_write_mmu_fault_buffer_get(struct gk20a *g, u32 index, - u32 reg_val); -u32 fb_tu104_read_mmu_fault_buffer_put(struct gk20a *g, u32 index); -u32 fb_tu104_read_mmu_fault_buffer_size(struct gk20a *g, u32 index); -void fb_tu104_write_mmu_fault_buffer_size(struct gk20a *g, u32 index, - u32 reg_val); -void fb_tu104_read_mmu_fault_addr_lo_hi(struct gk20a *g, - u32 *addr_lo, u32 *addr_hi); -void fb_tu104_read_mmu_fault_inst_lo_hi(struct gk20a *g, - u32 *inst_lo, u32 *inst_hi); -u32 fb_tu104_read_mmu_fault_info(struct gk20a *g); -u32 fb_tu104_read_mmu_fault_status(struct gk20a *g); -void fb_tu104_write_mmu_fault_status(struct gk20a *g, u32 reg_val); - -int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); -int fb_tu104_mmu_invalidate_replay(struct gk20a *g, - u32 invalidate_replay_val); - -void fb_tu104_init_cbc(struct gk20a *g, struct gr_gk20a *gr); - -int tu104_fb_apply_pdb_cache_war(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.c b/drivers/gpu/nvgpu/common/ltc/ltc_tu104.c deleted file mode 100644 index 500497fe6..000000000 --- a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -#include - -#include "gk20a/gk20a.h" - -#include "ltc_tu104.h" - -#include "common/ltc/ltc_gv11b.h" - -#include - -void ltc_tu104_init_fs_state(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - u32 reg; - - gv11b_ltc_init_fs_state(g); - - reg = nvgpu_readl(g, ltc_ltcs_ltss_cbc_param2_r()); - gr->slices_per_ltc = - ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(reg); - gr->cacheline_size = - 512U << ltc_ltcs_ltss_cbc_param2_cache_line_size_v(reg); -} - -u64 ltc_tu104_get_cbc_base_divisor(struct gk20a *g) -{ - return (u64)g->ltc_count << - ltc_ltcs_ltss_cbc_base_alignment_shift_v(); -} - -int ltc_tu104_init_comptags(struct gk20a *g, struct gr_gk20a *gr) -{ - /* max memory size (MB) to cover */ - u32 max_size = gr->max_comptag_mem; - /* one tag line covers 64KB */ - u32 max_comptag_lines = max_size << 4U; - u32 compbit_backing_size; - u32 hw_max_comptag_lines; - u32 cbc_param; - u32 ctags_size; - u32 ctags_per_cacheline; - u32 amap_divide_rounding, amap_swizzle_rounding; - int err; - - nvgpu_log_fn(g, " "); - - if (max_comptag_lines == 0U) { - return 0; - } - - /* Already initialized */ - if (gr->max_comptag_lines) { - return 0; - } - - hw_max_comptag_lines = - ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); - if (max_comptag_lines > hw_max_comptag_lines) { - max_comptag_lines = hw_max_comptag_lines; - } - - cbc_param = nvgpu_readl(g, ltc_ltcs_ltss_cbc_param_r()); - - ctags_size = - ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(cbc_param); - ctags_per_cacheline = gr->cacheline_size / ctags_size; - - amap_divide_rounding = (2 * 1024) << - ltc_ltcs_ltss_cbc_param_amap_divide_rounding_v(cbc_param); - amap_swizzle_rounding = (64 * 1024) << - ltc_ltcs_ltss_cbc_param_amap_swizzle_rounding_v(cbc_param); - - compbit_backing_size = - roundup(max_comptag_lines * ctags_size, gr->cacheline_size); - compbit_backing_size = - compbit_backing_size * gr->slices_per_ltc * g->ltc_count; - - compbit_backing_size += g->ltc_count * amap_divide_rounding; - compbit_backing_size += amap_swizzle_rounding; - - /* must be a multiple of 64KB */ - compbit_backing_size = roundup(compbit_backing_size, 64 * 1024); - - err = nvgpu_ltc_alloc_cbc(g, compbit_backing_size, true); - if (err) { - return err; - } - - err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines); - if (err) { - return err; - } - - gr->max_comptag_lines = max_comptag_lines; - gr->comptags_per_cacheline = ctags_per_cacheline; - gr->gobs_per_comptagline_per_slice = ctags_size; - gr->compbit_backing_size = compbit_backing_size; - - nvgpu_log_info(g, "compbit backing store size : %d", - compbit_backing_size); - nvgpu_log_info(g, "max comptag lines : %d", - max_comptag_lines); - nvgpu_log_info(g, "gobs_per_comptagline_per_slice: %d", - gr->gobs_per_comptagline_per_slice); - - return 0; -} - -int ltc_tu104_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, - u32 min, u32 max) -{ - struct gr_gk20a *gr = &g->gr; - struct nvgpu_timeout timeout; - int err = 0; - u32 ltc, slice, ctrl1, val, hw_op = 0U; - u32 slices_per_ltc = gr->slices_per_ltc; - u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); - u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); - const u32 max_lines = 16384U; - - nvgpu_log_fn(g, " "); - - trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max); - - if (gr->compbit_store.mem.size == 0U) { - return 0; - } - - while (1) { - const u32 iter_max = min(min + max_lines - 1, max); - bool full_cache_op = true; - - nvgpu_mutex_acquire(&g->mm.l2_op_lock); - - nvgpu_log_info(g, "clearing CBC lines %u..%u", min, iter_max); - - if (op == gk20a_cbc_op_clear) { - nvgpu_writel( - g, ltc_ltcs_ltss_cbc_ctrl2_r(), - ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f( - min)); - nvgpu_writel( - g, ltc_ltcs_ltss_cbc_ctrl3_r(), - ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f( - iter_max)); - hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(); - full_cache_op = false; - } else if (op == gk20a_cbc_op_clean) { - /* this is full-cache op */ - hw_op = ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(); - } else if (op == gk20a_cbc_op_invalidate) { - /* this is full-cache op */ - hw_op = ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(); - } else { - nvgpu_err(g, "Unknown op: %u", (unsigned)op); - err = -EINVAL; - goto out; - } - - nvgpu_writel(g, ltc_ltcs_ltss_cbc_ctrl1_r(), - nvgpu_readl(g, - ltc_ltcs_ltss_cbc_ctrl1_r()) | hw_op); - - for (ltc = 0; ltc < g->ltc_count; ltc++) { - for (slice = 0; slice < slices_per_ltc; slice++) { - - ctrl1 = ltc_ltc0_lts0_cbc_ctrl1_r() + - ltc * ltc_stride + slice * lts_stride; - - nvgpu_timeout_init(g, &timeout, 2000, - NVGPU_TIMER_RETRY_TIMER); - do { - val = nvgpu_readl(g, ctrl1); - if (!(val & hw_op)) { - break; - } - nvgpu_udelay(5); - } while (!nvgpu_timeout_expired(&timeout)); - - if (nvgpu_timeout_peek_expired(&timeout)) { - nvgpu_err(g, "comp tag clear timeout"); - err = -EBUSY; - goto out; - } - } - } - - /* are we done? */ - if (full_cache_op || iter_max == max) { - break; - } - - /* note: iter_max is inclusive upper bound */ - min = iter_max + 1; - - /* give a chance for higher-priority threads to progress */ - nvgpu_mutex_release(&g->mm.l2_op_lock); - } -out: - trace_gk20a_ltc_cbc_ctrl_done(g->name); - nvgpu_mutex_release(&g->mm.l2_op_lock); - return err; -} - -void tu104_ltc_isr(struct gk20a *g) -{ - unsigned int ltc, slice; - - /* Go through all the LTCs explicitly */ - for (ltc = 0; ltc < g->ltc_count; ltc++) { - for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { - gv11b_ltc_lts_isr(g, ltc, slice); - } - } -} diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.h b/drivers/gpu/nvgpu/common/ltc/ltc_tu104.h deleted file mode 100644 index d75d75824..000000000 --- a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef LTC_TU104_H -#define LTC_TU104_H - -#include - -enum gk20a_cbc_op; -struct gk20a; -struct gr_gk20a; - -void tu104_ltc_isr(struct gk20a *g); -u64 ltc_tu104_get_cbc_base_divisor(struct gk20a *g); -void ltc_tu104_init_fs_state(struct gk20a *g); -int ltc_tu104_init_comptags(struct gk20a *g, struct gr_gk20a *gr); -int ltc_tu104_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, - u32 min, u32 max); - -#endif diff --git a/drivers/gpu/nvgpu/common/mc/mc_tu104.c b/drivers/gpu/nvgpu/common/mc/mc_tu104.c deleted file mode 100644 index 73b9a80ec..000000000 --- a/drivers/gpu/nvgpu/common/mc/mc_tu104.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include "gk20a/gk20a.h" - -#include "common/mc/mc_gp10b.h" -#include "mc_tu104.h" - -#include "tu104/func_tu104.h" - -#include "nvgpu/hw/tu104/hw_mc_tu104.h" -#include "nvgpu/hw/tu104/hw_func_tu104.h" -#include "nvgpu/hw/tu104/hw_ctrl_tu104.h" - -/* helper to set leaf_reg_bit in LEAF_EN_SET(leaf_reg_index) register */ -void intr_tu104_leaf_en_set(struct gk20a *g, u32 leaf_reg_index, - u32 leaf_reg_bit) -{ - u32 val; - - val = nvgpu_func_readl(g, - func_priv_cpu_intr_leaf_en_set_r(leaf_reg_index)); - - val |= BIT(leaf_reg_bit); - nvgpu_func_writel(g, - func_priv_cpu_intr_leaf_en_set_r(leaf_reg_index), - val); -} - -/* helper to set leaf_reg_bit in LEAF_EN_CLEAR(leaf_reg_index) register */ -void intr_tu104_leaf_en_clear(struct gk20a *g, u32 leaf_reg_index, - u32 leaf_reg_bit) -{ - u32 val; - - val = nvgpu_func_readl(g, - func_priv_cpu_intr_leaf_en_clear_r(leaf_reg_index)); - - val |= BIT(leaf_reg_bit); - nvgpu_func_writel(g, - func_priv_cpu_intr_leaf_en_clear_r(leaf_reg_index), - val); -} - -/* helper to set leaf_reg_bit in LEAF(leaf_reg_index) register */ -static void intr_tu104_leaf_clear(struct gk20a *g, u32 leaf_reg_index, - u32 leaf_reg_bit) -{ - nvgpu_func_writel(g, - func_priv_cpu_intr_leaf_r(leaf_reg_index), - BIT(leaf_reg_bit)); -} - -/* helper to set top_reg_bit in TOP_EN_SET(top_reg_index) register */ -void intr_tu104_top_en_set(struct gk20a *g, u32 top_reg_index, - u32 top_reg_bit) -{ - u32 val; - - val = nvgpu_func_readl(g, - func_priv_cpu_intr_top_en_set_r(top_reg_index)); - - val |= BIT(top_reg_bit); - nvgpu_func_writel(g, - func_priv_cpu_intr_top_en_set_r(top_reg_index), - val); -} - -/* helper to enable interrupt vector in both LEAF and TOP registers */ -void intr_tu104_vector_en_set(struct gk20a *g, u32 intr_vector) -{ - intr_tu104_leaf_en_set(g, - NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector), - NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector)); - - intr_tu104_top_en_set(g, - NV_CPU_INTR_SUBTREE_TO_TOP_IDX( - NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(intr_vector)), - (NV_CPU_INTR_SUBTREE_TO_TOP_BIT( - NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(intr_vector)))); -} - -/* helper to disable interrupt vector in LEAF register */ -void intr_tu104_vector_en_clear(struct gk20a *g, u32 intr_vector) -{ - intr_tu104_leaf_en_clear(g, - NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector), - NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector)); -} - -/* helper to clear an interrupt vector in LEAF register */ -void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector) -{ - intr_tu104_leaf_clear(g, - NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector), - NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector)); -} - -/* helper to check if interrupt is pending for interrupt vector */ -bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector) -{ - u32 leaf_val; - - leaf_val = nvgpu_func_readl(g, - func_priv_cpu_intr_leaf_r( - NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector))); - - return leaf_val & BIT(NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector)); -} - -static void intr_tu104_stall_enable(struct gk20a *g) -{ - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - - nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), - 0xffffffff); - - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = - mc_intr_pfifo_pending_f() | - mc_intr_priv_ring_pending_f() | - mc_intr_pbus_pending_f() | - mc_intr_ltc_pending_f() | - mc_intr_nvlink_pending_f() | - mc_intr_pfb_pending_f() | - eng_intr_mask; - - nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); -} - -static void intr_tu104_nonstall_enable(struct gk20a *g) -{ - u32 i; - u32 nonstall_intr_base = 0; - u64 nonstall_intr_mask = 0; - u32 active_engine_id, intr_mask; - - /* Keep NV_PMC_INTR(1) disabled */ - nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffff); - - /* - * Enable nonstall interrupts in TOP - * Enable all engine specific non-stall interrupts in LEAF - * - * We need to read and add - * ctrl_legacy_engine_nonstall_intr_base_vectorid_r() - * to get correct interrupt id in NV_CTRL tree - */ - nonstall_intr_base = nvgpu_readl(g, - ctrl_legacy_engine_nonstall_intr_base_vectorid_r()); - - for (i = 0; i < g->fifo.num_engines; i++) { - active_engine_id = g->fifo.active_engines_list[i]; - intr_mask = g->fifo.engine_info[active_engine_id].intr_mask; - - nonstall_intr_mask |= intr_mask << nonstall_intr_base; - } - - nvgpu_func_writel(g, - func_priv_cpu_intr_top_en_set_r( - NV_CPU_INTR_SUBTREE_TO_TOP_IDX( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)), - BIT(NV_CPU_INTR_SUBTREE_TO_TOP_BIT( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE))); - - nvgpu_func_writel(g, - func_priv_cpu_intr_leaf_en_set_r( - NV_CPU_INTR_SUBTREE_TO_LEAF_REG0( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)), - u64_lo32(nonstall_intr_mask)); - nvgpu_func_writel(g, - func_priv_cpu_intr_leaf_en_set_r( - NV_CPU_INTR_SUBTREE_TO_LEAF_REG1( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)), - u64_hi32(nonstall_intr_mask)); -} - -void intr_tu104_mask(struct gk20a *g) -{ - u32 size, reg, i; - - nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), - 0xffffffff); - - nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffff); - - size = func_priv_cpu_intr_top_en_clear__size_1_v(); - for (i = 0; i < size; i++) { - reg = func_priv_cpu_intr_top_en_clear_r(i); - nvgpu_func_writel(g, reg, 0xffffffff); - } -} - -/* Enable all required interrupts */ -void intr_tu104_enable(struct gk20a *g) -{ - intr_tu104_stall_enable(g); - intr_tu104_nonstall_enable(g); -} - -/* Return non-zero if nonstall interrupts are pending */ -u32 intr_tu104_nonstall(struct gk20a *g) -{ - u32 nonstall_intr_status; - u32 nonstall_intr_set_mask; - - nonstall_intr_status = - nvgpu_func_readl(g, func_priv_cpu_intr_top_r( - NV_CPU_INTR_SUBTREE_TO_TOP_IDX( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE))); - - nonstall_intr_set_mask = BIT( - NV_CPU_INTR_SUBTREE_TO_TOP_BIT( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)); - - return nonstall_intr_status & nonstall_intr_set_mask; -} - -/* pause all nonstall interrupts */ -void intr_tu104_nonstall_pause(struct gk20a *g) -{ - nvgpu_func_writel(g, - func_priv_cpu_intr_top_en_clear_r( - NV_CPU_INTR_SUBTREE_TO_TOP_IDX( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)), - BIT(NV_CPU_INTR_SUBTREE_TO_TOP_BIT( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE))); -} - -/* resume all nonstall interrupts */ -void intr_tu104_nonstall_resume(struct gk20a *g) -{ - nvgpu_func_writel(g, - func_priv_cpu_intr_top_en_set_r( - NV_CPU_INTR_SUBTREE_TO_TOP_IDX( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)), - BIT(NV_CPU_INTR_SUBTREE_TO_TOP_BIT( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE))); -} - -/* Handle and clear all nonstall interrupts */ -u32 intr_tu104_isr_nonstall(struct gk20a *g) -{ - u32 i; - u32 nonstall_intr_base = 0; - u64 nonstall_intr_mask = 0; - u64 nonstall_intr_mask_lo, nonstall_intr_mask_hi; - u32 intr_leaf_reg0, intr_leaf_reg1; - u32 active_engine_id, intr_mask; - u32 ops = 0; - - intr_leaf_reg0 = nvgpu_func_readl(g, - func_priv_cpu_intr_leaf_r( - NV_CPU_INTR_SUBTREE_TO_LEAF_REG0( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE))); - - intr_leaf_reg1 = nvgpu_func_readl(g, - func_priv_cpu_intr_leaf_r( - NV_CPU_INTR_SUBTREE_TO_LEAF_REG1( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE))); - - nonstall_intr_base = nvgpu_readl(g, - ctrl_legacy_engine_nonstall_intr_base_vectorid_r()); - - for (i = 0; i < g->fifo.num_engines; i++) { - active_engine_id = g->fifo.active_engines_list[i]; - intr_mask = g->fifo.engine_info[active_engine_id].intr_mask; - - nonstall_intr_mask = intr_mask << nonstall_intr_base; - nonstall_intr_mask_lo = u64_lo32(nonstall_intr_mask); - nonstall_intr_mask_hi = u64_hi32(nonstall_intr_mask); - - if ((nonstall_intr_mask_lo & intr_leaf_reg0) || - (nonstall_intr_mask_hi & intr_leaf_reg1)) { - nvgpu_log(g, gpu_dbg_intr, "nonstall intr from engine %d", - active_engine_id); - - nvgpu_func_writel(g, - func_priv_cpu_intr_leaf_r( - NV_CPU_INTR_SUBTREE_TO_LEAF_REG0( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)), - nonstall_intr_mask_lo); - - nvgpu_func_writel(g, - func_priv_cpu_intr_leaf_r( - NV_CPU_INTR_SUBTREE_TO_LEAF_REG1( - NV_CPU_INTR_TOP_NONSTALL_SUBTREE)), - nonstall_intr_mask_hi); - - ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE | - GK20A_NONSTALL_OPS_POST_EVENTS); - } - } - - return ops; -} - -/* Return non-zero if stall interrupts are pending */ -u32 intr_tu104_stall(struct gk20a *g) -{ - u32 mc_intr_0; - - mc_intr_0 = mc_gp10b_intr_stall(g); - if (mc_intr_0) { - return mc_intr_0; - } - - if (g->ops.mc.is_intr_hub_pending) { - return g->ops.mc.is_intr_hub_pending(g, 0); - } - - return 0; -} - -/* Return true if HUB interrupt is pending */ -bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) -{ - return g->ops.mm.mmu_fault_pending(g); -} - -/* pause all stall interrupts */ -void intr_tu104_stall_pause(struct gk20a *g) -{ - mc_gp10b_intr_stall_pause(g); - - g->ops.fb.disable_hub_intr(g); -} - -/* resume all stall interrupts */ -void intr_tu104_stall_resume(struct gk20a *g) -{ - mc_gp10b_intr_stall_resume(g); - - g->ops.fb.enable_hub_intr(g); -} - -#define MAX_INTR_TOP_REGS (2U) - -void intr_tu104_log_pending_intrs(struct gk20a *g) -{ - bool pending; - u32 intr, i; - - intr = intr_tu104_nonstall(g); - if (intr) { - nvgpu_info(g, "Pending nonstall intr=0x%08x", intr); - } - - intr = mc_gp10b_intr_stall(g); - if (intr) { - nvgpu_info(g, "Pending stall intr=0x%08x", intr); - } - - if (g->ops.mc.is_intr_hub_pending) { - pending = g->ops.mc.is_intr_hub_pending(g, 0); - if (pending) { - nvgpu_info(g, "Pending hub intr"); - } - } - - for (i = 0; i < MAX_INTR_TOP_REGS; i++) { - intr = nvgpu_func_readl(g, - func_priv_cpu_intr_top_r(i)); - if (intr == 0U) { - continue; - } - nvgpu_info(g, "Pending TOP%d intr=0x%08x", i, intr); - } -} - -void mc_tu104_fbpa_isr(struct gk20a *g) -{ - u32 intr_fbpa, fbpas; - u32 i, num_fbpas; - - intr_fbpa = gk20a_readl(g, mc_intr_fbpa_r()); - fbpas = mc_intr_fbpa_part_mask_v(intr_fbpa); - num_fbpas = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS); - - for (i = 0u; i < num_fbpas; i++) { - if (!(fbpas & (1 << i))) { - continue; - } - g->ops.fb.handle_fbpa_intr(g, i); - } -} diff --git a/drivers/gpu/nvgpu/common/mc/mc_tu104.h b/drivers/gpu/nvgpu/common/mc/mc_tu104.h deleted file mode 100644 index bfec0fa07..000000000 --- a/drivers/gpu/nvgpu/common/mc/mc_tu104.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_MC_TU104_H -#define NVGPU_MC_TU104_H - -#include - -#define NV_CPU_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32) -#define NV_CPU_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32) -#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(i) ((i)*2) -#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(i) (((i)*2) + 1) - -#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32) -#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32) -#define NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) - -#define NV_CPU_INTR_TOP_NONSTALL_SUBTREE 0 - -struct gk20a; - -void intr_tu104_leaf_en_set(struct gk20a *g, u32 leaf_reg_index, - u32 leaf_reg_bit); -void intr_tu104_leaf_en_clear(struct gk20a *g, u32 leaf_reg_index, - u32 leaf_reg_bit); -void intr_tu104_top_en_set(struct gk20a *g, u32 top_reg_index, - u32 top_reg_bit); -void intr_tu104_vector_en_set(struct gk20a *g, u32 intr_vector); -void intr_tu104_vector_en_clear(struct gk20a *g, u32 intr_vector); -bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector); -void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector); - -void intr_tu104_mask(struct gk20a *g); -void intr_tu104_enable(struct gk20a *g); -u32 intr_tu104_stall(struct gk20a *g); -void intr_tu104_stall_pause(struct gk20a *g); -void intr_tu104_stall_resume(struct gk20a *g); -u32 intr_tu104_nonstall(struct gk20a *g); -void intr_tu104_nonstall_pause(struct gk20a *g); -void intr_tu104_nonstall_resume(struct gk20a *g); -u32 intr_tu104_isr_nonstall(struct gk20a *g); -bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); -void intr_tu104_log_pending_intrs(struct gk20a *g); -void mc_tu104_fbpa_isr(struct gk20a *g); - -#endif /* NVGPU_MC_TU104_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_bus_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_bus_tu104.h deleted file mode 100644 index 3fbb51d28..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_bus_tu104.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_tu104_h_ -#define _hw_bus_tu104_h_ - -static inline u32 bus_sw_scratch_r(u32 i) -{ - return 0x00001400U + i*4U; -} -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1U << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1U << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1U << 3U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ccsr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ccsr_tu104.h deleted file mode 100644 index 1249cc25f..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ccsr_tu104.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_tu104_h_ -#define _hw_ccsr_tu104_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000U + i*8U; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004U + i*8U; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) -{ - return 0x400000U; -} -static inline u32 ccsr_channel_eng_faulted_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 ccsr_channel_eng_faulted_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 ccsr_channel_eng_faulted_reset_f(void) -{ - return 0x800000U; -} -static inline u32 ccsr_channel_eng_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h deleted file mode 100644 index 4226584cf..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce_tu104_h_ -#define _hw_ce_tu104_h_ - -static inline u32 ce_intr_status_r(u32 i) -{ - return 0x00104410U + i*128U; -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_invalid_config_pending_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_invalid_config_reset_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) -{ - return 0x10U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) -{ - return 0x10U; -} -static inline u32 ce_pce_map_r(void) -{ - return 0x00104028U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctrl_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctrl_tu104.h deleted file mode 100644 index 10209dfc2..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctrl_tu104.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctrl_tu104_h_ -#define _hw_ctrl_tu104_h_ - -static inline u32 ctrl_doorbell_r(u32 i) -{ - return 0x00b64000U + i*8U; -} -static inline u32 ctrl_doorbell_vector_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ctrl_doorbell_runlist_id_f(u32 v) -{ - return (v & 0x7fU) << 16U; -} -static inline u32 ctrl_virtual_channel_cfg_r(u32 i) -{ - return 0x00b65000U + i*4U; -} -static inline u32 ctrl_virtual_channel_cfg_pending_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ctrl_legacy_engine_nonstall_intr_base_vectorid_r(void) -{ - return 0x00b66884U; -} -static inline u32 ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctxsw_prog_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctxsw_prog_tu104.h deleted file mode 100644 index e29fe7447..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctxsw_prog_tu104.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_tu104_h_ -#define _hw_ctxsw_prog_tu104_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) -{ - return 0x00000011U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) -{ - return 0x00000012U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) -{ - return 0x00000021U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7U << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7U << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) -{ - return 0x00000094U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) -{ - return 0x00000064U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) -{ - return 0x00000074U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) -{ - return 0x00000078U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) -{ - return 0x0000007cU; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) -{ - return 0x000000b8U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) -{ - return 0x000000bcU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) -{ - return 0x000000c0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) -{ - return 0x000000c4U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) -{ - return 0x000000c8U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) -{ - return 0x000000ccU; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_falcon_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_falcon_tu104.h deleted file mode 100644 index 1fbcbae06..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_falcon_tu104.h +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_falcon_tu104_h_ -#define _hw_falcon_tu104_h_ - -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return 0x1U << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return 0x00000180U + i*16U; -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return 0x00000184U + i*16U; -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return 0x00000188U + i*16U; -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return 0x000001c0U + i*8U; -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return 0x000001c4U + i*8U; -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h deleted file mode 100644 index a113dd004..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h +++ /dev/null @@ -1,2299 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_tu104_h_ -#define _hw_fb_tu104_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void) -{ - return 0xffU << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return 0x1U << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return 0x1U << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) -{ - return 0x3U << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_bind_imb_r(void) -{ - return 0x00100cacU; -} -static inline u32 fb_mmu_bind_imb_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_bind_imb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_bind_imb_aperture_sys_mem_c_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_bind_imb_aperture_sys_mem_nc_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_bind_imb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_bind_imb_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_bind_r(void) -{ - return 0x00100cb0U; -} -static inline u32 fb_mmu_bind_engine_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_mmu_bind_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_r(void) -{ - return 0x001fac80U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return 0x3U << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_hshub_num_active_ltcs_r(void) -{ - return 0x001fbc20U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void) -{ - return 0xffU << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return 0x1U << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return 0x1U << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return 0x7U << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return 0x3U << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return 0x3fU << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return 0x1fU << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return 0x1U << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return 0x7U << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_r(void) -{ - return 0x00100e70U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e74U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e78U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_r(void) -{ - return 0x00100e7cU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_status_r(void) -{ - return 0x00100e84U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e88U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e8cU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_address_r(void) -{ - return 0x00100e90U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fillunit_ecc_status_r(void) -{ - return 0x00100e98U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) -{ - return 0x1U << 3U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 16U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return 0x1U << 18U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) -{ - return 0x00100e9cU; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) -{ - return 0x00100ea0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_address_r(void) -{ - return 0x00100ea4U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_niso_cfg1_r(void) -{ - return 0x00100c14U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void) -{ - return 0x1U << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_f(void) -{ - return 0x20000U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_niso_intr_r(void) -{ - return 0x00100a20U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_r(u32 i) -{ - return 0x00100a24U + i*4U; -} -static inline u32 fb_niso_intr_en__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_set_r(u32 i) -{ - return 0x00100a2cU + i*4U; -} -static inline u32 fb_niso_intr_en_set__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_r(u32 i) -{ - return 0x00100a34U + i*4U; -} -static inline u32 fb_niso_intr_en_clr__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) -{ - return 0x1U << 27U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) -{ - return 0x1U << 28U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) -{ - return 0x1U << 29U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) -{ - return 0x00100e24U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) -{ - return (r >> 1U) & 0x3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x6U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) -{ - return 0x00100e28U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_buffer_get_r(u32 i) -{ - return 0x00100e2cU + i*20U; -} -static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) -{ - return 0xfffffU << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_put_r(u32 i) -{ - return 0x00100e30U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_size_r(u32 i) -{ - return 0x00100e34U + i*20U; -} -static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_addr_lo_r(void) -{ - return 0x00100e4cU; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_addr_hi_r(void) -{ - return 0x00100e50U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_inst_lo_r(void) -{ - return 0x00100e54U; -} -static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_inst_hi_r(void) -{ - return 0x00100e58U; -} -static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_info_r(void) -{ - return 0x00100e5cU; -} -static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fb_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_status_r(void) -{ - return 0x00100e60U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) -{ - return 0x1U << 0U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) -{ - return 0x1U << 2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) -{ - return 0x1U << 3U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) -{ - return 0x1U << 4U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) -{ - return 0x1U << 5U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) -{ - return 0x1U << 6U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) -{ - return 0x1U << 7U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_replayable_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fb_mmu_fault_status_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_set_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_fault_status_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_m(void) -{ - return 0x1U << 9U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) -{ - return 0x200U; -} -static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_error_m(void) -{ - return 0x1U << 10U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) -{ - return 0x400U; -} -static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) -{ - return 0x1U << 11U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) -{ - return 0x1U << 12U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) -{ - return 0x1000U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) -{ - return 0x1U << 13U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) -{ - return 0x2000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) -{ - return 0x1U << 14U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) -{ - return 0x4000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) -{ - return 0x1U << 15U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) -{ - return 0x8000U; -} -static inline u32 fb_mmu_fault_status_busy_m(void) -{ - return 0x1U << 30U; -} -static inline u32 fb_mmu_fault_status_busy_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_busy_true_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_status_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 fb_mmu_fault_status_valid_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_status_valid_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_local_memory_range_r(void) -{ - return 0x00100ce0U; -} -static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) -{ - return (r >> 4U) & 0x3fU; -} -static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_niso_scrub_status_r(void) -{ - return 0x00100b20U; -} -static inline u32 fb_niso_scrub_status_flag_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_priv_level_mask_r(void) -{ - return 0x00100cdcU; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) -{ - return 0x1U << 9U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r) -{ - return (r >> 9U) & 0x1U; -} -static inline u32 fb_hshub_config0_r(void) -{ - return 0x001fbc00U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 fb_hshub_config1_r(void) -{ - return 0x001fbc04U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config2_r(void) -{ - return 0x001fbc08U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config6_r(void) -{ - return 0x001fbc18U; -} -static inline u32 fb_hshub_config7_r(void) -{ - return 0x001fbc1cU; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_r(void) -{ - return 0x001fbc50U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_mmu_int_vector_info_fault_r(void) -{ - return 0x00100ee0U; -} -static inline u32 fb_mmu_int_vector_info_fault_vector_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_int_vector_ecc_error_r(void) -{ - return 0x00100edcU; -} -static inline u32 fb_mmu_int_vector_ecc_error_vector_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_int_vector_fault_r(u32 i) -{ - return 0x00100ee4U + i*4U; -} -static inline u32 fb_mmu_int_vector_fault_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_int_vector_fault_notify_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 fb_mmu_num_active_ltcs_r(void) -{ - return 0x00100ec0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_cbc_base_r(void) -{ - return 0x00100ec4U; -} -static inline u32 fb_mmu_cbc_base_address_f(u32 v) -{ - return (v & 0x3ffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_top_r(void) -{ - return 0x00100ec8U; -} -static inline u32 fb_mmu_cbc_top_size_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 fb_mmu_cbc_top_size_v(u32 r) -{ - return (r >> 0U) & 0x7fffU; -} -static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_max_r(void) -{ - return 0x00100eccU; -} -static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_max_comptagline_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fbpa_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fbpa_tu104.h deleted file mode 100644 index 7ffb16fb1..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fbpa_tu104.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fbpa_tu104_h_ -#define _hw_fbpa_tu104_h_ - -static inline u32 fbpa_0_intr_status_r(void) -{ - return 0x00900398U; -} -static inline u32 fbpa_0_intr_status_sec_subp0_pending_f(void) -{ - return 0x1U; -} -static inline u32 fbpa_0_intr_status_ded_subp0_pending_f(void) -{ - return 0x2U; -} -static inline u32 fbpa_0_intr_status_sec_subp1_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fbpa_0_intr_status_ded_subp1_pending_f(void) -{ - return 0x20000U; -} -static inline u32 fbpa_ecc_intr_ctrl_r(void) -{ - return 0x009a0474U; -} -static inline u32 fbpa_ecc_intr_ctrl_sec_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fbpa_ecc_intr_ctrl_ded_intr_en_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fbpa_0_ecc_status_r(u32 i) -{ - return 0x00900478U + i*4U; -} -static inline u32 fbpa_0_ecc_status_sec_intr_pending_f(void) -{ - return 0x2U; -} -static inline u32 fbpa_0_ecc_status_ded_intr_pending_f(void) -{ - return 0x4U; -} -static inline u32 fbpa_0_ecc_status_sec_counter_overflow_pending_f(void) -{ - return 0x20000U; -} -static inline u32 fbpa_0_ecc_status_ded_counter_overflow_pending_f(void) -{ - return 0x40000U; -} -static inline u32 fbpa_0_ecc_sec_count_r(u32 i) -{ - return 0x00900480U + i*4U; -} -static inline u32 fbpa_0_ecc_ded_count_r(u32 i) -{ - return 0x00900488U + i*4U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h deleted file mode 100644 index bb9ec08fb..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h +++ /dev/null @@ -1,495 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_tu104_h_ -#define _hw_fifo_tu104_h_ - -static inline u32 fifo_userd_writeback_r(void) -{ - return 0x0000225cU; -} -static inline u32 fifo_userd_writeback_timer_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_userd_writeback_timer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_userd_writeback_timer_shorter_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_userd_writeback_timer_100us_v(void) -{ - return 0x00000064U; -} -static inline u32 fifo_userd_writeback_timescale_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fifo_userd_writeback_timescale_0_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_runlist_base_lo_r(u32 i) -{ - return 0x00002b00U + i*16U; -} -static inline u32 fifo_runlist_base_lo__size_1_v(void) -{ - return 0x0000000bU; -} -static inline u32 fifo_runlist_base_lo_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_runlist_base_lo_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fifo_runlist_base_lo_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_lo_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fifo_runlist_base_lo_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fifo_runlist_base_hi_r(u32 i) -{ - return 0x00002b04U + i*16U; -} -static inline u32 fifo_runlist_base_hi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_runlist_submit_r(u32 i) -{ - return 0x00002b08U + i*16U; -} -static inline u32 fifo_runlist_submit_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_runlist_submit_info_r(u32 i) -{ - return 0x00002b0cU + i*16U; -} -static inline u32 fifo_runlist_submit_info_pending_true_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390U + i*4U; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_memop_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_memop_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1U << 8U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffffU << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_fb_timeout_period_init_f(void) -{ - return 0x3c00U; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_runlist_preempt_r(void) -{ - return 0x00002638U; -} -static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_m(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640U + i*8U; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x0000000dU; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_eng_reload_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080U + i*4U; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_cfg0_r(void) -{ - return 0x00002004U; -} -static inline u32 fifo_cfg0_num_pbdma_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_flush_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_flush_tu104.h deleted file mode 100644 index 2fb948e18..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_flush_tu104.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_tu104_h_ -#define _hw_flush_tu104_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_func_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_func_tu104.h deleted file mode 100644 index 15eaf0de0..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_func_tu104.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_func_tu104_h_ -#define _hw_func_tu104_h_ - -static inline u32 func_full_phys_offset_v(void) -{ - return 0x00b80000U; -} -static inline u32 func_doorbell_r(void) -{ - return 0x00030090U; -} -static inline u32 func_priv_cpu_intr_top_en_set_r(u32 i) -{ - return 0x00001608U + i*4U; -} -static inline u32 func_priv_cpu_intr_top_en_clear_r(u32 i) -{ - return 0x00001610U + i*4U; -} -static inline u32 func_priv_cpu_intr_top_en_clear__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 func_priv_cpu_intr_leaf_en_set_r(u32 i) -{ - return 0x00001200U + i*4U; -} -static inline u32 func_priv_cpu_intr_leaf_en_clear_r(u32 i) -{ - return 0x00001400U + i*4U; -} -static inline u32 func_priv_cpu_intr_leaf_en_clear__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 func_priv_cpu_intr_top_r(u32 i) -{ - return 0x00001600U + i*4U; -} -static inline u32 func_priv_cpu_intr_leaf_r(u32 i) -{ - return 0x00001000U + i*4U; -} -static inline u32 func_priv_mmu_fault_buffer_lo_r(u32 i) -{ - return 0x00003000U + i*32U; -} -static inline u32 func_priv_mmu_fault_buffer_hi_r(u32 i) -{ - return 0x00003004U + i*32U; -} -static inline u32 func_priv_mmu_fault_buffer_get_r(u32 i) -{ - return 0x00003008U + i*32U; -} -static inline u32 func_priv_mmu_fault_buffer_put_r(u32 i) -{ - return 0x0000300cU + i*32U; -} -static inline u32 func_priv_mmu_fault_buffer_size_r(u32 i) -{ - return 0x00003010U + i*32U; -} -static inline u32 func_priv_mmu_fault_addr_lo_r(void) -{ - return 0x00003080U; -} -static inline u32 func_priv_mmu_fault_addr_hi_r(void) -{ - return 0x00003084U; -} -static inline u32 func_priv_mmu_fault_inst_lo_r(void) -{ - return 0x00003088U; -} -static inline u32 func_priv_mmu_fault_inst_hi_r(void) -{ - return 0x0000308cU; -} -static inline u32 func_priv_mmu_fault_info_r(void) -{ - return 0x00003090U; -} -static inline u32 func_priv_mmu_fault_status_r(void) -{ - return 0x00003094U; -} -static inline u32 func_priv_bar2_block_r(void) -{ - return 0x00000f48U; -} -static inline u32 func_priv_bind_status_r(void) -{ - return 0x00000f50U; -} -static inline u32 func_priv_mmu_invalidate_pdb_r(void) -{ - return 0x000030a0U; -} -static inline u32 func_priv_mmu_invalidate_r(void) -{ - return 0x000030b0U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fuse_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fuse_tu104.h deleted file mode 100644 index 04f9faa26..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fuse_tu104.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_tu104_h_ -#define _hw_fuse_tu104_h_ - -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38U + i*4U; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838U + i*4U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70U + i*4U; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gc6_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gc6_tu104.h deleted file mode 100644 index e13cb1621..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gc6_tu104.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gc6_tu104_h_ -#define _hw_gc6_tu104_h_ - -static inline u32 gc6_aon_secure_scratch_group_05_r(u32 i) -{ - return 0x00118234U + i*4U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gmmu_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gmmu_tu104.h deleted file mode 100644 index c80dceef3..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gmmu_tu104.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_tu104_h_ -#define _hw_gmmu_tu104_h_ - -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0xfffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x00000007U; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_type_unbound_inst_block_v(void) -{ - return 0x00000004U; -} -static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) -{ - return 0x000000c0U; -} -static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) -{ - return 0x0000001fU; -} -static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) -{ - return 0x0000000fU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h deleted file mode 100644 index c4e874aed..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h +++ /dev/null @@ -1,4035 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_tu104_h_ -#define _hw_gr_tu104_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_exception_en_fe_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception_en_gpc_m(void) -{ - return 0x1U << 24U; -} -static inline u32 gr_exception_en_gpc_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 gr_exception_en_memfmt_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_exception_en_memfmt_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_exception_en_ds_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_exception_en_ds_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_exception_en_pd_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_exception_en_pd_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_exception_en_scc_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_exception_en_scc_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_exception_en_ssync_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_exception_en_ssync_enabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_exception_en_mme_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_exception_en_mme_enabled_f(void) -{ - return 0x80U; -} -static inline u32 gr_exception_en_sked_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_exception_en_sked_enabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return 0x7U << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x0050433cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419b3cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_fe_chip_def_info_r(void) -{ - return 0x00404030U; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x00504358U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) -{ - return 0x1U << 9U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) -{ - return 0x1U << 13U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) -{ - return 0x1U << 14U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) -{ - return 0x1U << 15U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 26U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) -{ - return 0x0050435cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) -{ - return 0x00504360U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) -{ - return 0x0050436cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) -{ - return 0x00504370U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) -{ - return 0x00504374U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) -{ - return 0x1U << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) -{ - return 0x0050463cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) -{ - return 0x00504640U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) -{ - return 0x00504430U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) -{ - return 0x00504434U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_address_veid_f(u32 v) -{ - return (v & 0x3fU) << 20U; -} -static inline u32 gr_pipe_bundle_address_veid_w(void) -{ - return 0U; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_data_hi_r(void) -{ - return 0x0040020cU; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x0050472cU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) -{ - return 0x00419eb4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) -{ - return 0x1U << 6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) -{ - return 0x1U << 8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200U + i*4U; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(u32 i) -{ - return 0x0040a200U + i*4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180U + i*16U; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184U + i*16U; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188U + i*16U; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0U + i*8U; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4U + i*8U; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840U + i*4U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1fU << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffffU << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1fU << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map_r(u32 i) -{ - return 0x0040780cU + i*4U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028U + i*4U; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000a80U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000a80U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0U + i*4U; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870U + i*4U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0x3ffU << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_rm_rtv_cb_base_r(void) -{ - return 0x00408070U; -} -static inline u32 gr_scc_rm_rtv_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f(void) -{ - return 0x8U; -} -static inline u32 gr_scc_rm_rtv_cb_size_r(void) -{ - return 0x00408074U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_default_f(void) -{ - return 0x800U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_db_adder_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gcc_rm_rtv_cb_base_r(void) -{ - return 0x00419034U; -} -static inline u32 gr_gpcs_gcc_rm_rtv_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_rm_gfxp_reserve_r(void) -{ - return 0x00408078U; -} -static inline u32 gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802cU; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ssync_hww_esr_r(void) -{ - return 0x00405a14U; -} -static inline u32 gr_ssync_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ssync_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return 0x1U << 25U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60U + i*4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0U + i*4U; -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04U + i*32U; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30U + i*4U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x00504330U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000700U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00000fa8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffffU << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000700U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419e00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419e04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return 0x1fffffU << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfffU << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180U + i*16U; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184U + i*16U; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188U + i*16U; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0U + i*8U; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4U + i*8U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800U + i*4U; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x000004b0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0U + i*4U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0x3fffffU << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return 0x00418010U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return 0x0041804cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return 0x00418088U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return 0x004180c4U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00418100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return 0x00418110U + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0041814cU; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) -{ - return 0x0041815cU + i*4U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) -{ - return 0x00418198U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map_r(u32 i) -{ - return 0x00418b08U + i*4U; -} -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) -{ - return 0x00418980U + i*4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) -{ - return 0x00504728U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void) -{ - return 0x4000000U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) -{ - return 0x1U << 3U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00504710U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504714U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) -{ - return 0x00504718U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x0050471cU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00419e90U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00419e94U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) -{ - return 0x00419e80U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void) -{ - return 0x5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void) -{ - return 0x6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void) -{ - return 0x9U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void) -{ - return 0xbU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void) -{ - return 0xdU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void) -{ - return 0xeU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) -{ - return 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void) -{ - return 0x12U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void) -{ - return 0x16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void) -{ - return 0x17U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void) -{ - return 0x19U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) -{ - return 0xffU << 16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) -{ - return 0xfU << 24U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x005043a0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419ba0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1U << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x005043b0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419bb0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) -{ - return 0x0041bf00U + i*4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) -{ - return 0x0041bfb0U + i*4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) -{ - return 0x00000005U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return 0x1U << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) -{ - return 0x00419a00U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) -{ - return 0x1U << 19U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) -{ - return 0x00419bf0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) -{ - return 0x1U << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) -{ - return 0x1U << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) -{ - return 0x1U << 28U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1U << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1U << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1U << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3U << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3U << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3U << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1U << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1U << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) -{ - return 0x00419e84U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419bd8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return 0x7U << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419ba4U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return 0x3U << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(void) -{ - return 0x1U << 21U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f(void) -{ - return 0x200000U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return 0x1ffU << 0U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrl_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrl_tu104.h deleted file mode 100644 index 5597f6024..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrl_tu104.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ioctrl_tu104_h_ -#define _hw_ioctrl_tu104_h_ - -static inline u32 ioctrl_reset_r(void) -{ - return 0x00000140U; -} -static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void) -{ - return 0x00000008U; -} -static inline u32 ioctrl_reset_linkreset_f(u32 v) -{ - return (v & 0x3U) << 8U; -} -static inline u32 ioctrl_reset_linkreset_m(void) -{ - return 0x3U << 8U; -} -static inline u32 ioctrl_reset_linkreset_v(u32 r) -{ - return (r >> 8U) & 0x3U; -} -static inline u32 ioctrl_debug_reset_r(void) -{ - return 0x00000144U; -} -static inline u32 ioctrl_debug_reset_link_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ioctrl_debug_reset_link_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ioctrl_debug_reset_link_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ioctrl_debug_reset_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_debug_reset_common_m(void) -{ - return 0x1U << 31U; -} -static inline u32 ioctrl_debug_reset_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_clock_control_r(u32 i) -{ - return 0x00000180U + i*4U; -} -static inline u32 ioctrl_clock_control__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 ioctrl_clock_control_clkdis_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_top_intr_0_status_r(void) -{ - return 0x00000200U; -} -static inline u32 ioctrl_top_intr_0_status_link_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_m(void) -{ - return 0x3U << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ioctrl_top_intr_0_status_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_m(void) -{ - return 0x1U << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_r(void) -{ - return 0x00000220U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_r(void) -{ - return 0x00000224U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_r(u32 i) -{ - return 0x00000240U + i*20U; -} -static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_r(u32 i) -{ - return 0x00000244U + i*20U; -} -static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrlmif_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrlmif_tu104.h deleted file mode 100644 index 188566192..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrlmif_tu104.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ioctrlmif_tu104_h_ -#define _hw_ioctrlmif_tu104_h_ - -static inline u32 ioctrlmif_rx_err_contain_en_0_r(void) -{ - return 0x00000e0cU; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f(void) -{ - return 0x10U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_r(void) -{ - return 0x00000e04U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_r(void) -{ - return 0x00000e00U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void) -{ - return 0x1U << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_first_0_r(void) -{ - return 0x00000e14U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_r(void) -{ - return 0x00000a90U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f(void) -{ - return 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f(void) -{ - return 0x2U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_r(void) -{ - return 0x00000a88U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_r(void) -{ - return 0x00000a84U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void) -{ - return 0x1U << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_first_0_r(void) -{ - return 0x00000a98U; -} -static inline u32 ioctrlmif_tx_ctrl_buffer_ready_r(void) -{ - return 0x00000a7cU; -} -static inline u32 ioctrlmif_rx_ctrl_buffer_ready_r(void) -{ - return 0x00000dfcU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ltc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ltc_tu104.h deleted file mode 100644 index 30da7995e..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ltc_tu104.h +++ /dev/null @@ -1,643 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_tu104_h_ -#define _hw_ltc_tu104_h_ - -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1U << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x000fffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_amap_divide_rounding_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_amap_swizzle_rounding_v(u32 r) -{ - return (r >> 12U) & 0x3U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_num_cache_lines_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33cU + i*4U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) -{ - return 0x0017e204U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) -{ - return 8U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1U << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return 0x1U << 21U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1U << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return 0xffU << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return 0xffU << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_mc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_mc_tu104.h deleted file mode 100644 index e6f7f48b2..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_mc_tu104.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_tu104_h_ -#define _hw_mc_tu104_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100U + i*4U; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pfb_pending_f(void) -{ - return 0x2000U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_nvlink_pending_f(void) -{ - return 0x400000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return 0x00000140U + i*4U; -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return 0x00000160U + i*4U; -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return 0x00000180U + i*4U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1U << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1U << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_nvdec_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvdec_enabled_f(void) -{ - return 0x8000U; -} -static inline u32 mc_enable_nvlink_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvlink_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_enable_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_nvlink_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_intr_fbpa_r(void) -{ - return 0x000001d0U; -} -static inline u32 mc_intr_fbpa_part_mask_v(u32 r) -{ - return (r >> 0U) & 0x1ffffU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_minion_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_minion_tu104.h deleted file mode 100644 index 8bb1874a4..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_minion_tu104.h +++ /dev/null @@ -1,935 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_minion_tu104_h_ -#define _hw_minion_tu104_h_ - -static inline u32 minion_minion_status_r(void) -{ - return 0x00000830U; -} -static inline u32 minion_minion_status_status_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_minion_status_status_m(void) -{ - return 0xffU << 0U; -} -static inline u32 minion_minion_status_status_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_minion_status_status_boot_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_status_status_boot_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_status_intr_code_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 minion_minion_status_intr_code_m(void) -{ - return 0xffffffU << 8U; -} -static inline u32 minion_minion_status_intr_code_v(u32 r) -{ - return (r >> 8U) & 0xffffffU; -} -static inline u32 minion_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 minion_falcon_irqstat_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqstat_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 minion_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 minion_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqmset_halt_m(void) -{ - return 0x1U << 4U; -} -static inline u32 minion_falcon_irqmset_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_halt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_halt_set_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_m(void) -{ - return 0x1U << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_exterr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_exterr_set_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_m(void) -{ - return 0x1U << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_m(void) -{ - return 0x1U << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_m(void) -{ - return 0x1U << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_m(void) -{ - return 0x1U << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_m(void) -{ - return 0x1U << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_m(void) -{ - return 0x1U << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_m(void) -{ - return 0x1U << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_m(void) -{ - return 0x1U << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_m(void) -{ - return 0x1U << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_m(void) -{ - return 0x1U << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 minion_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 minion_minion_intr_r(void) -{ - return 0x00000810U; -} -static inline u32 minion_minion_intr_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_fatal_m(void) -{ - return 0x1U << 0U; -} -static inline u32 minion_minion_intr_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_nonfatal_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_minion_intr_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_m(void) -{ - return 0x1U << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_m(void) -{ - return 0x1U << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_link_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 minion_minion_intr_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_minion_intr_nonstall_en_r(void) -{ - return 0x0000081cU; -} -static inline u32 minion_minion_intr_stall_en_r(void) -{ - return 0x00000818U; -} -static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_m(void) -{ - return 0x1U << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_m(void) -{ - return 0x1U << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_f(void) -{ - return 0x2U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void) -{ - return 0x1U << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_f(void) -{ - return 0x4U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void) -{ - return 0x1U << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_f(void) -{ - return 0x8U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_nvlink_dl_cmd_r(u32 i) -{ - return 0x00000900U + i*4U; -} -static inline u32 minion_nvlink_dl_cmd___size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_dl_cmd_command_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_dl_cmd_command_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_v(void) -{ - return 0x00000040U; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_f(void) -{ - return 0x40U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_v(void) -{ - return 0x00000003U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_f(void) -{ - return 0x3U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_v(void) -{ - return 0x00000004U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_f(void) -{ - return 0x4U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_v(void) -{ - return 0x00000008U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_f(void) -{ - return 0x8U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_v(void) -{ - return 0x00000009U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_f(void) -{ - return 0x9U; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_v(void) -{ - return 0x0000000cU; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_f(void) -{ - return 0xcU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_v(void) -{ - return 0x0000000aU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_f(void) -{ - return 0xaU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_v(void) -{ - return 0x0000000bU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_f(void) -{ - return 0xbU; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_v(void) -{ - return 0x00000010U; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_f(void) -{ - return 0x10U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_v(void) -{ - return 0x00000011U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_f(void) -{ - return 0x11U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_v(void) -{ - return 0x00000018U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_f(void) -{ - return 0x18U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_v(void) -{ - return 0x00000019U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_f(void) -{ - return 0x19U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_v(void) -{ - return 0x00000020U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_f(void) -{ - return 0x20U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_v(void) -{ - return 0x00000021U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_f(void) -{ - return 0x21U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_v(void) -{ - return 0x00000022U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_f(void) -{ - return 0x22U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_v(void) -{ - return 0x00000023U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_f(void) -{ - return 0x23U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_v(void) -{ - return 0x00000024U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_f(void) -{ - return 0x24U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_v(void) -{ - return 0x00000025U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_f(void) -{ - return 0x25U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_v(void) -{ - return 0x00000026U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_f(void) -{ - return 0x26U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_v(void) -{ - return 0x00000027U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_f(void) -{ - return 0x27U; -} -static inline u32 minion_nvlink_dl_cmd_command_turing_rxdet_v(void) -{ - return 0x00000058U; -} -static inline u32 minion_nvlink_dl_cmd_command_txclkswitch_pll_v(void) -{ - return 0x00000014U; -} -static inline u32 minion_nvlink_dl_cmd_command_turing_initdlpl_to_chipa_v(void) -{ - return 0x00000060U; -} -static inline u32 minion_nvlink_dl_cmd_command_inittl_v(void) -{ - return 0x00000006U; -} -static inline u32 minion_nvlink_dl_cmd_fault_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_dl_cmd_ready_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 minion_misc_0_r(void) -{ - return 0x000008b0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 minion_nvlink_link_intr_r(u32 i) -{ - return 0x00000a00U + i*4U; -} -static inline u32 minion_nvlink_link_intr___size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_link_intr_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_link_intr_code_m(void) -{ - return 0xffU << 0U; -} -static inline u32 minion_nvlink_link_intr_code_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_code_na_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_link_intr_code_na_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_f(void) -{ - return 0x2U; -} -static inline u32 minion_nvlink_link_intr_subcode_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_m(void) -{ - return 0xffU << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_state_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_link_intr_state_m(void) -{ - return 0x1U << 31U; -} -static inline u32 minion_nvlink_link_intr_state_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvl_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvl_tu104.h deleted file mode 100644 index 90382af45..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvl_tu104.h +++ /dev/null @@ -1,1631 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvl_tu104_h_ -#define _hw_nvl_tu104_h_ - -static inline u32 nvl_link_state_r(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 nvl_link_state_state_m(void) -{ - return 0xffU << 0U; -} -static inline u32 nvl_link_state_state_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 nvl_link_state_state_init_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_init_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_state_state_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_state_state_hwcfg_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_state_state_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_state_state_swcfg_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_state_state_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_state_state_active_f(void) -{ - return 0x3U; -} -static inline u32 nvl_link_state_state_fault_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_link_state_state_fault_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_state_state_rcvy_ac_v(void) -{ - return 0x00000008U; -} -static inline u32 nvl_link_state_state_rcvy_ac_f(void) -{ - return 0x8U; -} -static inline u32 nvl_link_state_state_rcvy_sw_v(void) -{ - return 0x00000009U; -} -static inline u32 nvl_link_state_state_rcvy_sw_f(void) -{ - return 0x9U; -} -static inline u32 nvl_link_state_state_rcvy_rx_v(void) -{ - return 0x0000000aU; -} -static inline u32 nvl_link_state_state_rcvy_rx_f(void) -{ - return 0xaU; -} -static inline u32 nvl_link_state_an0_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvl_link_state_an0_busy_m(void) -{ - return 0x1U << 12U; -} -static inline u32 nvl_link_state_an0_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvl_link_state_tl_busy_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvl_link_state_tl_busy_m(void) -{ - return 0x1U << 13U; -} -static inline u32 nvl_link_state_tl_busy_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvl_link_state_dbg_substate_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 nvl_link_state_dbg_substate_m(void) -{ - return 0xffffU << 16U; -} -static inline u32 nvl_link_state_dbg_substate_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 nvl_link_activity_r(void) -{ - return 0x0000000cU; -} -static inline u32 nvl_link_activity_blkact_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_link_activity_blkact_m(void) -{ - return 0x7U << 0U; -} -static inline u32 nvl_link_activity_blkact_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_r(u32 i) -{ - return 0x00000010U + i*4U; -} -static inline u32 nvl_sublink_activity_blkact0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_m(void) -{ - return 0x7U << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_blkact1_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_m(void) -{ - return 0x7U << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_v(u32 r) -{ - return (r >> 8U) & 0x7U; -} -static inline u32 nvl_link_config_r(void) -{ - return 0x00000018U; -} -static inline u32 nvl_link_config_ac_safe_en_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_config_ac_safe_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_ac_safe_en_on_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_config_link_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_config_link_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 nvl_link_config_link_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_config_link_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_link_en_on_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_link_change_r(void) -{ - return 0x00000040U; -} -static inline u32 nvl_link_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_m(void) -{ - return 0xfU << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_link_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_link_change_newstate_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_link_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_link_change_newstate_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_newstate_hwcfg_f(void) -{ - return 0x10U; -} -static inline u32 nvl_link_change_newstate_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_newstate_swcfg_f(void) -{ - return 0x20U; -} -static inline u32 nvl_link_change_newstate_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_change_newstate_active_f(void) -{ - return 0x30U; -} -static inline u32 nvl_link_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_link_change_action_m(void) -{ - return 0x3U << 2U; -} -static inline u32 nvl_link_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_link_change_action_ltssm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_action_ltssm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_link_change_status_m(void) -{ - return 0x3U << 0U; -} -static inline u32 nvl_link_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_link_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_sublink_change_r(void) -{ - return 0x00000044U; -} -static inline u32 nvl_sublink_change_countdown_f(u32 v) -{ - return (v & 0xfffU) << 20U; -} -static inline u32 nvl_sublink_change_countdown_m(void) -{ - return 0xfffU << 20U; -} -static inline u32 nvl_sublink_change_countdown_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_m(void) -{ - return 0xfU << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_sublink_change_sublink_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 nvl_sublink_change_sublink_m(void) -{ - return 0xfU << 12U; -} -static inline u32 nvl_sublink_change_sublink_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 nvl_sublink_change_sublink_tx_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_sublink_tx_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_sublink_rx_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_sublink_rx_f(void) -{ - return 0x1000U; -} -static inline u32 nvl_sublink_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sublink_change_newstate_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_sublink_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sublink_change_newstate_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_newstate_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_newstate_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sublink_change_newstate_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sublink_change_newstate_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sublink_change_newstate_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sublink_change_newstate_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sublink_change_newstate_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sublink_change_newstate_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sublink_change_newstate_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sublink_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_sublink_change_action_m(void) -{ - return 0x3U << 2U; -} -static inline u32 nvl_sublink_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_sublink_change_action_slsm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_action_slsm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_sublink_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_sublink_change_status_m(void) -{ - return 0x3U << 0U; -} -static inline u32 nvl_sublink_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_sublink_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_sublink_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_sublink_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_test_r(void) -{ - return 0x00000048U; -} -static inline u32 nvl_link_test_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_link_test_mode_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_link_test_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_link_test_mode_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_test_auto_nvhs_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_m(void) -{ - return 0x1U << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_r(void) -{ - return 0x00002024U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_m(void) -{ - return 0xfU << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_stable_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_stable_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_unknown_v(void) -{ - return 0x0000000dU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_unknown_f(void) -{ - return 0xd0U; -} -static inline u32 nvl_sl1_slsm_status_rx_r(void) -{ - return 0x00003014U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_m(void) -{ - return 0xfU << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_stable_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_stable_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void) -{ - return 0xfU << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_unknown_v(void) -{ - return 0x0000000dU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_unknown_f(void) -{ - return 0xd0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_r(void) -{ - return 0x00002008U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void) -{ - return 0x7ffU << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void) -{ - return 0x00000728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void) -{ - return 0x728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v) -{ - return (v & 0x1fU) << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void) -{ - return 0x1fU << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r) -{ - return (r >> 11U) & 0x1fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void) -{ - return 0x7800U; -} -static inline u32 nvl_sl1_error_rate_ctrl_r(void) -{ - return 0x00003284U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void) -{ - return 0x7U << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void) -{ - return 0x7U << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 nvl_sl1_rxslsm_timeout_2_r(void) -{ - return 0x00003034U; -} -static inline u32 nvl_txiobist_configreg_r(void) -{ - return 0x00002e14U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void) -{ - return 0x1U << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvl_txiobist_config_r(void) -{ - return 0x00002e10U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_r(void) -{ - return 0x00000050U; -} -static inline u32 nvl_intr_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_tx_replay_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_intr_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_m(void) -{ - return 0x1U << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_m(void) -{ - return 0x1U << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_m(void) -{ - return 0x1U << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_m(void) -{ - return 0x1U << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_m(void) -{ - return 0x1U << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_m(void) -{ - return 0x1U << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_m(void) -{ - return 0x1U << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_m(void) -{ - return 0x1U << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_m(void) -{ - return 0x1U << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_ltssm_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 nvl_intr_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_m(void) -{ - return 0x1U << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_request_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_intr_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_sw2_r(void) -{ - return 0x00000054U; -} -static inline u32 nvl_intr_minion_r(void) -{ - return 0x00000060U; -} -static inline u32 nvl_intr_minion_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_m(void) -{ - return 0x1U << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_m(void) -{ - return 0x1U << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void) -{ - return 0x1U << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void) -{ - return 0x1U << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void) -{ - return 0x1U << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_m(void) -{ - return 0x1U << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_m(void) -{ - return 0x1U << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_m(void) -{ - return 0x1U << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_m(void) -{ - return 0x1U << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_m(void) -{ - return 0x1U << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_minion_request_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_intr_minion_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_nonstall_en_r(void) -{ - return 0x0000005cU; -} -static inline u32 nvl_intr_stall_en_r(void) -{ - return 0x00000058U; -} -static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void) -{ - return 0x2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void) -{ - return 0x4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void) -{ - return 0x1U << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void) -{ - return 0x10U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void) -{ - return 0x1U << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void) -{ - return 0x20U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void) -{ - return 0x1U << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void) -{ - return 0x100U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void) -{ - return 0x1U << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void) -{ - return 0x10000U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void) -{ - return 0x1U << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void) -{ - return 0x100000U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void) -{ - return 0x1U << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void) -{ - return 0x200000U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void) -{ - return 0x1U << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void) -{ - return 0x400000U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void) -{ - return 0x1U << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void) -{ - return 0x800000U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void) -{ - return 0x1U << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void) -{ - return 0x1000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_m(void) -{ - return 0x1U << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void) -{ - return 0x1U << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 nvl_intr_stall_en_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_m(void) -{ - return 0x1U << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_br0_cfg_cal_r(void) -{ - return 0x0000281cU; -} -static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void) -{ - return 0x1U; -} -static inline u32 nvl_br0_cfg_status_cal_r(void) -{ - return 0x00002838U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_sl0_link_rxdet_status_r(void) -{ - return 0x00002228U; -} -static inline u32 nvl_sl0_link_rxdet_status_sts_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 nvl_sl0_link_rxdet_status_sts_found_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_sl0_link_rxdet_status_sts_timeout_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_clk_status_r(void) -{ - return 0x0000001cU; -} -static inline u32 nvl_clk_status_txclk_sts_v(u32 r) -{ - return (r >> 19U) & 0x1U; -} -static inline u32 nvl_clk_status_txclk_sts_pll_clk_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlinkip_discovery_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlinkip_discovery_tu104.h deleted file mode 100644 index 21e24bedb..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlinkip_discovery_tu104.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvlinkip_discovery_tu104_h_ -#define _hw_nvlinkip_discovery_tu104_h_ - -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlipt_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlipt_tu104.h deleted file mode 100644 index 83c27d5f1..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlipt_tu104.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvlipt_tu104_h_ -#define _hw_nvlipt_tu104_h_ - -static inline u32 nvlipt_intr_control_link0_r(void) -{ - return 0x000004b4U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_r(void) -{ - return 0x00000524U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_v(u32 r) -{ - return (r >> 14U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_v(u32 r) -{ - return (r >> 19U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvlipt_err_uc_mask_link0_r(void) -{ - return 0x00000528U; -} -static inline u32 nvlipt_err_uc_severity_link0_r(void) -{ - return 0x0000052cU; -} -static inline u32 nvlipt_err_uc_first_link0_r(void) -{ - return 0x00000530U; -} -static inline u32 nvlipt_err_uc_advisory_link0_r(void) -{ - return 0x00000534U; -} -static inline u32 nvlipt_err_c_status_link0_r(void) -{ - return 0x00000538U; -} -static inline u32 nvlipt_err_c_mask_link0_r(void) -{ - return 0x0000053cU; -} -static inline u32 nvlipt_err_c_first_link0_r(void) -{ - return 0x00000540U; -} -static inline u32 nvlipt_err_control_link0_r(void) -{ - return 0x00000544U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void) -{ - return 0x1U << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_r(void) -{ - return 0x000004b0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_m(void) -{ - return 0x1U << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_m(void) -{ - return 0x1U << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_scratch_cold_r(void) -{ - return 0x000007d4U; -} -static inline u32 nvlipt_scratch_cold_data_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 nvlipt_scratch_cold_data_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 nvlipt_scratch_cold_data_init_v(void) -{ - return 0xdeadbaadU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvtlc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvtlc_tu104.h deleted file mode 100644 index 63d514894..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvtlc_tu104.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_nvtlc_tu104_h_ -#define _hw_nvtlc_tu104_h_ - -static inline u32 nvtlc_tx_err_report_en_0_r(void) -{ - return 0x00000708U; -} -static inline u32 nvtlc_rx_err_report_en_0_r(void) -{ - return 0x00000f08U; -} -static inline u32 nvtlc_rx_err_report_en_1_r(void) -{ - return 0x00000f20U; -} -static inline u32 nvtlc_tx_err_status_0_r(void) -{ - return 0x00000700U; -} -static inline u32 nvtlc_rx_err_status_0_r(void) -{ - return 0x00000f00U; -} -static inline u32 nvtlc_rx_err_status_1_r(void) -{ - return 0x00000f18U; -} -static inline u32 nvtlc_tx_err_first_0_r(void) -{ - return 0x00000714U; -} -static inline u32 nvtlc_rx_err_first_0_r(void) -{ - return 0x00000f14U; -} -static inline u32 nvtlc_rx_err_first_1_r(void) -{ - return 0x00000f2cU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pbdma_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pbdma_tu104.h deleted file mode 100644 index 5e558bafa..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pbdma_tu104.h +++ /dev/null @@ -1,619 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_tu104_h_ -#define _hw_pbdma_tu104_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048U + i*8192U; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004cU + i*8192U; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050U + i*8192U; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014U + i*8192U; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000U + i*8192U; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054U + i*8192U; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058U + i*8192U; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018U + i*8192U; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001cU + i*8192U; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005cU + i*8192U; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060U + i*8192U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084U + i*8192U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118U + i*8192U; -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return 0x00040110U + i*8192U; -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return 0x00040114U + i*8192U; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094U + i*8192U; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0U + i*8192U; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8U + i*8192U; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0U + i*8192U; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8U + i*8192U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4U + i*8192U; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030U + i*8192U; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100U + i*8192U; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120U + i*8192U; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010U + i*8192U; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008U + i*8192U; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return 0x000400f4U + i*8192U; -} -static inline u32 pbdma_config_l2_evict_first_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_l2_evict_normal_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_config_ce_split_enable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_ce_split_disable_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_config_auth_level_non_privileged_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_config_userd_writeback_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_userd_writeback_enable_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000cU + i*8192U; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4U + i*8192U; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108U + i*8192U; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_eng_reset_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148U + i*8192U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010cU + i*8192U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014cU + i*8192U; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013cU + i*8192U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return 0x00040140U + i*8192U; -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400acU + i*8192U; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_target_eng_ctx_valid_true_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_target_eng_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_ce_ctx_valid_true_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_target_ce_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) -{ - return 0x3000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_true_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_set_channel_info_r(u32 i) -{ - return 0x000400fcU + i*8192U; -} -static inline u32 pbdma_set_channel_info_veid_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return 0x0004012cU + i*8192U; -} -static inline u32 pbdma_timeout_period_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_timeout_period_init_f(void) -{ - return 0x10000U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h deleted file mode 100644 index 1c04a1b6f..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_tu104_h_ -#define _hw_perf_tu104_h_ - -static inline u32 perf_pmmgpc_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmsys_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmgpc_base_v(void) -{ - return 0x00180000U; -} -static inline u32 perf_pmmgpc_extent_v(void) -{ - return 0x00183fffU; -} -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x00240000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x00243fffU; -} -static inline u32 perf_pmmfbp_base_v(void) -{ - return 0x00200000U; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x0024a000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x0024a070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x0024a074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x0024a078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x0024a07cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x0024a084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x0024a088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x0024a0a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmmsys_engine_sel_r(u32 i) -{ - return 0x0024006cU + i*512U; -} -static inline u32 perf_pmmsys_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmfbp_engine_sel_r(u32 i) -{ - return 0x0020006cU + i*512U; -} -static inline u32 perf_pmmfbp_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmgpc_engine_sel_r(u32 i) -{ - return 0x0018006cU + i*512U; -} -static inline u32 perf_pmmgpc_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pnvdec_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pnvdec_tu104.h deleted file mode 100644 index 6f517bf46..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pnvdec_tu104.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pnvdec_tu104_h_ -#define _hw_pnvdec_tu104_h_ - -static inline u32 pnvdec_falcon_irqsset_r(u32 i) -{ - return 0x00830000U + i*16384U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pram_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pram_tu104.h deleted file mode 100644 index acf35482c..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pram_tu104.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_tu104_h_ -#define _hw_pram_tu104_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000U + i*4U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h deleted file mode 100644 index 161d85de9..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_tu104_h_ -#define _hw_pri_ringmaster_tu104_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h deleted file mode 100644 index b3eaf040d..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_gpc_tu104_h_ -#define _hw_pri_ringstation_gpc_tu104_h_ - -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h deleted file mode 100644 index c3bdc5464..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_tu104_h_ -#define _hw_pri_ringstation_sys_tu104_h_ - -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7U << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h deleted file mode 100644 index 21bf1da65..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_tu104_h_ -#define _hw_proj_tu104_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_smpc_base_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_smpc_shared_base_v(void) -{ - return 0x00000300U; -} -static inline u32 proj_smpc_unique_base_v(void) -{ - return 0x00000600U; -} -static inline u32 proj_smpc_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x0000000dU; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x0000000cU; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000010U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_sm_stride_v(void) -{ - return 0x00000080U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_psec_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_psec_tu104.h deleted file mode 100644 index 8e8474f0d..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_psec_tu104.h +++ /dev/null @@ -1,787 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_psec_tu104_h_ -#define _hw_psec_tu104_h_ - -static inline u32 psec_falcon_irqsset_r(void) -{ - return 0x00840000U; -} -static inline u32 psec_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqsclr_r(void) -{ - return 0x00840004U; -} -static inline u32 psec_falcon_irqstat_r(void) -{ - return 0x00840008U; -} -static inline u32 psec_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 psec_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 psec_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqmode_r(void) -{ - return 0x0084000cU; -} -static inline u32 psec_falcon_irqmset_r(void) -{ - return 0x00840010U; -} -static inline u32 psec_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_r(void) -{ - return 0x00840014U; -} -static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqmask_r(void) -{ - return 0x00840018U; -} -static inline u32 psec_falcon_irqdest_r(void) -{ - return 0x0084001cU; -} -static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 psec_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 psec_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 psec_falcon_curctx_r(void) -{ - return 0x00840050U; -} -static inline u32 psec_falcon_nxtctx_r(void) -{ - return 0x00840054U; -} -static inline u32 psec_falcon_mailbox0_r(void) -{ - return 0x00840040U; -} -static inline u32 psec_falcon_mailbox1_r(void) -{ - return 0x00840044U; -} -static inline u32 psec_falcon_itfen_r(void) -{ - return 0x00840048U; -} -static inline u32 psec_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_idlestate_r(void) -{ - return 0x0084004cU; -} -static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 psec_falcon_os_r(void) -{ - return 0x00840080U; -} -static inline u32 psec_falcon_engctl_r(void) -{ - return 0x008400a4U; -} -static inline u32 psec_falcon_cpuctl_r(void) -{ - return 0x00840100U; -} -static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_alias_r(void) -{ - return 0x00840130U; -} -static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_imemc_r(u32 i) -{ - return 0x00840180U + i*16U; -} -static inline u32 psec_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_imemd_r(u32 i) -{ - return 0x00840184U + i*16U; -} -static inline u32 psec_falcon_imemt_r(u32 i) -{ - return 0x00840188U + i*16U; -} -static inline u32 psec_falcon_sctl_r(void) -{ - return 0x00840240U; -} -static inline u32 psec_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 psec_falcon_bootvec_r(void) -{ - return 0x00840104U; -} -static inline u32 psec_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_falcon_dmactl_r(void) -{ - return 0x0084010cU; -} -static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_hwcfg_r(void) -{ - return 0x00840108U; -} -static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 psec_falcon_dmatrfbase_r(void) -{ - return 0x00840110U; -} -static inline u32 psec_falcon_dmatrfbase1_r(void) -{ - return 0x00840128U; -} -static inline u32 psec_falcon_dmatrfmoffs_r(void) -{ - return 0x00840114U; -} -static inline u32 psec_falcon_dmatrfcmd_r(void) -{ - return 0x00840118U; -} -static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 psec_falcon_dmatrffboffs_r(void) -{ - return 0x0084011cU; -} -static inline u32 psec_falcon_exterraddr_r(void) -{ - return 0x00840168U; -} -static inline u32 psec_falcon_exterrstat_r(void) -{ - return 0x0084016cU; -} -static inline u32 psec_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 psec_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 psec_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 psec_sec2_falcon_icd_cmd_r(void) -{ - return 0x00840200U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 psec_sec2_falcon_icd_rdata_r(void) -{ - return 0x0084020cU; -} -static inline u32 psec_falcon_dmemc_r(u32 i) -{ - return 0x008401c0U + i*8U; -} -static inline u32 psec_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 psec_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 psec_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 psec_falcon_dmemd_r(u32 i) -{ - return 0x008401c4U + i*8U; -} -static inline u32 psec_falcon_debug1_r(void) -{ - return 0x00840090U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_m(void) -{ - return 0x1U << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_r(u32 i) -{ - return 0x00840600U + i*4U; -} -static inline u32 psec_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 psec_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 psec_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 psec_falcon_engine_r(void) -{ - return 0x008403c0U; -} -static inline u32 psec_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_r(void) -{ - return 0x00840624U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void) -{ - return 0x80U; -} -static inline u32 psec_hwcfg_r(void) -{ - return 0x00840abcU; -} -static inline u32 psec_hwcfg_emem_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 psec_hwcfg_emem_size_m(void) -{ - return 0x1ffU << 0U; -} -static inline u32 psec_hwcfg_emem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 psec_falcon_hwcfg1_r(void) -{ - return 0x0084012cU; -} -static inline u32 psec_falcon_hwcfg1_dmem_tag_width_f(u32 v) -{ - return (v & 0x1fU) << 21U; -} -static inline u32 psec_falcon_hwcfg1_dmem_tag_width_m(void) -{ - return 0x1fU << 21U; -} -static inline u32 psec_falcon_hwcfg1_dmem_tag_width_v(u32 r) -{ - return (r >> 21U) & 0x1fU; -} -static inline u32 psec_ememc_r(u32 i) -{ - return 0x00840ac0U + i*8U; -} -static inline u32 psec_ememc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 psec_ememc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_ememc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 psec_ememc_blk_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 psec_ememc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_ememc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 psec_ememc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 psec_ememc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_ememc_aincw_m(void) -{ - return 0x1U << 24U; -} -static inline u32 psec_ememc_aincw_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 psec_ememc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 psec_ememc_aincr_m(void) -{ - return 0x1U << 25U; -} -static inline u32 psec_ememc_aincr_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 psec_ememd_r(u32 i) -{ - return 0x00840ac4U + i*8U; -} -static inline u32 psec_ememd__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 psec_ememd_data_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_ememd_data_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 psec_ememd_data_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_msgq_head_r(u32 i) -{ - return 0x00840c80U + i*8U; -} -static inline u32 psec_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_msgq_head_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 psec_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_msgq_tail_r(u32 i) -{ - return 0x00840c84U + i*8U; -} -static inline u32 psec_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_msgq_tail_val_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 psec_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_queue_head_r(u32 i) -{ - return 0x00840c00U + i*8U; -} -static inline u32 psec_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_queue_head_address_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 psec_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_queue_tail_r(u32 i) -{ - return 0x00840c04U + i*8U; -} -static inline u32 psec_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_queue_tail_address_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 psec_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h deleted file mode 100644 index 1134eb70c..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h +++ /dev/null @@ -1,935 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_tu104_h_ -#define _hw_pwr_tu104_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) -{ - return 0x800U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmset_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1U << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1U << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1U << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180U + i*16U; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184U + i*16U; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188U + i*16U; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1U << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1U << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xfU << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0U + i*8U; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3fU << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xffU << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4U + i*8U; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xffU << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580U + i*4U; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a800U + i*4U; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a820U + i*4U; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010be40U + i*4U; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010bf80U + i*4U; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010bfc0U + i*4U; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3U << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0U + i*8U; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4U + i*8U; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30U + i*8U; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0U + i*4U; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450U + i*4U; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0U + i*4U; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8U + i*4U; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710U + i*4U; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760U + i*4U; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00U + i*4U; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1U << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ram_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ram_tu104.h deleted file mode 100644 index 1649c90eb..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ram_tu104.h +++ /dev/null @@ -1,771 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_tu104_h_ -#define _hw_ram_tu104_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1U << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1U << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return 0x1U << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1U << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_engine_wfi_mode_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_engine_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_wfi_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_engine_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_engine_wfi_target_local_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_engine_wfi_veid_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ram_in_engine_wfi_veid_w(void) -{ - return 134U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) -{ - return 136U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) -{ - return 137U; -} -static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) -{ - return (v & 0x3U) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) -{ - return (v & 0x1U) << (2U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) -{ - return (v & 0x1U) << (4U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) -{ - return (v & 0x1U) << (5U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) -{ - return (v & 0x1U) << (10U + i*0U); -} -static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) -{ - return (v & 0x1U) << (11U + i*0U); -} -static inline u32 ram_in_sc_big_page_size__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_big_page_size_64kb_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) -{ - return (v & 0xfffffU) << (12U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) -{ - return (v & 0xffffffffU) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_big_page_size_0_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_sc_big_page_size_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) -{ - return 169U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_sem_addr_hi_w(void) -{ - return 14U; -} -static inline u32 ram_fc_sem_addr_lo_w(void) -{ - return 15U; -} -static inline u32 ram_fc_sem_payload_lo_w(void) -{ - return 16U; -} -static inline u32 ram_fc_sem_payload_hi_w(void) -{ - return 39U; -} -static inline u32 ram_fc_sem_execute_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_set_channel_info_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000010U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ram_rl_entry_type_channel_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_type_tsg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) -{ - return (v & 0x3U) << 6U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_length_init_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_tsg_length_min_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_tsg_length_max_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_therm_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_therm_tu104.h deleted file mode 100644 index 6121992d4..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_therm_tu104.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_tu104_h_ -#define _hw_therm_tu104_h_ - -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200U + i*4U; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3U << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3U << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_m(void) -{ - return 0x1U << 4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1fU << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7U << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xfU << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xfU << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffffU << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160U + i*4U; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3fU << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8U + i*4U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3fU << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3fU << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3fU << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3fU << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3fU << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1U << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0U + i*4U; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1U << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h deleted file mode 100644 index d129c9c72..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_tu104_h_ -#define _hw_timer_tu104_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffffU << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1U << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_top_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_top_tu104.h deleted file mode 100644 index 3c3ef33b9..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_top_tu104.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_tu104_h_ -#define _hw_top_tu104_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbpas_r(void) -{ - return 0x0002243cU; -} -static inline u32 top_num_fbpas_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_num_ces_r(void) -{ - return 0x00022444U; -} -static inline u32 top_num_ces_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700U + i*4U; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_type_enum_ioctrl_v(void) -{ - return 0x00000012U; -} -static inline u32 top_device_info_type_enum_ioctrl_f(void) -{ - return 0x48U; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x7fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h deleted file mode 100644 index 2bc4d8af5..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_trim_tu104_h_ -#define _hw_trim_tu104_h_ - -static inline u32 trim_sys_nvlink_uphy_cfg_r(void) -{ - return 0x00132410U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void) -{ - return 0x3ffU << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void) -{ - return 0x1U << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void) -{ - return 0xffU << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 trim_sys_nvlink0_ctrl_r(void) -{ - return 0x00132420U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void) -{ - return 0x1U << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_nvlink0_status_r(void) -{ - return 0x00132424U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_m(void) -{ - return 0x1U << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_r(void) -{ - return 0x001371c4U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v) -{ - return (v & 0x3U) << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void) -{ - return 0x3U << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f(void) -{ - return 0x30000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void) -{ - return 0x3U << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v(void) -{ - return 0x00000002U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f(void) -{ - return 0x2U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void) -{ - return 0x3U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_usermode_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_usermode_tu104.h deleted file mode 100644 index 596fffabf..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_usermode_tu104.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_usermode_tu104_h_ -#define _hw_usermode_tu104_h_ - -static inline u32 usermode_cfg0_r(void) -{ - return 0x00810000U; -} -static inline u32 usermode_cfg0_class_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 usermode_cfg0_class_id_value_v(void) -{ - return 0x0000c461U; -} -static inline u32 usermode_time_0_r(void) -{ - return 0x00810080U; -} -static inline u32 usermode_time_0_nsec_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 usermode_time_1_r(void) -{ - return 0x00810084U; -} -static inline u32 usermode_time_1_nsec_f(u32 v) -{ - return (v & 0x1fffffffU) << 0U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h deleted file mode 100644 index 193810cfa..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_xp_tu104_h_ -#define _hw_xp_tu104_h_ - -static inline u32 xp_dl_mgr_r(u32 i) -{ - return 0x0008b8c0U + i*4U; -} -static inline u32 xp_dl_mgr_safe_timing_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 xp_pl_link_config_r(u32 i) -{ - return 0x0008c040U + i*4U; -} -static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_m(void) -{ - return 0xfU << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) -{ - return (v & 0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_m(void) -{ - return 0x3U << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) -{ - return 0x00000003U; -} -static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) -{ - return 0x00000002U; -} -static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_m(void) -{ - return 0x7U << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) -{ - return 0x00000007U; -} -static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) -{ - return 0x00000006U; -} -static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) -{ - return 0x00000005U; -} -static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) -{ - return 0x00000004U; -} -static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) -{ - return 0x00000000U; -} -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h deleted file mode 100644 index cc190ff42..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_xve_tu104_h_ -#define _hw_xve_tu104_h_ - -static inline u32 xve_rom_ctrl_r(void) -{ - return 0x00000050U; -} -static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) -{ - return 0x0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) -{ - return 0x1U; -} -static inline u32 xve_link_control_status_r(void) -{ - return 0x00000088U; -} -static inline u32 xve_link_control_status_link_speed_m(void) -{ - return 0xfU << 16U; -} -static inline u32 xve_link_control_status_link_speed_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) -{ - return 0x00000003U; -} -static inline u32 xve_link_control_status_link_width_m(void) -{ - return 0x3fU << 20U; -} -static inline u32 xve_link_control_status_link_width_v(u32 r) -{ - return (r >> 20U) & 0x3fU; -} -static inline u32 xve_link_control_status_link_width_x1_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_width_x2_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_width_x4_v(void) -{ - return 0x00000004U; -} -static inline u32 xve_link_control_status_link_width_x8_v(void) -{ - return 0x00000008U; -} -static inline u32 xve_link_control_status_link_width_x16_v(void) -{ - return 0x00000010U; -} -static inline u32 xve_priv_xv_r(void) -{ - return 0x00000150U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_m(void) -{ - return 0x1U << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_m(void) -{ - return 0x1U << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 xve_cya_2_r(void) -{ - return 0x00000704U; -} -static inline u32 xve_reset_r(void) -{ - return 0x00000718U; -} -static inline u32 xve_reset_reset_m(void) -{ - return 0x1U << 0U; -} -static inline u32 xve_reset_gpu_on_sw_reset_m(void) -{ - return 0x1U << 1U; -} -static inline u32 xve_reset_counter_en_m(void) -{ - return 0x1U << 2U; -} -static inline u32 xve_reset_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_m(void) -{ - return 0x7ffU << 4U; -} -static inline u32 xve_reset_counter_val_v(u32 r) -{ - return (r >> 4U) & 0x7ffU; -} -static inline u32 xve_reset_clock_on_sw_reset_m(void) -{ - return 0x1U << 15U; -} -static inline u32 xve_reset_clock_counter_en_m(void) -{ - return 0x1U << 16U; -} -static inline u32 xve_reset_clock_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_m(void) -{ - return 0x7ffU << 17U; -} -static inline u32 xve_reset_clock_counter_val_v(u32 r) -{ - return (r >> 17U) & 0x7ffU; -} -#endif diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_next.h b/drivers/gpu/nvgpu/nvgpu_gpuid_next.h deleted file mode 100644 index 62021b25b..000000000 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_next.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_GPUID_NEXT_H__ -#define __NVGPU_GPUID_NEXT_H__ - -#define NVGPU_GPUID_NEXT 0x00000164 - -#define NVGPU_GPU_NEXT_FECS_UCODE_SIG "tu104/fecs_sig.bin" -#define NVGPU_GPU_NEXT_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin" - -#define NVGPU_NEXT_INIT_HAL tu104_init_hal -#define NVGPU_NEXT_INIT_OS_OPS nvgpu_tu104_init_os_ops - -struct nvgpu_os_linux; - -extern int tu104_init_hal(struct gk20a *g); -extern void nvgpu_tu104_init_os_ops(struct nvgpu_os_linux *l); - -#endif diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_tu104.c b/drivers/gpu/nvgpu/os/linux/os_ops_tu104.c deleted file mode 100644 index 52d28db2c..000000000 --- a/drivers/gpu/nvgpu/os/linux/os_ops_tu104.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "os/linux/os_linux.h" - -#include "os/linux/debug_therm_gp106.h" -#include "os/linux/debug_clk_gv100.h" - -static struct nvgpu_os_linux_ops tu104_os_linux_ops = { - .therm = { - .init_debugfs = gp106_therm_init_debugfs, - }, - .clk = { - .init_debugfs = gv100_clk_init_debugfs, - }, -}; - -void nvgpu_tu104_init_os_ops(struct nvgpu_os_linux *l) -{ - l->ops.therm = tu104_os_linux_ops.therm; - l->ops.clk = tu104_os_linux_ops.clk; -} diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_tu104.h b/drivers/gpu/nvgpu/os/linux/os_ops_tu104.h deleted file mode 100644 index 60c900f14..000000000 --- a/drivers/gpu/nvgpu/os/linux/os_ops_tu104.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __LINUX_OS_OPS_TU104_H -#define __LINUX_OS_OPS_TU104_H - -void nvgpu_tu104_init_os_ops(struct nvgpu_os_linux *l) - -#endif diff --git a/drivers/gpu/nvgpu/tu104/acr_tu104.c b/drivers/gpu/nvgpu/tu104/acr_tu104.c deleted file mode 100644 index 393dade5c..000000000 --- a/drivers/gpu/nvgpu/tu104/acr_tu104.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "tu104/acr_tu104.h" -#include "gp106/acr_gp106.h" -#include "tu104/sec2_tu104.h" - -void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) -{ - nvgpu_log_fn(g, " "); - - nvgpu_gp106_acr_sw_init(g, acr); - - acr->bootstrap_owner = LSF_FALCON_ID_SEC2; - acr->max_supported_lsfm = MAX_SUPPORTED_LSFM; - - acr->acr.acr_flcn_setup_hw_and_bl_bootstrap = - tu104_sec2_setup_hw_and_bl_bootstrap; -} diff --git a/drivers/gpu/nvgpu/tu104/acr_tu104.h b/drivers/gpu/nvgpu/tu104/acr_tu104.h deleted file mode 100644 index 07cd027b3..000000000 --- a/drivers/gpu/nvgpu/tu104/acr_tu104.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_ACR_TU104_H -#define NVGPU_ACR_TU104_H - -#define TU104_MAX_SUPPORTED_LSFM 4 - -void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); - -#endif /*NVGPU_ACR_TU104_H*/ diff --git a/drivers/gpu/nvgpu/tu104/bios_tu104.c b/drivers/gpu/nvgpu/tu104/bios_tu104.c deleted file mode 100644 index c2b96d5b8..000000000 --- a/drivers/gpu/nvgpu/tu104/bios_tu104.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include "gk20a/gk20a.h" - -#include "tu104/bios_tu104.h" - -#include "nvgpu/hw/tu104/hw_gc6_tu104.h" - -#define NV_DEVINIT_VERIFY_TIMEOUT_MS 1000 -#define NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US 10 - -#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_MASK \ - 0xFF -#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED \ - 0xFF - -int tu104_bios_verify_devinit(struct gk20a *g) -{ - struct nvgpu_timeout timeout; - u32 val; - int err; - - err = nvgpu_timeout_init(g, &timeout, NV_DEVINIT_VERIFY_TIMEOUT_MS, - NVGPU_TIMER_CPU_TIMER); - if (err != 0) { - return err; - } - - do { - val = nvgpu_readl(g, gc6_aon_secure_scratch_group_05_r(0)); - val &= NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_MASK; - - if (val == NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED) { - nvgpu_log_info(g, "devinit complete"); - return 0; - } - - nvgpu_udelay(NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US); - } while (!nvgpu_timeout_expired(&timeout)); - - return -ETIMEDOUT; -} diff --git a/drivers/gpu/nvgpu/tu104/bios_tu104.h b/drivers/gpu/nvgpu/tu104/bios_tu104.h deleted file mode 100644 index 666f74de1..000000000 --- a/drivers/gpu/nvgpu/tu104/bios_tu104.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __BIOS_TU104_H__ -#define __BIOS_TU104_H__ - -struct gk20a; - -int tu104_bios_verify_devinit(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/tu104/ecc_tu104.c b/drivers/gpu/nvgpu/tu104/ecc_tu104.c deleted file mode 100644 index 4d8345daa..000000000 --- a/drivers/gpu/nvgpu/tu104/ecc_tu104.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "gk20a/gk20a.h" -#include "gv11b/ecc_gv11b.h" -#include "tu104/ecc_tu104.h" - -int tu104_ecc_init(struct gk20a *g) -{ - int err; - - err = gv11b_ecc_init(g); - if (err != 0) { - return err; - } - - err = NVGPU_ECC_COUNTER_INIT_PER_FBPA(fbpa_ecc_sec_err_count); - if (err != 0) { - goto done; - } - err = NVGPU_ECC_COUNTER_INIT_PER_FBPA(fbpa_ecc_ded_err_count); - if (err != 0) { - goto done; - } - -done: - if (err != 0) { - nvgpu_err(g, "ecc counter allocate failed, err=%d", err); - nvgpu_ecc_free(g); - } - - return err; -} diff --git a/drivers/gpu/nvgpu/tu104/ecc_tu104.h b/drivers/gpu/nvgpu/tu104/ecc_tu104.h deleted file mode 100644 index fb2f3998c..000000000 --- a/drivers/gpu/nvgpu/tu104/ecc_tu104.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __ECC_TU104_H__ -#define __ECC_TU104_H__ - -int tu104_ecc_init(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/tu104/fbpa_tu104.c b/drivers/gpu/nvgpu/tu104/fbpa_tu104.c deleted file mode 100644 index 4373818ed..000000000 --- a/drivers/gpu/nvgpu/tu104/fbpa_tu104.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * TU104 FBPA - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include "gk20a/gk20a.h" -#include "tu104/fbpa_tu104.h" - -int tu104_fbpa_init(struct gk20a *g) -{ - u32 val; - - val = gk20a_readl(g, fbpa_ecc_intr_ctrl_r()); - val |= fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f() | - fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f(); - gk20a_writel(g, fbpa_ecc_intr_ctrl_r(), val); - /* read back broadcast register */ - (void) gk20a_readl(g, fbpa_ecc_intr_ctrl_r()); - - return 0; -} - -static void tu104_fbpa_handle_ecc_intr(struct gk20a *g, - u32 fbpa_id, u32 subp_id) -{ - u32 status, sec_cnt, ded_cnt; - u32 offset = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) * fbpa_id; - u32 cnt_idx = fbpa_id * 2 + subp_id; - - status = gk20a_readl(g, offset + fbpa_0_ecc_status_r(subp_id)); - - if (status & fbpa_0_ecc_status_sec_counter_overflow_pending_f()) { - nvgpu_err(g, "fbpa %u subp %u ecc sec counter overflow", - fbpa_id, subp_id); - } - - if (status & fbpa_0_ecc_status_ded_counter_overflow_pending_f()) { - nvgpu_err(g, "fbpa %u subp %u ecc ded counter overflow", - fbpa_id, subp_id); - } - - if (status & fbpa_0_ecc_status_sec_intr_pending_f()) { - sec_cnt = gk20a_readl(g, - offset + fbpa_0_ecc_sec_count_r(subp_id)); - gk20a_writel(g, offset + fbpa_0_ecc_sec_count_r(subp_id), 0u); - g->ecc.fbpa.fbpa_ecc_sec_err_count[cnt_idx].counter += sec_cnt; - } - - if (status & fbpa_0_ecc_status_ded_intr_pending_f()) { - ded_cnt = gk20a_readl(g, - offset + fbpa_0_ecc_ded_count_r(subp_id)); - gk20a_writel(g, offset + fbpa_0_ecc_ded_count_r(subp_id), 0u); - g->ecc.fbpa.fbpa_ecc_ded_err_count[cnt_idx].counter += ded_cnt; - } - - gk20a_writel(g, offset + fbpa_0_ecc_status_r(subp_id), status); -} - -void tu104_fbpa_handle_intr(struct gk20a *g, u32 fbpa_id) -{ - u32 offset, status; - u32 ecc_subp0_mask = fbpa_0_intr_status_sec_subp0_pending_f() | - fbpa_0_intr_status_ded_subp0_pending_f(); - u32 ecc_subp1_mask = fbpa_0_intr_status_sec_subp1_pending_f() | - fbpa_0_intr_status_ded_subp1_pending_f(); - - offset = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) * fbpa_id; - - status = gk20a_readl(g, offset + fbpa_0_intr_status_r()); - if (!(status & (ecc_subp0_mask | ecc_subp1_mask))) { - nvgpu_err(g, "unknown interrupt fbpa %u status %08x", - fbpa_id, status); - return; - } - - if (status & ecc_subp0_mask) { - tu104_fbpa_handle_ecc_intr(g, fbpa_id, 0u); - } - if (status & ecc_subp1_mask) { - tu104_fbpa_handle_ecc_intr(g, fbpa_id, 1u); - } -} diff --git a/drivers/gpu/nvgpu/tu104/fbpa_tu104.h b/drivers/gpu/nvgpu/tu104/fbpa_tu104.h deleted file mode 100644 index c1ec2ae7c..000000000 --- a/drivers/gpu/nvgpu/tu104/fbpa_tu104.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * TU104 FBPA - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _NVGPU_TU104_FBPA -#define _NVGPU_TU104_FBPA - -struct gk20a; - -int tu104_fbpa_init(struct gk20a *g); -void tu104_fbpa_handle_intr(struct gk20a *g, u32 fbpa_id); - -#endif diff --git a/drivers/gpu/nvgpu/tu104/fifo_tu104.c b/drivers/gpu/nvgpu/tu104/fifo_tu104.c deleted file mode 100644 index 75f832faf..000000000 --- a/drivers/gpu/nvgpu/tu104/fifo_tu104.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "gk20a/gk20a.h" -#include "gk20a/fifo_gk20a.h" - -#include "gp10b/fifo_gp10b.h" - -#include "gv11b/fifo_gv11b.h" - -#include "tu104/fifo_tu104.h" -#include "tu104/func_tu104.h" - -#include -#include -#include -#include -#include - -int channel_tu104_setup_ramfc(struct channel_gk20a *c, - u64 gpfifo_base, u32 gpfifo_entries, - unsigned long acquire_timeout, u32 flags) -{ - struct gk20a *g = c->g; - struct nvgpu_mem *mem = &c->inst_block; - u32 data; - - nvgpu_log_fn(g, " "); - - nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); - - nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(), - pbdma_gp_base_offset_f( - u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); - - nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), - pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | - pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); - - nvgpu_mem_wr32(g, mem, ram_fc_signature_w(), - c->g->ops.fifo.get_pbdma_signature(c->g)); - - nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(), - pbdma_pb_header_method_zero_f() | - pbdma_pb_header_subchannel_zero_f() | - pbdma_pb_header_level_main_f() | - pbdma_pb_header_first_true_f() | - pbdma_pb_header_type_inc_f()); - - nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(), - pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) | - pbdma_subdevice_status_active_f() | - pbdma_subdevice_channel_dma_enable_f()); - - nvgpu_mem_wr32(g, mem, ram_fc_target_w(), - pbdma_target_eng_ctx_valid_true_f() | - pbdma_target_ce_ctx_valid_true_f() | - pbdma_target_engine_sw_f()); - - nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), - g->ops.fifo.pbdma_acquire_val(acquire_timeout)); - - nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), - pbdma_set_channel_info_veid_f(c->subctx_id)); - - nvgpu_mem_wr32(g, mem, ram_in_engine_wfi_veid_w(), - ram_in_engine_wfi_veid_f(c->subctx_id)); - - gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); - - if (c->is_privileged_channel) { - /* Set privilege level for channel */ - nvgpu_mem_wr32(g, mem, ram_fc_config_w(), - pbdma_config_auth_level_privileged_f()); - - gk20a_fifo_setup_ramfc_for_privileged_channel(c); - } - - /* Enable userd writeback */ - data = nvgpu_mem_rd32(g, mem, ram_fc_config_w()); - data = data | pbdma_config_userd_writeback_enable_f(); - nvgpu_mem_wr32(g, mem, ram_fc_config_w(),data); - - gv11b_userd_writeback_config(g); - - return channel_gp10b_commit_userd(c); -} - -void tu104_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id, - u32 count, u32 buffer_index) -{ - struct fifo_runlist_info_gk20a *runlist = NULL; - u64 runlist_iova; - u32 runlist_iova_lo, runlist_iova_hi; - - runlist = &g->fifo.runlist_info[runlist_id]; - runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]); - - runlist_iova_lo = u64_lo32(runlist_iova) >> - fifo_runlist_base_lo_ptr_align_shift_v(); - runlist_iova_hi = u64_hi32(runlist_iova); - - if (count != 0) { - nvgpu_writel(g, fifo_runlist_base_lo_r(runlist_id), - fifo_runlist_base_lo_ptr_lo_f(runlist_iova_lo) | - nvgpu_aperture_mask(g, &runlist->mem[buffer_index], - fifo_runlist_base_lo_target_sys_mem_ncoh_f(), - fifo_runlist_base_lo_target_sys_mem_coh_f(), - fifo_runlist_base_lo_target_vid_mem_f())); - - nvgpu_writel(g, fifo_runlist_base_hi_r(runlist_id), - fifo_runlist_base_hi_ptr_hi_f(runlist_iova_hi)); - } - - nvgpu_writel(g, fifo_runlist_submit_r(runlist_id), - fifo_runlist_submit_length_f(count)); -} - -int tu104_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id) -{ - struct nvgpu_timeout timeout; - unsigned long delay = GR_IDLE_CHECK_DEFAULT; - int ret = -ETIMEDOUT; - - ret = nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), - NVGPU_TIMER_CPU_TIMER); - if (ret != 0) { - return ret; - } - - ret = -ETIMEDOUT; - do { - if ((nvgpu_readl(g, fifo_runlist_submit_info_r(runlist_id)) & - fifo_runlist_submit_info_pending_true_f()) == 0) { - ret = 0; - break; - } - - nvgpu_usleep_range(delay, delay * 2); - delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); - } while (!nvgpu_timeout_expired(&timeout)); - - return ret; -} - -int tu104_init_fifo_setup_hw(struct gk20a *g) -{ - u32 val; - - nvgpu_log_fn(g, " "); - - /* - * Required settings for tu104_ring_channel_doorbell() - */ - val = nvgpu_readl(g, ctrl_virtual_channel_cfg_r(0)); - val |= ctrl_virtual_channel_cfg_pending_enable_true_f(); - nvgpu_writel(g, ctrl_virtual_channel_cfg_r(0), val); - - return gv11b_init_fifo_setup_hw(g); -} - -void tu104_ring_channel_doorbell(struct channel_gk20a *c) -{ - struct fifo_gk20a *f = &c->g->fifo; - u32 hw_chid = f->channel_base + c->chid; - - nvgpu_log_info(c->g, "channel ring door bell %d, runlist %d", - c->chid, c->runlist_id); - - nvgpu_func_writel(c->g, func_doorbell_r(), - ctrl_doorbell_vector_f(hw_chid) | - ctrl_doorbell_runlist_id_f(c->runlist_id)); -} - -int tu104_init_pdb_cache_war(struct gk20a *g) -{ - u32 size = PAGE_SIZE * 258U; - u64 last_bind_pdb_addr; - u64 pdb_addr; - u32 pdb_addr_lo, pdb_addr_hi; - u32 i; - int err; - - if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) { - return 0; - } - - /* - * Allocate memory for 257 instance block binds + - * PDB bound to 257th instance block - */ - err = nvgpu_dma_alloc_sys(g, size, &g->pdb_cache_war_mem); - if (err) { - return err; - } - - /* - * 257th instance block (i.e. last bind) needs to be bound to - * valid memory - * First 256 binds can happen to dummy addresses - */ - pdb_addr = PAGE_SIZE; - last_bind_pdb_addr = nvgpu_mem_get_addr(g, &g->pdb_cache_war_mem) + - (257U * PAGE_SIZE); - - /* Setup first 256 instance blocks */ - for (i = 0U; i < 256U; i++) { - pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); - pdb_addr_hi = u64_hi32(pdb_addr); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_lo_w() + (i * PAGE_SIZE / 4), - nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_target_sys_mem_ncoh_f(), - ram_in_page_dir_base_target_sys_mem_coh_f(), - ram_in_page_dir_base_target_vid_mem_f()) | - ram_in_page_dir_base_vol_true_f() | - ram_in_big_page_size_64kb_f() | - ram_in_page_dir_base_lo_f(pdb_addr_lo) | - ram_in_use_ver2_pt_format_true_f()); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_hi_w() + (i * PAGE_SIZE / 4), - ram_in_page_dir_base_hi_f(pdb_addr_hi)); - - pdb_addr += PAGE_SIZE; - } - - /* Setup 257th instance block */ - pdb_addr_lo = u64_lo32(last_bind_pdb_addr >> ram_in_base_shift_v()); - pdb_addr_hi = u64_hi32(last_bind_pdb_addr); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_lo_w() + (256U * PAGE_SIZE / 4), - nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_target_sys_mem_ncoh_f(), - ram_in_page_dir_base_target_sys_mem_coh_f(), - ram_in_page_dir_base_target_vid_mem_f()) | - ram_in_page_dir_base_vol_true_f() | - ram_in_big_page_size_64kb_f() | - ram_in_page_dir_base_lo_f(pdb_addr_lo) | - ram_in_use_ver2_pt_format_true_f()); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_hi_w() + (256U * PAGE_SIZE / 4), - ram_in_page_dir_base_hi_f(pdb_addr_hi)); - - return 0; -} - -void tu104_deinit_pdb_cache_war(struct gk20a *g) -{ - if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) { - nvgpu_dma_free(g, &g->pdb_cache_war_mem); - } -} diff --git a/drivers/gpu/nvgpu/tu104/fifo_tu104.h b/drivers/gpu/nvgpu/tu104/fifo_tu104.h deleted file mode 100644 index 601a8d535..000000000 --- a/drivers/gpu/nvgpu/tu104/fifo_tu104.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __FIFO_TU104_H__ -#define __FIFO_TU104_H__ - -#include - -struct gk20a; -struct channel_gk20a; - -int channel_tu104_setup_ramfc(struct channel_gk20a *c, - u64 gpfifo_base, u32 gpfifo_entries, - unsigned long acquire_timeout, u32 flags); -void tu104_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id, - u32 count, u32 buffer_index); -int tu104_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id); -int tu104_init_fifo_setup_hw(struct gk20a *g); -void tu104_ring_channel_doorbell(struct channel_gk20a *c); - -int tu104_init_pdb_cache_war(struct gk20a *g); -void tu104_deinit_pdb_cache_war(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/tu104/flcn_tu104.c b/drivers/gpu/nvgpu/tu104/flcn_tu104.c deleted file mode 100644 index 089fb2a8b..000000000 --- a/drivers/gpu/nvgpu/tu104/flcn_tu104.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#include - -#include "gk20a/gk20a.h" -#include "gk20a/flcn_gk20a.h" -#include "gv100/flcn_gv100.h" -#include "tu104/flcn_tu104.h" -#include "tu104/sec2_tu104.h" - -#include -#include - -static void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) -{ - struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = - &flcn->flcn_engine_dep_ops; - - switch (flcn->flcn_id) { - case FALCON_ID_SEC2: - flcn_eng_dep_ops->reset_eng = tu104_sec2_reset; - flcn_eng_dep_ops->copy_to_emem = tu104_sec2_flcn_copy_to_emem; - flcn_eng_dep_ops->copy_from_emem = tu104_sec2_flcn_copy_from_emem; - flcn_eng_dep_ops->queue_head = tu104_sec2_queue_head; - flcn_eng_dep_ops->queue_tail = tu104_sec2_queue_tail; - break; - default: - flcn_eng_dep_ops->reset_eng = NULL; - break; - } -} - -static void tu104_falcon_ops(struct nvgpu_falcon *flcn) -{ - gk20a_falcon_ops(flcn); - tu104_falcon_engine_dependency_ops(flcn); -} - -int tu104_falcon_hal_sw_init(struct nvgpu_falcon *flcn) -{ - struct gk20a *g = flcn->g; - int err = 0; - - switch (flcn->flcn_id) { - case FALCON_ID_SEC2: - flcn->flcn_base = psec_falcon_irqsset_r(); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = true; - break; - case FALCON_ID_NVDEC: - flcn->flcn_base = pnvdec_falcon_irqsset_r(0); - flcn->is_falcon_supported = true; - flcn->is_interrupt_enabled = true; - break; - default: - /* - * set false to inherit falcon support - * from previous chips HAL - */ - flcn->is_falcon_supported = false; - break; - } - - if (flcn->is_falcon_supported) { - err = nvgpu_mutex_init(&flcn->copy_lock); - if (err != 0) { - nvgpu_err(g, "Error in flcn.copy_lock mutex initialization"); - } else { - tu104_falcon_ops(flcn); - } - } else { - /* - * Forward call to previous chips HAL - * to fetch info for requested - * falcon as no changes between - * current & previous chips. - */ - err = gv100_falcon_hal_sw_init(flcn); - } - - return err; -} diff --git a/drivers/gpu/nvgpu/tu104/flcn_tu104.h b/drivers/gpu/nvgpu/tu104/flcn_tu104.h deleted file mode 100644 index b8f1bf031..000000000 --- a/drivers/gpu/nvgpu/tu104/flcn_tu104.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __FLCN_TU104_H__ -#define __FLCN_TU104_H__ - -int tu104_falcon_hal_sw_init(struct nvgpu_falcon *flcn); - -#endif /* __FLCN_TU104_H__ */ diff --git a/drivers/gpu/nvgpu/tu104/func_tu104.c b/drivers/gpu/nvgpu/tu104/func_tu104.c deleted file mode 100644 index 41879c83c..000000000 --- a/drivers/gpu/nvgpu/tu104/func_tu104.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include "gk20a/gk20a.h" -#include "tu104/func_tu104.h" - -#include - -void nvgpu_func_writel(struct gk20a *g, u32 r, u32 v) -{ - nvgpu_writel(g, r + func_full_phys_offset_v(), v); -} - -u32 nvgpu_func_readl(struct gk20a *g, u32 r) -{ - return nvgpu_readl(g, r + func_full_phys_offset_v()); -} diff --git a/drivers/gpu/nvgpu/tu104/func_tu104.h b/drivers/gpu/nvgpu/tu104/func_tu104.h deleted file mode 100644 index 195c93819..000000000 --- a/drivers/gpu/nvgpu/tu104/func_tu104.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef FUNC_TU104_H -#define FUNC_TU104_H - -#include - -struct gk20a; - -void nvgpu_func_writel(struct gk20a *g, u32 r, u32 v); -u32 nvgpu_func_readl(struct gk20a *g, u32 r); - -#endif diff --git a/drivers/gpu/nvgpu/tu104/gr_ctx_tu104.c b/drivers/gpu/nvgpu/tu104/gr_ctx_tu104.c deleted file mode 100644 index 6fb817d86..000000000 --- a/drivers/gpu/nvgpu/tu104/gr_ctx_tu104.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * TU104 Graphics Context - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" -#include "gr_ctx_tu104.h" -#include "nvgpu_gpuid_next.h" - -int gr_tu104_get_netlist_name(struct gk20a *g, int index, char *name) -{ - u32 ver = g->params.gpu_arch + g->params.gpu_impl; - - switch (ver) { - case NVGPU_GPUID_NEXT: - sprintf(name, "%s/%s", "tu104", "NETC_img.bin"); - break; - default: - nvgpu_err(g, "no support for GPUID %x", ver); - } - - return 0; -} - -bool gr_tu104_is_firmware_defined(void) -{ - return true; -} diff --git a/drivers/gpu/nvgpu/tu104/gr_ctx_tu104.h b/drivers/gpu/nvgpu/tu104/gr_ctx_tu104.h deleted file mode 100644 index 662edafbd..000000000 --- a/drivers/gpu/nvgpu/tu104/gr_ctx_tu104.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __GR_CTX_TU104_H__ -#define __GR_CTX_TU104_H__ - -int gr_tu104_get_netlist_name(struct gk20a *g, int index, char *name); -bool gr_tu104_is_firmware_defined(void); - -#endif /*__GR_CTX_TU104_H__*/ diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.c b/drivers/gpu/nvgpu/tu104/gr_tu104.c deleted file mode 100644 index e7a33de7b..000000000 --- a/drivers/gpu/nvgpu/tu104/gr_tu104.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -#include "gk20a/gk20a.h" -#include "gk20a/gr_gk20a.h" -#include "gk20a/gr_ctx_gk20a.h" -#include "gk20a/gr_pri_gk20a.h" - -#include "gp10b/gr_gp10b.h" - -#include "gv11b/gr_gv11b.h" - -#include "tu104/gr_tu104.h" - -#include - -bool gr_tu104_is_valid_class(struct gk20a *g, u32 class_num) -{ - switch (class_num) { - case TURING_CHANNEL_GPFIFO_A: - case TURING_A: - case TURING_COMPUTE_A: - case TURING_DMA_COPY_A: - return true; - default: - break; - } - - return gr_gv11b_is_valid_class(g, class_num); -}; - -bool gr_tu104_is_valid_gfx_class(struct gk20a *g, u32 class_num) -{ - switch (class_num) { - case TURING_A: - return true; - default: - break; - } - - return gr_gv11b_is_valid_gfx_class(g, class_num); -} - -bool gr_tu104_is_valid_compute_class(struct gk20a *g, u32 class_num) -{ - switch (class_num) { - case TURING_COMPUTE_A: - return true; - default: - break; - } - - return gr_gv11b_is_valid_compute_class(g, class_num); -} - -int gr_tu104_init_sw_bundle64(struct gk20a *g) -{ - u32 i; - u32 last_bundle_data_lo = 0; - u32 last_bundle_data_hi = 0; - u32 err = 0; - struct av64_list_gk20a *sw_bundle64_init = - &g->gr.ctx_vars.sw_bundle64_init; - - for (i = 0; i < sw_bundle64_init->count; i++) { - if (i == 0 || - (last_bundle_data_lo != sw_bundle64_init->l[i].value_lo) || - (last_bundle_data_hi != sw_bundle64_init->l[i].value_hi)) { - nvgpu_writel(g, gr_pipe_bundle_data_r(), - sw_bundle64_init->l[i].value_lo); - nvgpu_writel(g, gr_pipe_bundle_data_hi_r(), - sw_bundle64_init->l[i].value_hi); - - last_bundle_data_lo = sw_bundle64_init->l[i].value_lo; - last_bundle_data_hi = sw_bundle64_init->l[i].value_hi; - } - - nvgpu_writel(g, gr_pipe_bundle_address_r(), - sw_bundle64_init->l[i].addr); - - if (gr_pipe_bundle_address_value_v(sw_bundle64_init->l[i].addr) - == GR_GO_IDLE_BUNDLE) { - err |= gr_gk20a_wait_idle(g, - gk20a_get_gr_idle_timeout(g), - GR_IDLE_CHECK_DEFAULT); - } else if (nvgpu_platform_is_silicon(g)) { - err |= gr_gk20a_wait_fe_idle(g, - gk20a_get_gr_idle_timeout(g), - GR_IDLE_CHECK_DEFAULT); - } - } - - return err; -} - -int gr_tu104_alloc_global_ctx_buffers(struct gk20a *g) -{ - int err; - struct gr_gk20a *gr = &g->gr; - u32 rtv_circular_buffer_size; - - nvgpu_log_fn(g, " "); - - rtv_circular_buffer_size = - (gr_scc_rm_rtv_cb_size_div_256b_default_f() + - gr_scc_rm_rtv_cb_size_div_256b_db_adder_f()) * - gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); - nvgpu_log_info(g, "rtv_circular_buffer_size : %u", - rtv_circular_buffer_size); - - err = gk20a_gr_alloc_ctx_buffer(g, - &gr->global_ctx_buffer[RTV_CIRCULAR_BUFFER], - rtv_circular_buffer_size); - if (err) { - return err; - } - - err = gr_gk20a_alloc_global_ctx_buffers(g); - if (err) { - goto clean_up; - } - - return 0; - -clean_up: - nvgpu_err(g, "fail"); - gk20a_gr_destroy_ctx_buffer(g, - &gr->global_ctx_buffer[RTV_CIRCULAR_BUFFER]); - - return err; -} - -int gr_tu104_map_global_ctx_buffers(struct gk20a *g, - struct channel_gk20a *ch) -{ - int err; - struct tsg_gk20a *tsg; - struct vm_gk20a *ch_vm = ch->vm; - u64 *g_bfr_va; - u64 *g_bfr_size; - int *g_bfr_index; - struct gr_gk20a *gr = &g->gr; - struct nvgpu_mem *mem; - u64 gpu_va; - - nvgpu_log_fn(g, " "); - - tsg = tsg_gk20a_from_ch(ch); - if (!tsg) { - return -EINVAL; - } - - g_bfr_va = tsg->gr_ctx.global_ctx_buffer_va; - g_bfr_size = tsg->gr_ctx.global_ctx_buffer_size; - g_bfr_index = tsg->gr_ctx.global_ctx_buffer_index; - - /* RTV circular buffer */ - mem = &gr->global_ctx_buffer[RTV_CIRCULAR_BUFFER].mem; - gpu_va = nvgpu_gmmu_map(ch_vm, mem, mem->size, 0, - gk20a_mem_flag_none, true, mem->aperture); - if (!gpu_va) { - return -ENOMEM; - } - - g_bfr_va[RTV_CIRCULAR_BUFFER_VA] = gpu_va; - g_bfr_size[RTV_CIRCULAR_BUFFER_VA] = mem->size; - g_bfr_index[RTV_CIRCULAR_BUFFER_VA] = RTV_CIRCULAR_BUFFER; - - err = gr_gk20a_map_global_ctx_buffers(g, ch); - if (err) { - goto clean_up; - } - - return 0; - -clean_up: - nvgpu_err(g, "fail"); - nvgpu_gmmu_unmap(ch_vm, mem, gpu_va); - - return err; -} - -static void gr_tu104_commit_rtv_circular_buffer(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - u64 addr, u32 size, bool patch) -{ - gr_gk20a_ctx_patch_write(g, gr_ctx, gr_scc_rm_rtv_cb_base_r(), - gr_scc_rm_rtv_cb_base_addr_39_8_f(addr), patch); - gr_gk20a_ctx_patch_write(g, gr_ctx, gr_scc_rm_rtv_cb_size_r(), - gr_scc_rm_rtv_cb_size_div_256b_f(size), patch); - gr_gk20a_ctx_patch_write(g, gr_ctx, gr_gpcs_gcc_rm_rtv_cb_base_r(), - gr_gpcs_gcc_rm_rtv_cb_base_addr_39_8_f(addr), patch); - gr_gk20a_ctx_patch_write(g, gr_ctx, gr_scc_rm_gfxp_reserve_r(), - gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(0), patch); -} - -int gr_tu104_commit_global_ctx_buffers(struct gk20a *g, - struct channel_gk20a *ch, bool patch) -{ - int err; - struct tsg_gk20a *tsg; - struct nvgpu_gr_ctx *gr_ctx = NULL; - u64 addr; - u32 size; - - err = gr_gk20a_commit_global_ctx_buffers(g, ch, patch); - if (err) { - return err; - } - - tsg = tsg_gk20a_from_ch(ch); - if (!tsg) { - return -EINVAL; - } - - gr_ctx = &tsg->gr_ctx; - if (patch) { - int err; - err = gr_gk20a_ctx_patch_write_begin(g, gr_ctx, false); - if (err) { - return err; - } - } - - /* RTV circular buffer */ - addr = (u64_lo32(gr_ctx->global_ctx_buffer_va[RTV_CIRCULAR_BUFFER_VA]) >> - gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f()) | - (u64_hi32(gr_ctx->global_ctx_buffer_va[RTV_CIRCULAR_BUFFER_VA]) << - (32 - gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f())); - - size = (gr_scc_rm_rtv_cb_size_div_256b_default_f() + - gr_scc_rm_rtv_cb_size_div_256b_db_adder_f()); - - gr_tu104_commit_rtv_circular_buffer(g, gr_ctx, addr, size, patch); - - if (patch) { - gr_gk20a_ctx_patch_write_end(g, gr_ctx, false); - } - - return 0; -} - -void gr_tu104_bundle_cb_defaults(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - - gr->bundle_cb_default_size = - gr_scc_bundle_cb_size_div_256b__prod_v(); - gr->min_gpm_fifo_depth = - gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(); - gr->bundle_cb_token_limit = - gr_pd_ab_dist_cfg2_token_limit_init_v(); -} - -void gr_tu104_cb_size_default(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - - if (!gr->attrib_cb_default_size) { - gr->attrib_cb_default_size = - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); - } - gr->alpha_cb_default_size = - gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); -} - -int gr_tu104_get_preemption_mode_flags(struct gk20a *g, - struct nvgpu_preemption_modes_rec *preemption_modes_rec) -{ - preemption_modes_rec->graphics_preemption_mode_flags = ( - NVGPU_PREEMPTION_MODE_GRAPHICS_WFI); - preemption_modes_rec->compute_preemption_mode_flags = ( - NVGPU_PREEMPTION_MODE_COMPUTE_WFI | - NVGPU_PREEMPTION_MODE_COMPUTE_CTA | - NVGPU_PREEMPTION_MODE_COMPUTE_CILP); - - preemption_modes_rec->default_graphics_preempt_mode = - NVGPU_PREEMPTION_MODE_GRAPHICS_WFI; - preemption_modes_rec->default_compute_preempt_mode = - NVGPU_PREEMPTION_MODE_COMPUTE_WFI; - - return 0; -} - -void gr_tu104_enable_gpc_exceptions(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - u32 tpc_mask; - - gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), - gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); - - tpc_mask = - gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->max_tpc_per_gpc_count) - 1); - - gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), - (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) | - gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1) | - gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1))); -} - -int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g, - enum ctxsw_addr_type addr_type, - u32 num_tpcs, - u32 num_ppcs, - u32 reg_list_ppc_count, - u32 *__offset_in_segment) -{ - u32 offset_in_segment = 0; - struct gr_gk20a *gr = &g->gr; - u32 num_pes_per_gpc = nvgpu_get_litter_value(g, - GPU_LIT_NUM_PES_PER_GPC); - - if (addr_type == CTXSW_ADDR_TYPE_TPC) { - /* - * reg = gr->ctx_vars.ctxsw_regs.tpc.l; - * offset_in_segment = 0; - */ - } else if (addr_type == CTXSW_ADDR_TYPE_PPC) { - /* - * The ucode stores TPC data before PPC data. - * Advance offset past TPC data to PPC data. - */ - offset_in_segment = - ((gr->ctx_vars.ctxsw_regs.tpc.count * - num_tpcs) << 2); - } else if (addr_type == CTXSW_ADDR_TYPE_GPC) { - /* - * The ucode stores TPC/PPC data before GPC data. - * Advance offset past TPC/PPC data to GPC data. - * - * Note 1 PES_PER_GPC case - */ - if (num_pes_per_gpc > 1) { - offset_in_segment = - (((gr->ctx_vars.ctxsw_regs.tpc.count * - num_tpcs) << 2) + - ((reg_list_ppc_count * num_ppcs) << 2)); - } else { - offset_in_segment = - ((gr->ctx_vars.ctxsw_regs.tpc.count * - num_tpcs) << 2); - } - } else if ((addr_type == CTXSW_ADDR_TYPE_EGPC) || - (addr_type == CTXSW_ADDR_TYPE_ETPC)) { - if (num_pes_per_gpc > 1) { - offset_in_segment = - ((gr->ctx_vars.ctxsw_regs.tpc.count * - num_tpcs) << 2) + - ((reg_list_ppc_count * num_ppcs) << 2) + - (gr->ctx_vars.ctxsw_regs.gpc.count << 2); - } else { - offset_in_segment = - ((gr->ctx_vars.ctxsw_regs.tpc.count * - num_tpcs) << 2) + - (gr->ctx_vars.ctxsw_regs.gpc.count << 2); - } - - /* aligned to next 256 byte */ - offset_in_segment = ALIGN(offset_in_segment, 256); - - nvgpu_log(g, gpu_dbg_info | gpu_dbg_gpu_dbg, - "egpc etpc offset_in_segment 0x%#08x", - offset_in_segment); - } else { - nvgpu_log_fn(g, "Unknown address type."); - return -EINVAL; - } - - *__offset_in_segment = offset_in_segment; - return 0; -} - -static void gr_tu104_set_sm_disp_ctrl(struct gk20a *g, u32 data) -{ - u32 reg_val; - - nvgpu_log_fn(g, " "); - - reg_val = nvgpu_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r()); - - if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK) - == NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE) { - reg_val = set_field(reg_val, - gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(), - gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f() - ); - } else if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK) - == NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE) { - reg_val = set_field(reg_val, - gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(), - gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f() - ); - } - - nvgpu_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), reg_val); -} - -int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr, - u32 class_num, u32 offset, u32 data) -{ - nvgpu_log_fn(g, " "); - - if (class_num == TURING_COMPUTE_A) { - switch (offset << 2) { - case NVC5C0_SET_SHADER_EXCEPTIONS: - gv11b_gr_set_shader_exceptions(g, data); - break; - case NVC5C0_SET_SKEDCHECK: - gr_gv11b_set_skedcheck(g, data); - break; - case NVC5C0_SET_SM_DISP_CTRL: - gr_tu104_set_sm_disp_ctrl(g, data); - break; - case NVC5C0_SET_SHADER_CUT_COLLECTOR: - gr_gv11b_set_shader_cut_collector(g, data); - break; - default: - goto fail; - } - } - - if (class_num == TURING_A) { - switch (offset << 2) { - case NVC597_SET_SHADER_EXCEPTIONS: - gv11b_gr_set_shader_exceptions(g, data); - break; - case NVC597_SET_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_circular_buffer_size(g, data); - break; - case NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_alpha_circular_buffer_size(g, data); - break; - case NVC597_SET_GO_IDLE_TIMEOUT: - gr_gv11b_set_go_idle_timeout(g, data); - break; - case NVC097_SET_COALESCE_BUFFER_SIZE: - gr_gv11b_set_coalesce_buffer_size(g, data); - break; - case NVC597_SET_TEX_IN_DBG: - gr_gv11b_set_tex_in_dbg(g, data); - break; - case NVC597_SET_SKEDCHECK: - gr_gv11b_set_skedcheck(g, data); - break; - case NVC597_SET_BES_CROP_DEBUG3: - g->ops.gr.set_bes_crop_debug3(g, data); - break; - case NVC597_SET_BES_CROP_DEBUG4: - g->ops.gr.set_bes_crop_debug4(g, data); - break; - case NVC597_SET_SHADER_CUT_COLLECTOR: - gr_gv11b_set_shader_cut_collector(g, data); - break; - default: - goto fail; - } - } - return 0; - -fail: - return -EINVAL; -} diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.h b/drivers/gpu/nvgpu/tu104/gr_tu104.h deleted file mode 100644 index 6eb9d224a..000000000 --- a/drivers/gpu/nvgpu/tu104/gr_tu104.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __GR_TU104_H__ -#define __GR_TU104_H__ - -#include - -struct gk20a; -struct nvgpu_preemption_modes_rec; - -enum { - TURING_CHANNEL_GPFIFO_A = 0xC46F, - TURING_A = 0xC597, - TURING_COMPUTE_A = 0xC5C0, - TURING_DMA_COPY_A = 0xC5B5, -}; - -#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC5C0_SET_SKEDCHECK 0x23c -#define NVC5C0_SET_SHADER_CUT_COLLECTOR 0x254 - -#define NVC5C0_SET_SM_DISP_CTRL 0x250 -#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK 0x1 -#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE 0 -#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE 1 - -#define NVC597_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280 -#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc -#define NVC597_SET_GO_IDLE_TIMEOUT 0x022c -#define NVC597_SET_TEX_IN_DBG 0x10bc -#define NVC597_SET_SKEDCHECK 0x10c0 -#define NVC597_SET_BES_CROP_DEBUG3 0x10c4 -#define NVC597_SET_BES_CROP_DEBUG4 0x10b0 -#define NVC597_SET_SHADER_CUT_COLLECTOR 0x10d0 - -/* TODO: merge these into global context buffer list in gr_gk20a.h */ -#define RTV_CIRCULAR_BUFFER 8 -#define RTV_CIRCULAR_BUFFER_VA 5 - -bool gr_tu104_is_valid_class(struct gk20a *g, u32 class_num); -bool gr_tu104_is_valid_gfx_class(struct gk20a *g, u32 class_num); -bool gr_tu104_is_valid_compute_class(struct gk20a *g, u32 class_num); - -int gr_tu104_init_sw_bundle64(struct gk20a *g); - -void gr_tu10x_create_sysfs(struct gk20a *g); -void gr_tu10x_remove_sysfs(struct gk20a *g); - -int gr_tu104_alloc_global_ctx_buffers(struct gk20a *g); -int gr_tu104_map_global_ctx_buffers(struct gk20a *g, - struct channel_gk20a *ch); -int gr_tu104_commit_global_ctx_buffers(struct gk20a *g, - struct channel_gk20a *ch, bool patch); - -void gr_tu104_bundle_cb_defaults(struct gk20a *g); -void gr_tu104_cb_size_default(struct gk20a *g); - -int gr_tu104_get_preemption_mode_flags(struct gk20a *g, - struct nvgpu_preemption_modes_rec *preemption_modes_rec); -void gr_tu104_enable_gpc_exceptions(struct gk20a *g); - -int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g, - enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs, - u32 reg_list_ppc_count, u32 *__offset_in_segment); - -int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr, - u32 class_num, u32 offset, u32 data); - -#endif diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c deleted file mode 100644 index 0e16bc2c2..000000000 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ /dev/null @@ -1,1003 +0,0 @@ -/* - * TU104 Tegra HAL interface - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "common/bus/bus_gk20a.h" -#include "common/bus/bus_gp10b.h" -#include "common/bus/bus_gv100.h" -#include "common/bus/bus_tu104.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" -#include "common/clock_gating/gv11b_gating_reglist.h" -#include "common/ptimer/ptimer_gk20a.h" -#include "common/fb/fb_gm20b.h" -#include "common/fb/fb_gp10b.h" -#include "common/fb/fb_gp106.h" -#include "common/fb/fb_gv11b.h" -#include "common/fb/fb_gv100.h" -#include "common/fb/fb_tu104.h" -#include "common/xve/xve_gp106.h" -#include "common/therm/therm_gm20b.h" -#include "common/therm/therm_gp10b.h" -#include "common/therm/therm_gp106.h" -#include "common/therm/therm_gv11b.h" -#include "common/ltc/ltc_gm20b.h" -#include "common/ltc/ltc_gp10b.h" -#include "common/ltc/ltc_gv11b.h" -#include "common/ltc/ltc_tu104.h" -#include "common/fuse/fuse_gm20b.h" -#include "common/fuse/fuse_gp10b.h" -#include "common/fuse/fuse_gp106.h" -#include "common/mc/mc_gm20b.h" -#include "common/mc/mc_gp10b.h" -#include "common/mc/mc_gv11b.h" -#include "common/mc/mc_gv100.h" -#include "common/mc/mc_tu104.h" -#include "common/perf/perf_gv11b.h" - -#include "gk20a/gk20a.h" -#include "gk20a/fifo_gk20a.h" -#include "gk20a/fecs_trace_gk20a.h" -#include "gk20a/css_gr_gk20a.h" -#include "gk20a/dbg_gpu_gk20a.h" -#include "gk20a/flcn_gk20a.h" -#include "gk20a/regops_gk20a.h" -#include "gk20a/mm_gk20a.h" -#include "gk20a/pmu_gk20a.h" -#include "gk20a/gr_gk20a.h" - -#include "gm20b/gr_gm20b.h" -#include "gm20b/fifo_gm20b.h" -#include "gm20b/mm_gm20b.h" -#include "gm20b/pmu_gm20b.h" -#include "gm20b/acr_gm20b.h" - -#include "gv100/clk_gv100.h" -#include "gp106/clk_arb_gp106.h" -#include "gp106/pmu_gp106.h" -#include "gp106/acr_gp106.h" -#include "gp106/sec2_gp106.h" -#include "gp106/bios_gp106.h" -#include "gp106/flcn_gp106.h" - -#include "gp10b/gr_gp10b.h" -#include "gp10b/ce_gp10b.h" -#include "gp10b/fifo_gp10b.h" -#include "gp10b/fecs_trace_gp10b.h" -#include "gp10b/mm_gp10b.h" -#include "gp10b/pmu_gp10b.h" - -#include "gv11b/css_gr_gv11b.h" -#include "gv11b/hal_gv11b.h" -#include "gv11b/gr_gv11b.h" -#include "gv11b/gv11b.h" -#include "gv11b/ce_gv11b.h" -#include "gv11b/mm_gv11b.h" -#include "gv11b/pmu_gv11b.h" -#include "gv11b/pmu_gv11b.h" -#include "gv11b/fifo_gv11b.h" -#include "gv11b/regops_gv11b.h" -#include "gv11b/subctx_gv11b.h" - -#include "gv100/bios_gv100.h" -#include "gv100/fifo_gv100.h" -#include "gv100/flcn_gv100.h" -#include "gv100/gr_ctx_gv100.h" -#include "gv100/gr_gv100.h" -#include "gv100/mm_gv100.h" -#include "gv100/pmu_gv100.h" -#include "gv100/nvlink_gv100.h" -#include "gv100/regops_gv100.h" - -#include "tu104/fifo_tu104.h" -#include "tu104/gr_tu104.h" -#include "tu104/bios_tu104.h" -#include "tu104/fbpa_tu104.h" -#include "tu104/gr_ctx_tu104.h" -#include "tu104/sec2_tu104.h" -#include "tu104/flcn_tu104.h" -#include "tu104/nvlink_tu104.h" -#include "tu104/ecc_tu104.h" -#include "tu104/hal_tu104.h" -#include "tu104/regops_tu104.h" -#include "tu104/acr_tu104.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -static u32 tu104_get_litter_value(struct gk20a *g, int value) -{ - u32 ret = 0; - switch (value) { - case GPU_LIT_NUM_GPCS: - ret = proj_scal_litter_num_gpcs_v(); - break; - case GPU_LIT_NUM_PES_PER_GPC: - ret = proj_scal_litter_num_pes_per_gpc_v(); - break; - case GPU_LIT_NUM_ZCULL_BANKS: - ret = proj_scal_litter_num_zcull_banks_v(); - break; - case GPU_LIT_NUM_TPC_PER_GPC: - ret = proj_scal_litter_num_tpc_per_gpc_v(); - break; - case GPU_LIT_NUM_SM_PER_TPC: - ret = proj_scal_litter_num_sm_per_tpc_v(); - break; - case GPU_LIT_NUM_FBPS: - ret = proj_scal_litter_num_fbps_v(); - break; - case GPU_LIT_GPC_BASE: - ret = proj_gpc_base_v(); - break; - case GPU_LIT_GPC_STRIDE: - ret = proj_gpc_stride_v(); - break; - case GPU_LIT_GPC_SHARED_BASE: - ret = proj_gpc_shared_base_v(); - break; - case GPU_LIT_TPC_IN_GPC_BASE: - ret = proj_tpc_in_gpc_base_v(); - break; - case GPU_LIT_TPC_IN_GPC_STRIDE: - ret = proj_tpc_in_gpc_stride_v(); - break; - case GPU_LIT_TPC_IN_GPC_SHARED_BASE: - ret = proj_tpc_in_gpc_shared_base_v(); - break; - case GPU_LIT_PPC_IN_GPC_BASE: - ret = proj_ppc_in_gpc_base_v(); - break; - case GPU_LIT_PPC_IN_GPC_STRIDE: - ret = proj_ppc_in_gpc_stride_v(); - break; - case GPU_LIT_PPC_IN_GPC_SHARED_BASE: - ret = proj_ppc_in_gpc_shared_base_v(); - break; - case GPU_LIT_ROP_BASE: - ret = proj_rop_base_v(); - break; - case GPU_LIT_ROP_STRIDE: - ret = proj_rop_stride_v(); - break; - case GPU_LIT_ROP_SHARED_BASE: - ret = proj_rop_shared_base_v(); - break; - case GPU_LIT_HOST_NUM_ENGINES: - ret = proj_host_num_engines_v(); - break; - case GPU_LIT_HOST_NUM_PBDMA: - ret = proj_host_num_pbdma_v(); - break; - case GPU_LIT_LTC_STRIDE: - ret = proj_ltc_stride_v(); - break; - case GPU_LIT_LTS_STRIDE: - ret = proj_lts_stride_v(); - break; - case GPU_LIT_NUM_FBPAS: - ret = proj_scal_litter_num_fbpas_v(); - break; - case GPU_LIT_FBPA_SHARED_BASE: - ret = proj_fbpa_shared_base_v(); - break; - case GPU_LIT_FBPA_BASE: - ret = proj_fbpa_base_v(); - break; - case GPU_LIT_FBPA_STRIDE: - ret = proj_fbpa_stride_v(); - break; - case GPU_LIT_SM_PRI_STRIDE: - ret = proj_sm_stride_v(); - break; - case GPU_LIT_SMPC_PRI_BASE: - ret = proj_smpc_base_v(); - break; - case GPU_LIT_SMPC_PRI_SHARED_BASE: - ret = proj_smpc_shared_base_v(); - break; - case GPU_LIT_SMPC_PRI_UNIQUE_BASE: - ret = proj_smpc_unique_base_v(); - break; - case GPU_LIT_SMPC_PRI_STRIDE: - ret = proj_smpc_stride_v(); - break; - case GPU_LIT_TWOD_CLASS: - ret = FERMI_TWOD_A; - break; - case GPU_LIT_THREED_CLASS: - ret = TURING_A; - break; - case GPU_LIT_COMPUTE_CLASS: - ret = TURING_COMPUTE_A; - break; - case GPU_LIT_GPFIFO_CLASS: - ret = TURING_CHANNEL_GPFIFO_A; - break; - case GPU_LIT_I2M_CLASS: - ret = KEPLER_INLINE_TO_MEMORY_B; - break; - case GPU_LIT_DMA_COPY_CLASS: - ret = TURING_DMA_COPY_A; - break; - case GPU_LIT_GPC_PRIV_STRIDE: - ret = proj_gpc_priv_stride_v(); - break; - default: - nvgpu_err(g, "Missing definition %d", value); - BUG(); - break; - } - - return ret; -} - -static int tu104_init_gpu_characteristics(struct gk20a *g) -{ - int err; - - err = gk20a_init_gpu_characteristics(g); - if (err) { - return err; - } - - __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); - - if (nvgpu_has_syncpoints(g)) { - __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); - } - - return 0; -} - - - -static const struct gpu_ops tu104_ops = { - .bios = { - .init = gp106_bios_init, - .preos_wait_for_halt = NULL, - .preos_reload_check = NULL, - .devinit = NULL, - .preos = NULL, - .verify_devinit = tu104_bios_verify_devinit, - }, - .ltc = { - .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, - .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = NULL, - .get_cbc_base_divisor = ltc_tu104_get_cbc_base_divisor, - .init_fs_state = ltc_tu104_init_fs_state, - .init_comptags = ltc_tu104_init_comptags, - .cbc_ctrl = ltc_tu104_cbc_ctrl, - .isr = tu104_ltc_isr, - .cbc_fix_config = NULL, - .flush = gm20b_flush_ltc, - .set_enabled = gp10b_ltc_set_enabled, - .intr_en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat, - .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr, - .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr, - .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr, - .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr, - .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr, - }, - .ce2 = { - .isr_stall = gv11b_ce_isr, - .isr_nonstall = NULL, - .get_num_pce = gv11b_ce_get_num_pce, - }, - .gr = { - .get_patch_slots = gr_gv100_get_patch_slots, - .init_gpc_mmu = gr_gv11b_init_gpc_mmu, - .bundle_cb_defaults = gr_tu104_bundle_cb_defaults, - .cb_size_default = gr_tu104_cb_size_default, - .calc_global_ctx_buffer_size = - gr_gv11b_calc_global_ctx_buffer_size, - .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, - .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, - .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, - .commit_global_pagepool = gr_gp10b_commit_global_pagepool, - .handle_sw_method = gr_tu104_handle_sw_method, - .set_alpha_circular_buffer_size = - gr_gv11b_set_alpha_circular_buffer_size, - .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, - .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, - .is_valid_class = gr_tu104_is_valid_class, - .is_valid_gfx_class = gr_tu104_is_valid_gfx_class, - .is_valid_compute_class = gr_tu104_is_valid_compute_class, - .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, - .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, - .init_fs_state = gr_gv11b_init_fs_state, - .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, - .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, - .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, - .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, - .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, - .get_gpc_mask = gr_gm20b_get_gpc_mask, - .alloc_obj_ctx = gk20a_alloc_obj_ctx, - .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, - .get_zcull_info = gr_gk20a_get_zcull_info, - .is_tpc_addr = gr_gm20b_is_tpc_addr, - .get_tpc_num = gr_gm20b_get_tpc_num, - .detect_sm_arch = gr_gv11b_detect_sm_arch, - .add_zbc_color = gr_gp10b_add_zbc_color, - .add_zbc_depth = gr_gp10b_add_zbc_depth, - .get_gpcs_swdx_dss_zbc_c_format_reg = - gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg, - .get_gpcs_swdx_dss_zbc_z_format_reg = - gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg, - .zbc_set_table = gk20a_gr_zbc_set_table, - .zbc_query_table = gr_gk20a_query_zbc, - .pmu_save_zbc = gk20a_pmu_save_zbc, - .add_zbc = gr_gk20a_add_zbc, - .pagepool_default_size = gr_gv11b_pagepool_default_size, - .init_ctx_state = gr_gp10b_init_ctx_state, - .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, - .free_gr_ctx = gr_gk20a_free_gr_ctx, - .update_ctxsw_preemption_mode = - gr_gp10b_update_ctxsw_preemption_mode, - .dump_gr_regs = gr_gv11b_dump_gr_status_regs, - .update_pc_sampling = gr_gm20b_update_pc_sampling, - .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, - .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, - .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, - .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, - .get_max_fbps_count = gr_gm20b_get_max_fbps_count, - .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, - .wait_empty = gr_gv11b_wait_empty, - .init_cyclestats = gr_gm20b_init_cyclestats, - .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, - .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, - .bpt_reg_info = gv11b_gr_bpt_reg_info, - .get_access_map = gr_gv11b_get_access_map, - .handle_fecs_error = gr_gv11b_handle_fecs_error, - .handle_sm_exception = gr_gk20a_handle_sm_exception, - .handle_tex_exception = NULL, - .enable_gpc_exceptions = gr_tu104_enable_gpc_exceptions, - .enable_exceptions = gr_gv11b_enable_exceptions, - .get_lrf_tex_ltc_dram_override = get_ecc_override_val, - .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, - .get_hw_accessor_stream_out_mode = - gr_gv100_get_hw_accessor_stream_out_mode, - .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, - .set_pmm_register = gr_gv100_set_pmm_register, - .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, - .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, - .record_sm_error_state = gv11b_gr_record_sm_error_state, - .clear_sm_error_state = gv11b_gr_clear_sm_error_state, - .suspend_contexts = gr_gp10b_suspend_contexts, - .resume_contexts = gr_gk20a_resume_contexts, - .get_preemption_mode_flags = gr_tu104_get_preemption_mode_flags, - .init_sm_id_table = gr_gv100_init_sm_id_table, - .load_smid_config = gr_gv11b_load_smid_config, - .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, - .setup_rop_mapping = gr_gv11b_setup_rop_mapping, - .program_zcull_mapping = gr_gv11b_program_zcull_mapping, - .commit_global_timeslice = gr_gv11b_commit_global_timeslice, - .commit_inst = gr_gv11b_commit_inst, - .write_zcull_ptr = gr_gv11b_write_zcull_ptr, - .write_pm_ptr = gr_gv11b_write_pm_ptr, - .load_tpc_mask = gr_gv11b_load_tpc_mask, - .trigger_suspend = gv11b_gr_sm_trigger_suspend, - .wait_for_pause = gr_gk20a_wait_for_pause, - .resume_from_pause = gv11b_gr_resume_from_pause, - .clear_sm_errors = gr_gk20a_clear_sm_errors, - .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, - .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, - .sm_debugger_attached = gv11b_gr_sm_debugger_attached, - .suspend_single_sm = gv11b_gr_suspend_single_sm, - .suspend_all_sms = gv11b_gr_suspend_all_sms, - .resume_single_sm = gv11b_gr_resume_single_sm, - .resume_all_sms = gv11b_gr_resume_all_sms, - .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, - .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, - .get_sm_no_lock_down_hww_global_esr_mask = - gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, - .lock_down_sm = gv11b_gr_lock_down_sm, - .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, - .clear_sm_hww = gv11b_gr_clear_sm_hww, - .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, - .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, - .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, - .set_boosted_ctx = gr_gp10b_set_boosted_ctx, - .set_preemption_mode = gr_gp10b_set_preemption_mode, - .set_czf_bypass = NULL, - .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, - .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, - .init_preemption_state = NULL, - .update_boosted_ctx = gr_gp10b_update_boosted_ctx, - .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, - .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, - .init_ecc = tu104_ecc_init, - .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, - .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, - .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, - .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, - .zbc_s_query_table = gr_gv11b_zbc_s_query_table, - .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, - .handle_gpc_gpcmmu_exception = - gr_gv11b_handle_gpc_gpcmmu_exception, - .add_zbc_type_s = gr_gv11b_add_zbc_type_s, - .get_egpc_base = gv11b_gr_get_egpc_base, - .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, - .handle_gpc_gpccs_exception = - gr_gv11b_handle_gpc_gpccs_exception, - .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, - .access_smpc_reg = gv11b_gr_access_smpc_reg, - .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, - .add_zbc_s = gr_gv11b_add_zbc_stencil, - .handle_gcc_exception = gr_gv11b_handle_gcc_exception, - .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, - .handle_tpc_sm_ecc_exception = - gr_gv11b_handle_tpc_sm_ecc_exception, - .decode_egpc_addr = gv11b_gr_decode_egpc_addr, - .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, - .handle_ssync_hww = gr_gv11b_handle_ssync_hww, - .handle_notify_pending = gk20a_gr_handle_notify_pending, - .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, - .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa, - .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, - .decode_priv_addr = gr_gv11b_decode_priv_addr, - .create_priv_addr_table = gr_gv11b_create_priv_addr_table, - .get_pmm_per_chiplet_offset = - gr_gv11b_get_pmm_per_chiplet_offset, - .init_sw_bundle64 = gr_tu104_init_sw_bundle64, - .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v, - .alloc_global_ctx_buffers = gr_tu104_alloc_global_ctx_buffers, - .map_global_ctx_buffers = gr_tu104_map_global_ctx_buffers, - .commit_global_ctx_buffers = gr_tu104_commit_global_ctx_buffers, - .get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc, - .get_offset_in_gpccs_segment = - gr_tu104_get_offset_in_gpccs_segment, - .set_debug_mode = gm20b_gr_set_debug_mode, - }, - .fb = { - .init_hw = gv11b_fb_init_hw, - .init_fs_state = gp106_fb_init_fs_state, - .init_cbc = fb_tu104_init_cbc, - .set_mmu_page_size = NULL, - .set_use_full_comp_tag_line = - gm20b_fb_set_use_full_comp_tag_line, - .mmu_ctrl = gm20b_fb_mmu_ctrl, - .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl, - .mmu_debug_wr = gm20b_fb_mmu_debug_wr, - .mmu_debug_rd = gm20b_fb_mmu_debug_rd, - .compression_page_size = gp10b_fb_compression_page_size, - .compressible_page_size = gp10b_fb_compressible_page_size, - .compression_align_mask = gm20b_fb_compression_align_mask, - .vpr_info_fetch = NULL, - .dump_vpr_info = NULL, - .dump_wpr_info = gm20b_fb_dump_wpr_info, - .read_wpr_info = gm20b_fb_read_wpr_info, - .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, - .set_debug_mode = gm20b_fb_set_debug_mode, - .tlb_invalidate = fb_tu104_tlb_invalidate, - .hub_isr = tu104_fb_hub_isr, - .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, - .mem_unlock = gv100_fb_memory_unlock, - .init_nvlink = gv100_fb_init_nvlink, - .enable_nvlink = gv100_fb_enable_nvlink, - .enable_hub_intr = tu104_fb_enable_hub_intr, - .disable_hub_intr = tu104_fb_disable_hub_intr, - .init_fbpa = tu104_fbpa_init, - .handle_fbpa_intr = tu104_fbpa_handle_intr, - .write_mmu_fault_buffer_lo_hi = - fb_tu104_write_mmu_fault_buffer_lo_hi, - .write_mmu_fault_buffer_get = - fb_tu104_write_mmu_fault_buffer_get, - .write_mmu_fault_buffer_size = - fb_tu104_write_mmu_fault_buffer_size, - .write_mmu_fault_status = fb_tu104_write_mmu_fault_status, - .read_mmu_fault_buffer_get = - fb_tu104_read_mmu_fault_buffer_get, - .read_mmu_fault_buffer_put = - fb_tu104_read_mmu_fault_buffer_put, - .read_mmu_fault_buffer_size = - fb_tu104_read_mmu_fault_buffer_size, - .read_mmu_fault_addr_lo_hi = fb_tu104_read_mmu_fault_addr_lo_hi, - .read_mmu_fault_inst_lo_hi = fb_tu104_read_mmu_fault_inst_lo_hi, - .read_mmu_fault_info = fb_tu104_read_mmu_fault_info, - .read_mmu_fault_status = fb_tu104_read_mmu_fault_status, - .mmu_invalidate_replay = fb_tu104_mmu_invalidate_replay, - .mmu_fault_pending = tu104_fb_mmu_fault_pending, - .is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled, - .fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw, - .fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw, - .get_vidmem_size = gv100_fb_get_vidmem_size, - .apply_pdb_cache_war = tu104_fb_apply_pdb_cache_war, - }, - .fifo = { - .get_preempt_timeout = gv100_fifo_get_preempt_timeout, - .init_fifo_setup_hw = tu104_init_fifo_setup_hw, - .bind_channel = channel_gm20b_bind, - .unbind_channel = channel_gv11b_unbind, - .disable_channel = gk20a_fifo_disable_channel, - .enable_channel = gk20a_fifo_enable_channel, - .alloc_inst = gk20a_fifo_alloc_inst, - .free_inst = gk20a_fifo_free_inst, - .setup_ramfc = channel_tu104_setup_ramfc, - .default_timeslice_us = gk20a_fifo_default_timeslice_us, - .setup_userd = gk20a_fifo_setup_userd, - .userd_gp_get = gv11b_userd_gp_get, - .userd_gp_put = gv11b_userd_gp_put, - .userd_pb_get = gv11b_userd_pb_get, - .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, - .preempt_channel = gv11b_fifo_preempt_channel, - .preempt_tsg = gv11b_fifo_preempt_tsg, - .enable_tsg = gv11b_fifo_enable_tsg, - .disable_tsg = gk20a_disable_tsg, - .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, - .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, - .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, - .update_runlist = gk20a_fifo_update_runlist, - .trigger_mmu_fault = NULL, - .get_mmu_fault_info = NULL, - .get_mmu_fault_desc = NULL, - .get_mmu_fault_client_desc = NULL, - .get_mmu_fault_gpc_desc = NULL, - .wait_engine_idle = gk20a_fifo_wait_engine_idle, - .get_num_fifos = gv100_fifo_get_num_fifos, - .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, - .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, - .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, - .force_reset_ch = gk20a_fifo_force_reset_ch, - .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, - .device_info_data_parse = gp10b_device_info_data_parse, - .eng_runlist_base_size = fifo_runlist_base_lo__size_1_v, - .init_engine_info = gk20a_fifo_init_engine_info, - .runlist_entry_size = ram_rl_entry_size_v, - .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, - .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, - .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, - .dump_pbdma_status = gk20a_dump_pbdma_status, - .dump_eng_status = gv11b_dump_eng_status, - .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, - .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, - .is_preempt_pending = gv11b_fifo_is_preempt_pending, - .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, - .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, - .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, - .handle_sched_error = gv11b_fifo_handle_sched_error, - .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, - .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, - .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, - .deinit_eng_method_buffers = - gv11b_fifo_deinit_eng_method_buffers, - .tsg_bind_channel = gk20a_tsg_bind_channel, - .tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel, - .post_event_id = gk20a_tsg_event_id_post_event, - .ch_abort_clean_up = gk20a_channel_abort_clean_up, - .check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout, - .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, - .channel_suspend = gk20a_channel_suspend, - .channel_resume = gk20a_channel_resume, - .set_error_notifier = nvgpu_set_error_notifier_if_empty, - .setup_sw = gk20a_init_fifo_setup_sw, -#ifdef CONFIG_TEGRA_GK20A_NVHOST - .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, - .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, - .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, - .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, - .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, - .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, - .get_syncpt_incr_per_release = - gv11b_fifo_get_syncpt_incr_per_release, - .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, -#endif - .resetup_ramfc = NULL, - .device_info_fault_id = top_device_info_data_fault_id_enum_v, - .free_channel_ctx_header = gv11b_free_subctx_header, - .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, - .runlist_hw_submit = tu104_fifo_runlist_hw_submit, - .runlist_wait_pending = tu104_fifo_runlist_wait_pending, - .ring_channel_doorbell = tu104_ring_channel_doorbell, - .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gv11b_fifo_add_sema_cmd, - .init_pdb_cache_war = tu104_init_pdb_cache_war, - .deinit_pdb_cache_war = tu104_deinit_pdb_cache_war, - }, - .gr_ctx = { - .get_netlist_name = gr_tu104_get_netlist_name, - .is_fw_defined = gr_tu104_is_firmware_defined, - }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = NULL, - .free_user_buffer = NULL, - .mmap_user_buffer = NULL, - .init = NULL, - .deinit = NULL, - .enable = NULL, - .disable = NULL, - .is_enabled = NULL, - .reset = NULL, - .flush = NULL, - .poll = NULL, - .bind_channel = NULL, - .unbind_channel = NULL, - .max_entries = NULL, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ - .mm = { - .support_sparse = gm20b_mm_support_sparse, - .gmmu_map = gk20a_locked_gmmu_map, - .gmmu_unmap = gk20a_locked_gmmu_unmap, - .vm_bind_channel = gk20a_vm_bind_channel, - .fb_flush = gk20a_mm_fb_flush, - .l2_invalidate = gk20a_mm_l2_invalidate, - .l2_flush = gv11b_mm_l2_flush, - .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, - .get_big_page_sizes = gm20b_mm_get_big_page_sizes, - .get_default_big_page_size = gp10b_mm_get_default_big_page_size, - .gpu_phys_addr = gv11b_gpu_phys_addr, - .get_mmu_levels = gp10b_mm_get_mmu_levels, - .init_pdb = gp10b_mm_init_pdb, - .init_mm_setup_hw = gv11b_init_mm_setup_hw, - .is_bar1_supported = gv11b_mm_is_bar1_supported, - .alloc_inst_block = gk20a_alloc_inst_block, - .init_inst_block = gv11b_init_inst_block, - .mmu_fault_pending = gv11b_mm_mmu_fault_pending, - .get_kind_invalid = gm20b_get_kind_invalid, - .get_kind_pitch = gm20b_get_kind_pitch, - .init_bar2_vm = gp10b_init_bar2_vm, - .remove_bar2_vm = gp10b_remove_bar2_vm, - .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, - .mmu_fault_disable_hw = gv11b_mm_mmu_fault_disable_hw, - .get_flush_retries = gv100_mm_get_flush_retries, - }, - .pramin = { - .data032_r = pram_data032_r, - }, - .therm = { - /* PROD values match with H/W INIT values */ - .init_elcg_mode = gv11b_therm_init_elcg_mode, - .init_blcg_mode = gm20b_therm_init_blcg_mode, - .elcg_init_idle_filters = NULL, - .get_internal_sensor_curr_temp = - gp106_get_internal_sensor_curr_temp, - }, - .pmu = { - .init_wpr_region = gv100_pmu_init_acr, - .load_lsfalcon_ucode = gv100_load_falcon_ucode, - .is_lazy_bootstrap = gp106_is_lazy_bootstrap, - .is_priv_load = gp106_is_priv_load, - .prepare_ucode = gp106_prepare_ucode_blob, - .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, - .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, - .pmu_queue_tail = gk20a_pmu_queue_tail, - .pmu_get_queue_head = pwr_pmu_queue_head_r, - .pmu_mutex_release = gk20a_pmu_mutex_release, - .pmu_is_interrupted = gk20a_pmu_is_interrupted, - .pmu_isr = gk20a_pmu_isr, - .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, - .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, - .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, - .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, - .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, - .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, - .pmu_enable_irq = gk20a_pmu_enable_irq, - .is_pmu_supported = gp106_is_pmu_supported, - .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, - .pmu_elpg_statistics = gp106_pmu_elpg_statistics, - .pmu_init_perfmon = nvgpu_pmu_init_perfmon, - .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, - .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, - .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, - .pmu_is_lpwr_feature_supported = - gp106_pmu_is_lpwr_feature_supported, - .pmu_msgq_tail = gk20a_pmu_msgq_tail, - .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, - .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, - .pmu_queue_head = gk20a_pmu_queue_head, - .pmu_pg_param_post_init = nvgpu_lpwr_post_init, - .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, - .pmu_pg_init_param = gp106_pg_param_init, - .reset_engine = gp106_pmu_engine_reset, - .write_dmatrfbase = gp10b_write_dmatrfbase, - .pmu_mutex_size = pwr_pmu_mutex__size_1_v, - .is_engine_in_reset = gp106_pmu_is_engine_in_reset, - .pmu_get_queue_tail = pwr_pmu_queue_tail_r, - .get_irqdest = gk20a_pmu_get_irqdest, - .alloc_super_surface = nvgpu_pmu_super_surface_alloc, - .handle_ext_irq = gv11b_pmu_handle_ext_irq, - .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, - .update_lspmu_cmdline_args = - gp106_update_lspmu_cmdline_args, - .setup_apertures = gp106_pmu_setup_apertures, - .secured_pmu_start = gm20b_secured_pmu_start, - }, - .clk = { - .init_clk_support = gv100_init_clk_support, - .get_crystal_clk_hz = gv100_crystal_clk_hz, - .get_rate_cntr = gv100_get_rate_cntr, - .measure_freq = gv100_clk_measure_freq, - .suspend_clk_support = gv100_suspend_clk_support, - }, - .clk_arb = { - .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, - .get_arbiter_clk_range = gp106_get_arbiter_clk_range, - .get_arbiter_clk_default = gp106_get_arbiter_clk_default, - .get_current_pstate = nvgpu_clk_arb_get_current_pstate, - }, - .regops = { - .exec_regops = exec_regops_gk20a, - .get_global_whitelist_ranges = - tu104_get_global_whitelist_ranges, - .get_global_whitelist_ranges_count = - tu104_get_global_whitelist_ranges_count, - .get_context_whitelist_ranges = - tu104_get_context_whitelist_ranges, - .get_context_whitelist_ranges_count = - tu104_get_context_whitelist_ranges_count, - .get_runcontrol_whitelist = tu104_get_runcontrol_whitelist, - .get_runcontrol_whitelist_count = - tu104_get_runcontrol_whitelist_count, - .get_qctl_whitelist = tu104_get_qctl_whitelist, - .get_qctl_whitelist_count = tu104_get_qctl_whitelist_count, - }, - .mc = { - .intr_enable = intr_tu104_enable, - .intr_mask = intr_tu104_mask, - .intr_unit_config = mc_gp10b_intr_unit_config, - .isr_stall = mc_gp10b_isr_stall, - .intr_stall = intr_tu104_stall, - .intr_stall_pause = intr_tu104_stall_pause, - .intr_stall_resume = intr_tu104_stall_resume, - .intr_nonstall = intr_tu104_nonstall, - .intr_nonstall_pause = intr_tu104_nonstall_pause, - .intr_nonstall_resume = intr_tu104_nonstall_resume, - .isr_nonstall = intr_tu104_isr_nonstall, - .enable = gm20b_mc_enable, - .disable = gm20b_mc_disable, - .reset = gm20b_mc_reset, - .is_intr1_pending = NULL, - .log_pending_intrs = intr_tu104_log_pending_intrs, - .is_intr_hub_pending = intr_tu104_is_intr_hub_pending, - .is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending, - .is_stall_and_eng_intr_pending = - gv100_mc_is_stall_and_eng_intr_pending, - .fbpa_isr = mc_tu104_fbpa_isr, - .reset_mask = gv100_mc_reset_mask, - .is_enabled = gm20b_mc_is_enabled, - .fb_reset = NULL, - }, - .debug = { - .show_dump = gk20a_debug_show_dump, - }, - .debugger = { - .post_events = gk20a_dbg_gpu_post_events, - }, - .dbg_session_ops = { - .dbg_set_powergate = dbg_set_powergate, - .check_and_set_global_reservation = - nvgpu_check_and_set_global_reservation, - .check_and_set_context_reservation = - nvgpu_check_and_set_context_reservation, - .release_profiler_reservation = - nvgpu_release_profiler_reservation, - }, - .perf = { - .enable_membuf = gv11b_perf_enable_membuf, - .disable_membuf = gv11b_perf_disable_membuf, - .membuf_reset_streaming = gv11b_perf_membuf_reset_streaming, - .get_membuf_pending_bytes = gv11b_perf_get_membuf_pending_bytes, - .set_membuf_handled_bytes = gv11b_perf_set_membuf_handled_bytes, - .get_membuf_overflow_status = - gv11b_perf_get_membuf_overflow_status, - }, - .perfbuf = { - .perfbuf_enable = nvgpu_perfbuf_enable_locked, - .perfbuf_disable = nvgpu_perfbuf_disable_locked, - }, - .bus = { - .init_hw = gk20a_bus_init_hw, - .isr = gk20a_bus_isr, - .bar1_bind = NULL, - .bar2_bind = bus_tu104_bar2_bind, - .set_bar0_window = gk20a_bus_set_bar0_window, - .read_sw_scratch = gv100_bus_read_sw_scratch, - .write_sw_scratch = gv100_bus_write_sw_scratch, - }, - .ptimer = { - .isr = gk20a_ptimer_isr, - .read_ptimer = gk20a_read_ptimer, - .get_timestamps_zipper = nvgpu_get_timestamps_zipper, - }, -#if defined(CONFIG_GK20A_CYCLE_STATS) - .css = { - .enable_snapshot = gv11b_css_hw_enable_snapshot, - .disable_snapshot = gv11b_css_hw_disable_snapshot, - .check_data_available = gv11b_css_hw_check_data_available, - .set_handled_snapshots = gv11b_css_hw_set_handled_snapshots, - .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, - .release_perfmon_ids = css_gr_release_perfmon_ids, - .get_overflow_status = gv11b_css_hw_get_overflow_status, - .get_pending_snapshots = gv11b_css_hw_get_pending_snapshots, - }, -#endif - .xve = { - .get_speed = xve_get_speed_gp106, - .xve_readl = xve_xve_readl_gp106, - .xve_writel = xve_xve_writel_gp106, - .disable_aspm = xve_disable_aspm_gp106, - .reset_gpu = xve_reset_gpu_gp106, -#if defined(CONFIG_PCI_MSI) - .rearm_msi = xve_rearm_msi_gp106, -#endif - .enable_shadow_rom = NULL, - .disable_shadow_rom = NULL, - }, - .falcon = { - .falcon_hal_sw_init = tu104_falcon_hal_sw_init, - }, - .priv_ring = { - .enable_priv_ring = gm20b_priv_ring_enable, - .isr = gp10b_priv_ring_isr, - .decode_error_code = gp10b_priv_ring_decode_error_code, - .set_ppriv_timeout_settings = NULL, - .enum_ltc = gm20b_priv_ring_enum_ltc, - }, - .fuse = { - .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, - .is_opt_feature_override_disable = - gp10b_fuse_is_opt_feature_override_disable, - .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, - .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, - .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, - .fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc, - .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, - .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, - .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, - .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, - .read_vin_cal_fuse_rev = gp106_fuse_read_vin_cal_fuse_rev, - .read_vin_cal_slope_intercept_fuse = - gp106_fuse_read_vin_cal_slope_intercept_fuse, - .read_vin_cal_gain_offset_fuse = - gp106_fuse_read_vin_cal_gain_offset_fuse, - }, -#if defined(CONFIG_TEGRA_NVLINK) - .nvlink = { - .discover_ioctrl = gv100_nvlink_discover_ioctrl, - .discover_link = gv100_nvlink_discover_link, - .init = gv100_nvlink_init, - .isr = gv100_nvlink_isr, - .rxdet = tu104_nvlink_rxdet, - .setup_pll = tu104_nvlink_setup_pll, - .minion_data_ready_en = tu104_nvlink_minion_data_ready_en, - .get_connected_link_mask = tu104_nvlink_get_connected_link_mask, - .set_sw_war = NULL, - /* API */ - .link_early_init = gv100_nvlink_link_early_init, - .link_get_state = gv100_nvlink_link_get_state, - .link_set_mode = gv100_nvlink_link_set_mode, - .link_get_mode = gv100_nvlink_link_get_mode, - .get_sublink_mode = gv100_nvlink_link_get_sublink_mode, - .get_tx_sublink_state = tu104_nvlink_link_get_tx_sublink_state, - .get_rx_sublink_state = tu104_nvlink_link_get_rx_sublink_state, - .set_sublink_mode = gv100_nvlink_link_set_sublink_mode, - .interface_init = gv100_nvlink_interface_init, - .reg_init = gv100_nvlink_reg_init, - .shutdown = gv100_nvlink_shutdown, - .early_init = gv100_nvlink_early_init, - }, -#endif - .acr = { - .acr_sw_init = nvgpu_tu104_acr_sw_init, - }, - .sec2 = { - .secured_sec2_start = tu104_start_sec2_secure, - .enable_irq = tu104_sec2_enable_irq, - .is_interrupted = tu104_sec2_is_interrupted, - .isr = tu104_sec2_isr, - .msgq_tail = tu104_sec2_msgq_tail, - }, - .chip_init_gpu_characteristics = tu104_init_gpu_characteristics, - .get_litter_value = tu104_get_litter_value, -}; - -int tu104_init_hal(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - - gops->bios = tu104_ops.bios; - gops->ltc = tu104_ops.ltc; - gops->ce2 = tu104_ops.ce2; - gops->gr = tu104_ops.gr; - gops->fb = tu104_ops.fb; - gops->clock_gating = tu104_ops.clock_gating; - gops->fifo = tu104_ops.fifo; - gops->gr_ctx = tu104_ops.gr_ctx; - gops->mm = tu104_ops.mm; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = tu104_ops.fecs_trace; -#endif - gops->pramin = tu104_ops.pramin; - gops->therm = tu104_ops.therm; - gops->pmu = tu104_ops.pmu; - gops->regops = tu104_ops.regops; - gops->mc = tu104_ops.mc; - gops->debug = tu104_ops.debug; - gops->debugger = tu104_ops.debugger; - gops->dbg_session_ops = tu104_ops.dbg_session_ops; - gops->perf = tu104_ops.perf; - gops->perfbuf = tu104_ops.perfbuf; - gops->bus = tu104_ops.bus; - gops->ptimer = tu104_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) - gops->css = tu104_ops.css; -#endif - gops->xve = tu104_ops.xve; - gops->falcon = tu104_ops.falcon; - gops->priv_ring = tu104_ops.priv_ring; - gops->fuse = tu104_ops.fuse; - gops->nvlink = tu104_ops.nvlink; - gops->acr = tu104_ops.acr; - gops->sec2 = tu104_ops.sec2; - - /* clocks */ - gops->clk.init_clk_support = tu104_ops.clk.init_clk_support; - gops->clk.get_rate_cntr = tu104_ops.clk.get_rate_cntr; - gops->clk.get_crystal_clk_hz = tu104_ops.clk.get_crystal_clk_hz; - gops->clk.measure_freq = tu104_ops.clk.measure_freq; - gops->clk.suspend_clk_support = tu104_ops.clk.suspend_clk_support; - - /* Lone functions */ - gops->chip_init_gpu_characteristics = - tu104_ops.chip_init_gpu_characteristics; - gops->get_litter_value = tu104_ops.get_litter_value; - gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup; - - __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); - __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, true); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, false); - - /* for now */ - __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); - - g->pmu_lsf_pmu_wpr_init_done = 0; - - g->name = "tu10x"; - - return 0; -} diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.h b/drivers/gpu/nvgpu/tu104/hal_tu104.h deleted file mode 100644 index 4a6202ff6..000000000 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * TU104 Tegra HAL interface - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVGPU_HAL_TU104_H__ -#define __NVGPU_HAL_TU104_H__ - -struct gk20a; - -int tu104_init_hal(struct gk20a *gops); - -#endif diff --git a/drivers/gpu/nvgpu/tu104/nvlink_tu104.c b/drivers/gpu/nvgpu/tu104/nvlink_tu104.c deleted file mode 100644 index 807805282..000000000 --- a/drivers/gpu/nvgpu/tu104/nvlink_tu104.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef CONFIG_TEGRA_NVLINK - -#include -#include -#include -#include -#include -#include - -#include "gk20a/gk20a.h" -#include "gv100/nvlink_gv100.h" -#include "nvlink_tu104.h" - -#include -#include - -int tu104_nvlink_rxdet(struct gk20a *g, u32 link_id) -{ - u32 ret = 0; - u32 reg; - struct nvgpu_timeout timeout; - - ret = gv100_nvlink_minion_send_command(g, link_id, - 0x00000005U, 0, true); - if (ret) { - nvgpu_err(g, "Error during INITRXTERM minion DLCMD on link %u", - link_id); - return ret; - } - - ret = gv100_nvlink_minion_send_command(g, link_id, - minion_nvlink_dl_cmd_command_turing_rxdet_v(), 0, true); - if (ret) { - nvgpu_err(g, "Error during RXDET minion DLCMD on link %u", - link_id); - return ret; - } - - ret = nvgpu_timeout_init(g, &timeout, NV_NVLINK_REG_POLL_TIMEOUT_MS, - NVGPU_TIMER_CPU_TIMER); - if (ret != 0) { - nvgpu_err(g, "Error during timeout init"); - return ret; - } - - do { - reg = DLPL_REG_RD32(g, link_id, nvl_sl0_link_rxdet_status_r()); - if (nvl_sl0_link_rxdet_status_sts_v(reg) == - nvl_sl0_link_rxdet_status_sts_found_v()) { - nvgpu_log(g, gpu_dbg_nvlink, - "RXDET successful on link %u", link_id); - return ret; - } - if (nvl_sl0_link_rxdet_status_sts_v(reg) == - nvl_sl0_link_rxdet_status_sts_timeout_v()) { - nvgpu_log(g, gpu_dbg_nvlink, - "RXDET failed on link %u", link_id); - break; - } - nvgpu_udelay(NV_NVLINK_TIMEOUT_DELAY_US); - } while (!nvgpu_timeout_expired_msg( - &timeout, - "RXDET status check timed out on link %u", - link_id)); - return -ETIMEDOUT; -} - -int tu104_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) -{ - int ret = 0; - u32 link_id; - u32 reg; - struct nvgpu_timeout timeout; - - for_each_set_bit(link_id, &link_mask, 32) { - ret = gv100_nvlink_minion_send_command(g, link_id, - minion_nvlink_dl_cmd_command_txclkswitch_pll_v(), - 0, true); - if (ret) { - nvgpu_err(g, "Error: TXCLKSWITCH_PLL dlcmd on link %u", - link_id); - return ret; - } - - ret = nvgpu_timeout_init(g, &timeout, - NV_NVLINK_REG_POLL_TIMEOUT_MS, NVGPU_TIMER_CPU_TIMER); - if (ret) { - nvgpu_err(g, "Error during timeout init"); - return ret; - } - do { - reg = DLPL_REG_RD32(g, link_id, nvl_clk_status_r()); - if (nvl_clk_status_txclk_sts_v(reg) == - nvl_clk_status_txclk_sts_pll_clk_v()) { - nvgpu_log(g, gpu_dbg_nvlink, - "PLL SETUP successful on link %u", - link_id); - break; - } - nvgpu_udelay(NV_NVLINK_TIMEOUT_DELAY_US); - } while ((!nvgpu_timeout_expired_msg(&timeout, - "Timed out setting pll on link %u", - link_id))); - if (nvgpu_timeout_peek_expired(&timeout)) { - return -ETIMEDOUT; - } - } - return ret; -} - -u32 tu104_nvlink_link_get_tx_sublink_state(struct gk20a *g, u32 link_id) -{ - u32 reg; - struct nvgpu_timeout timeout; - int err = 0; - - err = nvgpu_timeout_init(g, &timeout, NV_NVLINK_REG_POLL_TIMEOUT_MS, - NVGPU_TIMER_CPU_TIMER); - if (err != 0) { - nvgpu_err(g, "Failed to init timeout: %d", err); - goto result; - } - - /* Poll till substate value becomes STABLE */ - do { - reg = DLPL_REG_RD32(g, link_id, nvl_sl0_slsm_status_tx_r()); - if (nvl_sl0_slsm_status_tx_substate_v(reg) == - nvl_sl0_slsm_status_tx_substate_stable_v()) { - return nvl_sl0_slsm_status_tx_primary_state_v(reg); - } - nvgpu_udelay(NV_NVLINK_TIMEOUT_DELAY_US); - } while (!nvgpu_timeout_expired_msg(&timeout, - "Timeout on TX SLSM substate = stable check")); - - nvgpu_log(g, gpu_dbg_nvlink, "TX SLSM primary state :%u, substate:%u", - nvl_sl0_slsm_status_tx_primary_state_v(reg), - nvl_sl0_slsm_status_tx_substate_v(reg)); - -result: - return nvl_sl0_slsm_status_tx_primary_state_unknown_v(); -} - -u32 tu104_nvlink_link_get_rx_sublink_state(struct gk20a *g, u32 link_id) -{ - u32 reg; - struct nvgpu_timeout timeout; - int err = 0; - - err = nvgpu_timeout_init(g, &timeout, NV_NVLINK_REG_POLL_TIMEOUT_MS, - NVGPU_TIMER_CPU_TIMER); - if (err != 0) { - nvgpu_err(g, "Failed to init timeout: %d", err); - goto result; - } - - /* Poll till substate value becomes STABLE */ - do { - reg = DLPL_REG_RD32(g, link_id, nvl_sl1_slsm_status_rx_r()); - if (nvl_sl1_slsm_status_rx_substate_v(reg) == - nvl_sl1_slsm_status_rx_substate_stable_v()) { - return nvl_sl1_slsm_status_rx_primary_state_v(reg); - } - nvgpu_udelay(NV_NVLINK_TIMEOUT_DELAY_US); - } while (!nvgpu_timeout_expired_msg(&timeout, - "Timeout on RX SLSM substate = stable check")); - - nvgpu_log(g, gpu_dbg_nvlink, "RX SLSM primary state :%u, substate:%u", - nvl_sl1_slsm_status_rx_primary_state_v(reg), - nvl_sl1_slsm_status_rx_substate_v(reg)); - -result: - return nvl_sl1_slsm_status_rx_primary_state_unknown_v(); -} - -int tu104_nvlink_minion_data_ready_en(struct gk20a *g, - unsigned long link_mask, bool sync) -{ - int ret = 0; - u32 link_id; - - /* On Volta, the order of INIT* DLCMDs was arbitrary. - * On Turing, the INIT* DLCMDs need to be executed in the following - * order - - * INITDLPL -> INITL -> INITLANEENABLE. - * INITDLPL_TO_CHIPA is needed additionally when connected to 2.0 dev. - */ - for_each_set_bit(link_id, &link_mask, 32) { - ret = gv100_nvlink_minion_send_command(g, link_id, - minion_nvlink_dl_cmd_command_initdlpl_v(), 0, - sync); - if (ret) { - nvgpu_err(g, "Minion initdlpl failed on link %u", - link_id); - return ret; - } - } - for_each_set_bit(link_id, &link_mask, 32) { - ret = gv100_nvlink_minion_send_command(g, link_id, - minion_nvlink_dl_cmd_command_turing_initdlpl_to_chipa_v(), - 0, sync); - if (ret) { - nvgpu_err(g, "Minion initdlpl_to_chipA failed on link\ - %u", link_id); - return ret; - } - } - for_each_set_bit(link_id, &link_mask, 32) { - ret = gv100_nvlink_minion_send_command(g, link_id, - minion_nvlink_dl_cmd_command_inittl_v(), 0, - sync); - if (ret) { - nvgpu_err(g, "Minion inittl failed on link %u", - link_id); - return ret; - } - } - for_each_set_bit(link_id, &link_mask, 32) { - ret = gv100_nvlink_minion_send_command(g, link_id, - minion_nvlink_dl_cmd_command_initlaneenable_v(), 0, - sync); - if (ret) { - nvgpu_err(g, "Minion initlaneenable failed on link %u", - link_id); - return ret; - } - } - return ret; -} - -void tu104_nvlink_get_connected_link_mask(u32 *link_mask) -{ - *link_mask = TU104_CONNECTED_LINK_MASK; -} - -#endif /* CONFIG_TEGRA_NVLINK */ diff --git a/drivers/gpu/nvgpu/tu104/nvlink_tu104.h b/drivers/gpu/nvgpu/tu104/nvlink_tu104.h deleted file mode 100644 index 99010010a..000000000 --- a/drivers/gpu/nvgpu/tu104/nvlink_tu104.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NVLINK_TU104_H -#define NVGPU_NVLINK_TU104_H - -#define TU104_CONNECTED_LINK_MASK 0x1 - -struct gk20a; - -/* API */ -int tu104_nvlink_rxdet(struct gk20a *g, u32 link_id); -int tu104_nvlink_setup_pll(struct gk20a *g, unsigned long mask); -u32 tu104_nvlink_link_get_tx_sublink_state(struct gk20a *g, u32 link_id); -u32 tu104_nvlink_link_get_rx_sublink_state(struct gk20a *g, u32 link_id); -int tu104_nvlink_minion_data_ready_en(struct gk20a *g, unsigned long mask, - bool sync); -void tu104_nvlink_get_connected_link_mask(u32 *link_mask); -#endif diff --git a/drivers/gpu/nvgpu/tu104/regops_tu104.c b/drivers/gpu/nvgpu/tu104/regops_tu104.c deleted file mode 100644 index e6309a1c0..000000000 --- a/drivers/gpu/nvgpu/tu104/regops_tu104.c +++ /dev/null @@ -1,5449 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" -#include "gk20a/regops_gk20a.h" - -#include "regops_tu104.h" - -static const struct regop_offset_range tu104_global_whitelist_ranges[] = { - { 0x000004f0, 1}, - { 0x000010c0, 1}, - { 0x00001a00, 1}, - { 0x00009400, 1}, - { 0x00009410, 1}, - { 0x00009480, 1}, - { 0x00020200, 32}, - { 0x00021c04, 2}, - { 0x00021c14, 3}, - { 0x00021c24, 37}, - { 0x00021d38, 1}, - { 0x00021d68, 18}, - { 0x00021dbc, 16}, - { 0x00022430, 7}, - { 0x00022450, 1}, - { 0x0002245c, 2}, - { 0x00070000, 5}, - { 0x000884e0, 1}, - { 0x000884f4, 1}, - { 0x0008e00c, 1}, - { 0x00100c18, 3}, - { 0x00100c84, 1}, - { 0x0010a0a8, 1}, - { 0x0010a4f0, 1}, - { 0x0013c808, 2}, - { 0x0013cc14, 1}, - { 0x0013cc34, 1}, - { 0x0013cc54, 1}, - { 0x0013cc74, 1}, - { 0x0013cc94, 1}, - { 0x0013ccb4, 1}, - { 0x0013ec18, 1}, - { 0x00140028, 1}, - { 0x00140280, 1}, - { 0x001402a0, 1}, - { 0x00140350, 1}, - { 0x00140480, 1}, - { 0x001404a0, 1}, - { 0x00140550, 1}, - { 0x00140680, 1}, - { 0x001406a0, 1}, - { 0x00140750, 1}, - { 0x00140880, 1}, - { 0x001408a0, 1}, - { 0x00140950, 1}, - { 0x00140a80, 1}, - { 0x00140aa0, 1}, - { 0x00140b50, 1}, - { 0x00142028, 1}, - { 0x00142280, 1}, - { 0x001422a0, 1}, - { 0x00142350, 1}, - { 0x00142480, 1}, - { 0x001424a0, 1}, - { 0x00142550, 1}, - { 0x00142680, 1}, - { 0x001426a0, 1}, - { 0x00142750, 1}, - { 0x00142880, 1}, - { 0x001428a0, 1}, - { 0x00142950, 1}, - { 0x00142a80, 1}, - { 0x00142aa0, 1}, - { 0x00142b50, 1}, - { 0x00144028, 1}, - { 0x00144280, 1}, - { 0x00144350, 1}, - { 0x00144480, 1}, - { 0x00144550, 1}, - { 0x00144680, 1}, - { 0x00144750, 1}, - { 0x00144880, 1}, - { 0x00144950, 1}, - { 0x00144a80, 1}, - { 0x00144b50, 1}, - { 0x00146028, 1}, - { 0x00146280, 1}, - { 0x00146350, 1}, - { 0x00146480, 1}, - { 0x00146550, 1}, - { 0x00146680, 1}, - { 0x00146750, 1}, - { 0x00146880, 1}, - { 0x00146950, 1}, - { 0x00146a80, 1}, - { 0x00146b50, 1}, - { 0x00148028, 1}, - { 0x00148280, 1}, - { 0x00148350, 1}, - { 0x00148480, 1}, - { 0x00148550, 1}, - { 0x00148680, 1}, - { 0x00148750, 1}, - { 0x00148880, 1}, - { 0x00148950, 1}, - { 0x00148a80, 1}, - { 0x00148b50, 1}, - { 0x0014a028, 1}, - { 0x0014a280, 1}, - { 0x0014a350, 1}, - { 0x0014a480, 1}, - { 0x0014a550, 1}, - { 0x0014a680, 1}, - { 0x0014a750, 1}, - { 0x0014a880, 1}, - { 0x0014a950, 1}, - { 0x0014aa80, 1}, - { 0x0014ab50, 1}, - { 0x0014c028, 1}, - { 0x0014c280, 1}, - { 0x0014c350, 1}, - { 0x0014c480, 1}, - { 0x0014c550, 1}, - { 0x0014c680, 1}, - { 0x0014c750, 1}, - { 0x0014c880, 1}, - { 0x0014c950, 1}, - { 0x0014ca80, 1}, - { 0x0014cb50, 1}, - { 0x0014e028, 1}, - { 0x0014e280, 1}, - { 0x0014e350, 1}, - { 0x0014e480, 1}, - { 0x0014e550, 1}, - { 0x0014e680, 1}, - { 0x0014e750, 1}, - { 0x0014e880, 1}, - { 0x0014e950, 1}, - { 0x0014ea80, 1}, - { 0x0014eb50, 1}, - { 0x00150028, 1}, - { 0x00150280, 1}, - { 0x00150350, 1}, - { 0x00150480, 1}, - { 0x00150550, 1}, - { 0x00150680, 1}, - { 0x00150750, 1}, - { 0x00150880, 1}, - { 0x00150950, 1}, - { 0x00150a80, 1}, - { 0x00150b50, 1}, - { 0x00152028, 1}, - { 0x00152280, 1}, - { 0x00152350, 1}, - { 0x00152480, 1}, - { 0x00152550, 1}, - { 0x00152680, 1}, - { 0x00152750, 1}, - { 0x00152880, 1}, - { 0x00152950, 1}, - { 0x00152a80, 1}, - { 0x00152b50, 1}, - { 0x00154028, 1}, - { 0x00154280, 1}, - { 0x00154350, 1}, - { 0x00154480, 1}, - { 0x00154550, 1}, - { 0x00154680, 1}, - { 0x00154750, 1}, - { 0x00154880, 1}, - { 0x00154950, 1}, - { 0x00154a80, 1}, - { 0x00154b50, 1}, - { 0x00156028, 1}, - { 0x00156280, 1}, - { 0x00156350, 1}, - { 0x00156480, 1}, - { 0x00156550, 1}, - { 0x00156680, 1}, - { 0x00156750, 1}, - { 0x00156880, 1}, - { 0x00156950, 1}, - { 0x00156a80, 1}, - { 0x00156b50, 1}, - { 0x00158028, 1}, - { 0x00158280, 1}, - { 0x00158350, 1}, - { 0x00158480, 1}, - { 0x00158550, 1}, - { 0x00158680, 1}, - { 0x00158750, 1}, - { 0x00158880, 1}, - { 0x00158950, 1}, - { 0x00158a80, 1}, - { 0x00158b50, 1}, - { 0x0015a028, 1}, - { 0x0015a280, 1}, - { 0x0015a350, 1}, - { 0x0015a480, 1}, - { 0x0015a550, 1}, - { 0x0015a680, 1}, - { 0x0015a750, 1}, - { 0x0015a880, 1}, - { 0x0015a950, 1}, - { 0x0015aa80, 1}, - { 0x0015ab50, 1}, - { 0x0015c028, 1}, - { 0x0015c280, 1}, - { 0x0015c350, 1}, - { 0x0015c480, 1}, - { 0x0015c550, 1}, - { 0x0015c680, 1}, - { 0x0015c750, 1}, - { 0x0015c880, 1}, - { 0x0015c950, 1}, - { 0x0015ca80, 1}, - { 0x0015cb50, 1}, - { 0x0015e028, 1}, - { 0x0015e280, 1}, - { 0x0015e350, 1}, - { 0x0015e480, 1}, - { 0x0015e550, 1}, - { 0x0015e680, 1}, - { 0x0015e750, 1}, - { 0x0015e880, 1}, - { 0x0015e950, 1}, - { 0x0015ea80, 1}, - { 0x0015eb50, 1}, - { 0x0017e028, 1}, - { 0x0017e280, 1}, - { 0x0017e294, 1}, - { 0x0017e29c, 2}, - { 0x0017e2ac, 1}, - { 0x0017e350, 1}, - { 0x0017e39c, 1}, - { 0x0017e480, 1}, - { 0x0017e4a0, 1}, - { 0x0017e550, 1}, - { 0x0017e680, 1}, - { 0x0017e6a0, 1}, - { 0x0017e750, 1}, - { 0x0017e880, 1}, - { 0x0017e8a0, 1}, - { 0x0017e950, 1}, - { 0x0017ea80, 1}, - { 0x0017eaa0, 1}, - { 0x0017eb50, 1}, - { 0x00180040, 41}, - { 0x001800ec, 1}, - { 0x001800f8, 7}, - { 0x00180120, 2}, - { 0x00180240, 41}, - { 0x001802ec, 1}, - { 0x001802f8, 7}, - { 0x00180320, 2}, - { 0x00180440, 41}, - { 0x001804ec, 1}, - { 0x001804f8, 7}, - { 0x00180520, 2}, - { 0x00180640, 41}, - { 0x001806ec, 1}, - { 0x001806f8, 7}, - { 0x00180720, 2}, - { 0x00180840, 41}, - { 0x001808ec, 1}, - { 0x001808f8, 7}, - { 0x00180920, 2}, - { 0x00180a40, 41}, - { 0x00180aec, 1}, - { 0x00180af8, 7}, - { 0x00180b20, 2}, - { 0x00180c40, 41}, - { 0x00180cec, 1}, - { 0x00180cf8, 7}, - { 0x00180d20, 2}, - { 0x00180e40, 41}, - { 0x00180eec, 1}, - { 0x00180ef8, 7}, - { 0x00180f20, 2}, - { 0x00181040, 41}, - { 0x001810ec, 1}, - { 0x001810f8, 7}, - { 0x00181120, 2}, - { 0x00181240, 41}, - { 0x001812ec, 1}, - { 0x001812f8, 7}, - { 0x00181320, 2}, - { 0x00181440, 41}, - { 0x001814ec, 1}, - { 0x001814f8, 7}, - { 0x00181520, 2}, - { 0x00181640, 41}, - { 0x001816ec, 1}, - { 0x001816f8, 7}, - { 0x00181720, 2}, - { 0x00181840, 41}, - { 0x001818ec, 1}, - { 0x001818f8, 7}, - { 0x00181920, 2}, - { 0x00181a40, 41}, - { 0x00181aec, 1}, - { 0x00181af8, 7}, - { 0x00181b20, 2}, - { 0x00181c40, 41}, - { 0x00181cec, 1}, - { 0x00181cf8, 7}, - { 0x00181d20, 2}, - { 0x00181e40, 41}, - { 0x00181eec, 1}, - { 0x00181ef8, 7}, - { 0x00181f20, 2}, - { 0x00182040, 41}, - { 0x001820ec, 1}, - { 0x001820f8, 7}, - { 0x00182120, 2}, - { 0x00182240, 41}, - { 0x001822ec, 1}, - { 0x001822f8, 7}, - { 0x00182320, 2}, - { 0x00182440, 41}, - { 0x001824ec, 1}, - { 0x001824f8, 7}, - { 0x00182520, 2}, - { 0x00182640, 41}, - { 0x001826ec, 1}, - { 0x001826f8, 7}, - { 0x00182720, 2}, - { 0x00182840, 41}, - { 0x001828ec, 1}, - { 0x001828f8, 7}, - { 0x00182920, 2}, - { 0x00182a40, 41}, - { 0x00182aec, 1}, - { 0x00182af8, 7}, - { 0x00182b20, 2}, - { 0x00182c40, 41}, - { 0x00182cec, 1}, - { 0x00182cf8, 7}, - { 0x00182d20, 2}, - { 0x00182e40, 41}, - { 0x00182eec, 1}, - { 0x00182ef8, 7}, - { 0x00182f20, 2}, - { 0x00183040, 41}, - { 0x001830ec, 1}, - { 0x001830f8, 7}, - { 0x00183120, 2}, - { 0x00183240, 41}, - { 0x001832ec, 1}, - { 0x001832f8, 7}, - { 0x00183320, 2}, - { 0x00183440, 41}, - { 0x001834ec, 1}, - { 0x001834f8, 7}, - { 0x00183520, 2}, - { 0x00183640, 41}, - { 0x001836ec, 1}, - { 0x001836f8, 7}, - { 0x00183720, 2}, - { 0x00183840, 41}, - { 0x001838ec, 1}, - { 0x001838f8, 7}, - { 0x00183920, 2}, - { 0x00183a40, 41}, - { 0x00183aec, 1}, - { 0x00183af8, 7}, - { 0x00183b20, 2}, - { 0x00183c40, 41}, - { 0x00183cec, 1}, - { 0x00183cf8, 7}, - { 0x00183d20, 2}, - { 0x00183e40, 41}, - { 0x00183eec, 1}, - { 0x00183ef8, 7}, - { 0x00183f20, 2}, - { 0x00184040, 41}, - { 0x001840ec, 1}, - { 0x001840f8, 7}, - { 0x00184120, 2}, - { 0x00184240, 41}, - { 0x001842ec, 1}, - { 0x001842f8, 7}, - { 0x00184320, 2}, - { 0x00184440, 41}, - { 0x001844ec, 1}, - { 0x001844f8, 7}, - { 0x00184520, 2}, - { 0x00184640, 41}, - { 0x001846ec, 1}, - { 0x001846f8, 7}, - { 0x00184720, 2}, - { 0x00184840, 41}, - { 0x001848ec, 1}, - { 0x001848f8, 7}, - { 0x00184920, 2}, - { 0x00184a40, 41}, - { 0x00184aec, 1}, - { 0x00184af8, 7}, - { 0x00184b20, 2}, - { 0x00184c40, 41}, - { 0x00184cec, 1}, - { 0x00184cf8, 7}, - { 0x00184d20, 2}, - { 0x00184e40, 41}, - { 0x00184eec, 1}, - { 0x00184ef8, 7}, - { 0x00184f20, 2}, - { 0x00185040, 41}, - { 0x001850ec, 1}, - { 0x001850f8, 7}, - { 0x00185120, 2}, - { 0x00185240, 41}, - { 0x001852ec, 1}, - { 0x001852f8, 7}, - { 0x00185320, 2}, - { 0x00185440, 41}, - { 0x001854ec, 1}, - { 0x001854f8, 7}, - { 0x00185520, 2}, - { 0x00185640, 41}, - { 0x001856ec, 1}, - { 0x001856f8, 7}, - { 0x00185720, 2}, - { 0x00185840, 41}, - { 0x001858ec, 1}, - { 0x001858f8, 7}, - { 0x00185920, 2}, - { 0x00185a40, 41}, - { 0x00185aec, 1}, - { 0x00185af8, 7}, - { 0x00185b20, 2}, - { 0x00185c40, 41}, - { 0x00185cec, 1}, - { 0x00185cf8, 7}, - { 0x00185d20, 2}, - { 0x00185e40, 41}, - { 0x00185eec, 1}, - { 0x00185ef8, 7}, - { 0x00185f20, 2}, - { 0x00186040, 41}, - { 0x001860ec, 1}, - { 0x001860f8, 7}, - { 0x00186120, 2}, - { 0x00186240, 41}, - { 0x001862ec, 1}, - { 0x001862f8, 7}, - { 0x00186320, 2}, - { 0x00186440, 41}, - { 0x001864ec, 1}, - { 0x001864f8, 7}, - { 0x00186520, 2}, - { 0x00186640, 41}, - { 0x001866ec, 1}, - { 0x001866f8, 7}, - { 0x00186720, 2}, - { 0x00186840, 41}, - { 0x001868ec, 1}, - { 0x001868f8, 7}, - { 0x00186920, 2}, - { 0x00186a40, 41}, - { 0x00186aec, 1}, - { 0x00186af8, 7}, - { 0x00186b20, 2}, - { 0x00186c40, 41}, - { 0x00186cec, 1}, - { 0x00186cf8, 7}, - { 0x00186d20, 2}, - { 0x00186e40, 41}, - { 0x00186eec, 1}, - { 0x00186ef8, 7}, - { 0x00186f20, 2}, - { 0x00187040, 41}, - { 0x001870ec, 1}, - { 0x001870f8, 7}, - { 0x00187120, 2}, - { 0x00187240, 41}, - { 0x001872ec, 1}, - { 0x001872f8, 7}, - { 0x00187320, 2}, - { 0x00187440, 41}, - { 0x001874ec, 1}, - { 0x001874f8, 7}, - { 0x00187520, 2}, - { 0x00187640, 41}, - { 0x001876ec, 1}, - { 0x001876f8, 7}, - { 0x00187720, 2}, - { 0x00187840, 41}, - { 0x001878ec, 1}, - { 0x001878f8, 7}, - { 0x00187920, 2}, - { 0x00187a40, 41}, - { 0x00187aec, 1}, - { 0x00187af8, 7}, - { 0x00187b20, 2}, - { 0x00187c40, 41}, - { 0x00187cec, 1}, - { 0x00187cf8, 7}, - { 0x00187d20, 2}, - { 0x00187e40, 41}, - { 0x00187eec, 1}, - { 0x00187ef8, 7}, - { 0x00187f20, 2}, - { 0x00188040, 41}, - { 0x001880ec, 1}, - { 0x001880f8, 7}, - { 0x00188120, 2}, - { 0x00188240, 41}, - { 0x001882ec, 1}, - { 0x001882f8, 7}, - { 0x00188320, 2}, - { 0x00188440, 41}, - { 0x001884ec, 1}, - { 0x001884f8, 7}, - { 0x00188520, 2}, - { 0x00188640, 41}, - { 0x001886ec, 1}, - { 0x001886f8, 7}, - { 0x00188720, 2}, - { 0x00188840, 41}, - { 0x001888ec, 1}, - { 0x001888f8, 7}, - { 0x00188920, 2}, - { 0x00188a40, 41}, - { 0x00188aec, 1}, - { 0x00188af8, 7}, - { 0x00188b20, 2}, - { 0x00188c40, 41}, - { 0x00188cec, 1}, - { 0x00188cf8, 7}, - { 0x00188d20, 2}, - { 0x00188e40, 41}, - { 0x00188eec, 1}, - { 0x00188ef8, 7}, - { 0x00188f20, 2}, - { 0x00189040, 41}, - { 0x001890ec, 1}, - { 0x001890f8, 7}, - { 0x00189120, 2}, - { 0x00189240, 41}, - { 0x001892ec, 1}, - { 0x001892f8, 7}, - { 0x00189320, 2}, - { 0x00189440, 41}, - { 0x001894ec, 1}, - { 0x001894f8, 7}, - { 0x00189520, 2}, - { 0x00189640, 41}, - { 0x001896ec, 1}, - { 0x001896f8, 7}, - { 0x00189720, 2}, - { 0x00189840, 41}, - { 0x001898ec, 1}, - { 0x001898f8, 7}, - { 0x00189920, 2}, - { 0x00189a40, 41}, - { 0x00189aec, 1}, - { 0x00189af8, 7}, - { 0x00189b20, 2}, - { 0x00189c40, 41}, - { 0x00189cec, 1}, - { 0x00189cf8, 7}, - { 0x00189d20, 2}, - { 0x00189e40, 41}, - { 0x00189eec, 1}, - { 0x00189ef8, 7}, - { 0x00189f20, 2}, - { 0x0018a040, 41}, - { 0x0018a0ec, 1}, - { 0x0018a0f8, 7}, - { 0x0018a120, 2}, - { 0x0018a240, 41}, - { 0x0018a2ec, 1}, - { 0x0018a2f8, 7}, - { 0x0018a320, 2}, - { 0x0018a440, 41}, - { 0x0018a4ec, 1}, - { 0x0018a4f8, 7}, - { 0x0018a520, 2}, - { 0x0018a640, 41}, - { 0x0018a6ec, 1}, - { 0x0018a6f8, 7}, - { 0x0018a720, 2}, - { 0x0018a840, 41}, - { 0x0018a8ec, 1}, - { 0x0018a8f8, 7}, - { 0x0018a920, 2}, - { 0x0018aa40, 41}, - { 0x0018aaec, 1}, - { 0x0018aaf8, 7}, - { 0x0018ab20, 2}, - { 0x0018ac40, 41}, - { 0x0018acec, 1}, - { 0x0018acf8, 7}, - { 0x0018ad20, 2}, - { 0x0018ae40, 41}, - { 0x0018aeec, 1}, - { 0x0018aef8, 7}, - { 0x0018af20, 2}, - { 0x0018b040, 41}, - { 0x0018b0ec, 1}, - { 0x0018b0f8, 7}, - { 0x0018b120, 2}, - { 0x0018b240, 41}, - { 0x0018b2ec, 1}, - { 0x0018b2f8, 7}, - { 0x0018b320, 2}, - { 0x0018b440, 41}, - { 0x0018b4ec, 1}, - { 0x0018b4f8, 7}, - { 0x0018b520, 2}, - { 0x0018b640, 41}, - { 0x0018b6ec, 1}, - { 0x0018b6f8, 7}, - { 0x0018b720, 2}, - { 0x0018b840, 41}, - { 0x0018b8ec, 1}, - { 0x0018b8f8, 7}, - { 0x0018b920, 2}, - { 0x0018ba40, 41}, - { 0x0018baec, 1}, - { 0x0018baf8, 7}, - { 0x0018bb20, 2}, - { 0x0018bc40, 41}, - { 0x0018bcec, 1}, - { 0x0018bcf8, 7}, - { 0x0018bd20, 2}, - { 0x0018be40, 41}, - { 0x0018beec, 1}, - { 0x0018bef8, 7}, - { 0x0018bf20, 2}, - { 0x0018c040, 41}, - { 0x0018c0ec, 1}, - { 0x0018c0f8, 7}, - { 0x0018c120, 2}, - { 0x0018c240, 41}, - { 0x0018c2ec, 1}, - { 0x0018c2f8, 7}, - { 0x0018c320, 2}, - { 0x0018c440, 41}, - { 0x0018c4ec, 1}, - { 0x0018c4f8, 7}, - { 0x0018c520, 2}, - { 0x0018c640, 41}, - { 0x0018c6ec, 1}, - { 0x0018c6f8, 7}, - { 0x0018c720, 2}, - { 0x0018c840, 41}, - { 0x0018c8ec, 1}, - { 0x0018c8f8, 7}, - { 0x0018c920, 2}, - { 0x0018ca40, 41}, - { 0x0018caec, 1}, - { 0x0018caf8, 7}, - { 0x0018cb20, 2}, - { 0x0018cc40, 41}, - { 0x0018ccec, 1}, - { 0x0018ccf8, 7}, - { 0x0018cd20, 2}, - { 0x0018ce40, 41}, - { 0x0018ceec, 1}, - { 0x0018cef8, 7}, - { 0x0018cf20, 2}, - { 0x0018d040, 41}, - { 0x0018d0ec, 1}, - { 0x0018d0f8, 7}, - { 0x0018d120, 2}, - { 0x0018d240, 41}, - { 0x0018d2ec, 1}, - { 0x0018d2f8, 7}, - { 0x0018d320, 2}, - { 0x0018d440, 41}, - { 0x0018d4ec, 1}, - { 0x0018d4f8, 7}, - { 0x0018d520, 2}, - { 0x0018d640, 41}, - { 0x0018d6ec, 1}, - { 0x0018d6f8, 7}, - { 0x0018d720, 2}, - { 0x0018d840, 41}, - { 0x0018d8ec, 1}, - { 0x0018d8f8, 7}, - { 0x0018d920, 2}, - { 0x0018da40, 41}, - { 0x0018daec, 1}, - { 0x0018daf8, 7}, - { 0x0018db20, 2}, - { 0x0018dc40, 41}, - { 0x0018dcec, 1}, - { 0x0018dcf8, 7}, - { 0x0018dd20, 2}, - { 0x0018de40, 41}, - { 0x0018deec, 1}, - { 0x0018def8, 7}, - { 0x0018df20, 2}, - { 0x0018e040, 41}, - { 0x0018e0ec, 1}, - { 0x0018e0f8, 7}, - { 0x0018e120, 2}, - { 0x0018e240, 41}, - { 0x0018e2ec, 1}, - { 0x0018e2f8, 7}, - { 0x0018e320, 2}, - { 0x0018e440, 41}, - { 0x0018e4ec, 1}, - { 0x0018e4f8, 7}, - { 0x0018e520, 2}, - { 0x0018e640, 41}, - { 0x0018e6ec, 1}, - { 0x0018e6f8, 7}, - { 0x0018e720, 2}, - { 0x0018e840, 41}, - { 0x0018e8ec, 1}, - { 0x0018e8f8, 7}, - { 0x0018e920, 2}, - { 0x0018ea40, 41}, - { 0x0018eaec, 1}, - { 0x0018eaf8, 7}, - { 0x0018eb20, 2}, - { 0x0018ec40, 41}, - { 0x0018ecec, 1}, - { 0x0018ecf8, 7}, - { 0x0018ed20, 2}, - { 0x0018ee40, 41}, - { 0x0018eeec, 1}, - { 0x0018eef8, 7}, - { 0x0018ef20, 2}, - { 0x0018f040, 41}, - { 0x0018f0ec, 1}, - { 0x0018f0f8, 7}, - { 0x0018f120, 2}, - { 0x0018f240, 41}, - { 0x0018f2ec, 1}, - { 0x0018f2f8, 7}, - { 0x0018f320, 2}, - { 0x0018f440, 41}, - { 0x0018f4ec, 1}, - { 0x0018f4f8, 7}, - { 0x0018f520, 2}, - { 0x0018f640, 41}, - { 0x0018f6ec, 1}, - { 0x0018f6f8, 7}, - { 0x0018f720, 2}, - { 0x0018f840, 41}, - { 0x0018f8ec, 1}, - { 0x0018f8f8, 7}, - { 0x0018f920, 2}, - { 0x0018fa40, 41}, - { 0x0018faec, 1}, - { 0x0018faf8, 7}, - { 0x0018fb20, 2}, - { 0x0018fc40, 41}, - { 0x0018fcec, 1}, - { 0x0018fcf8, 7}, - { 0x0018fd20, 2}, - { 0x0018fe40, 41}, - { 0x0018feec, 1}, - { 0x0018fef8, 7}, - { 0x0018ff20, 2}, - { 0x00190040, 41}, - { 0x001900ec, 1}, - { 0x001900f8, 7}, - { 0x00190120, 2}, - { 0x00190240, 41}, - { 0x001902ec, 1}, - { 0x001902f8, 7}, - { 0x00190320, 2}, - { 0x00190440, 41}, - { 0x001904ec, 1}, - { 0x001904f8, 7}, - { 0x00190520, 2}, - { 0x00190640, 41}, - { 0x001906ec, 1}, - { 0x001906f8, 7}, - { 0x00190720, 2}, - { 0x00190840, 41}, - { 0x001908ec, 1}, - { 0x001908f8, 7}, - { 0x00190920, 2}, - { 0x00190a40, 41}, - { 0x00190aec, 1}, - { 0x00190af8, 7}, - { 0x00190b20, 2}, - { 0x00190c40, 41}, - { 0x00190cec, 1}, - { 0x00190cf8, 7}, - { 0x00190d20, 2}, - { 0x00190e40, 41}, - { 0x00190eec, 1}, - { 0x00190ef8, 7}, - { 0x00190f20, 2}, - { 0x00191040, 41}, - { 0x001910ec, 1}, - { 0x001910f8, 7}, - { 0x00191120, 2}, - { 0x00191240, 41}, - { 0x001912ec, 1}, - { 0x001912f8, 7}, - { 0x00191320, 2}, - { 0x00191440, 41}, - { 0x001914ec, 1}, - { 0x001914f8, 7}, - { 0x00191520, 2}, - { 0x00191640, 41}, - { 0x001916ec, 1}, - { 0x001916f8, 7}, - { 0x00191720, 2}, - { 0x00191840, 41}, - { 0x001918ec, 1}, - { 0x001918f8, 7}, - { 0x00191920, 2}, - { 0x00191a40, 41}, - { 0x00191aec, 1}, - { 0x00191af8, 7}, - { 0x00191b20, 2}, - { 0x00191c40, 41}, - { 0x00191cec, 1}, - { 0x00191cf8, 7}, - { 0x00191d20, 2}, - { 0x00191e40, 41}, - { 0x00191eec, 1}, - { 0x00191ef8, 7}, - { 0x00191f20, 2}, - { 0x00192040, 41}, - { 0x001920ec, 1}, - { 0x001920f8, 7}, - { 0x00192120, 2}, - { 0x00192240, 41}, - { 0x001922ec, 1}, - { 0x001922f8, 7}, - { 0x00192320, 2}, - { 0x00192440, 41}, - { 0x001924ec, 1}, - { 0x001924f8, 7}, - { 0x00192520, 2}, - { 0x00192640, 41}, - { 0x001926ec, 1}, - { 0x001926f8, 7}, - { 0x00192720, 2}, - { 0x00192840, 41}, - { 0x001928ec, 1}, - { 0x001928f8, 7}, - { 0x00192920, 2}, - { 0x00192a40, 41}, - { 0x00192aec, 1}, - { 0x00192af8, 7}, - { 0x00192b20, 2}, - { 0x00192c40, 41}, - { 0x00192cec, 1}, - { 0x00192cf8, 7}, - { 0x00192d20, 2}, - { 0x00192e40, 41}, - { 0x00192eec, 1}, - { 0x00192ef8, 7}, - { 0x00192f20, 2}, - { 0x00193040, 41}, - { 0x001930ec, 1}, - { 0x001930f8, 7}, - { 0x00193120, 2}, - { 0x00193240, 41}, - { 0x001932ec, 1}, - { 0x001932f8, 7}, - { 0x00193320, 2}, - { 0x00193440, 41}, - { 0x001934ec, 1}, - { 0x001934f8, 7}, - { 0x00193520, 2}, - { 0x00193640, 41}, - { 0x001936ec, 1}, - { 0x001936f8, 7}, - { 0x00193720, 2}, - { 0x00193840, 41}, - { 0x001938ec, 1}, - { 0x001938f8, 7}, - { 0x00193920, 2}, - { 0x00193a40, 41}, - { 0x00193aec, 1}, - { 0x00193af8, 7}, - { 0x00193b20, 2}, - { 0x00193c40, 41}, - { 0x00193cec, 1}, - { 0x00193cf8, 7}, - { 0x00193d20, 2}, - { 0x00193e40, 41}, - { 0x00193eec, 1}, - { 0x00193ef8, 7}, - { 0x00193f20, 2}, - { 0x00194040, 41}, - { 0x001940ec, 1}, - { 0x001940f8, 7}, - { 0x00194120, 2}, - { 0x00194240, 41}, - { 0x001942ec, 1}, - { 0x001942f8, 7}, - { 0x00194320, 2}, - { 0x00194440, 41}, - { 0x001944ec, 1}, - { 0x001944f8, 7}, - { 0x00194520, 2}, - { 0x00194640, 41}, - { 0x001946ec, 1}, - { 0x001946f8, 7}, - { 0x00194720, 2}, - { 0x00194840, 41}, - { 0x001948ec, 1}, - { 0x001948f8, 7}, - { 0x00194920, 2}, - { 0x00194a40, 41}, - { 0x00194aec, 1}, - { 0x00194af8, 7}, - { 0x00194b20, 2}, - { 0x00194c40, 41}, - { 0x00194cec, 1}, - { 0x00194cf8, 7}, - { 0x00194d20, 2}, - { 0x00194e40, 41}, - { 0x00194eec, 1}, - { 0x00194ef8, 7}, - { 0x00194f20, 2}, - { 0x00195040, 41}, - { 0x001950ec, 1}, - { 0x001950f8, 7}, - { 0x00195120, 2}, - { 0x00195240, 41}, - { 0x001952ec, 1}, - { 0x001952f8, 7}, - { 0x00195320, 2}, - { 0x00195440, 41}, - { 0x001954ec, 1}, - { 0x001954f8, 7}, - { 0x00195520, 2}, - { 0x00195640, 41}, - { 0x001956ec, 1}, - { 0x001956f8, 7}, - { 0x00195720, 2}, - { 0x00195840, 41}, - { 0x001958ec, 1}, - { 0x001958f8, 7}, - { 0x00195920, 2}, - { 0x00195a40, 41}, - { 0x00195aec, 1}, - { 0x00195af8, 7}, - { 0x00195b20, 2}, - { 0x00195c40, 41}, - { 0x00195cec, 1}, - { 0x00195cf8, 7}, - { 0x00195d20, 2}, - { 0x00195e40, 41}, - { 0x00195eec, 1}, - { 0x00195ef8, 7}, - { 0x00195f20, 2}, - { 0x00196040, 41}, - { 0x001960ec, 1}, - { 0x001960f8, 7}, - { 0x00196120, 2}, - { 0x00196240, 41}, - { 0x001962ec, 1}, - { 0x001962f8, 7}, - { 0x00196320, 2}, - { 0x00196440, 41}, - { 0x001964ec, 1}, - { 0x001964f8, 7}, - { 0x00196520, 2}, - { 0x00196640, 41}, - { 0x001966ec, 1}, - { 0x001966f8, 7}, - { 0x00196720, 2}, - { 0x00196840, 41}, - { 0x001968ec, 1}, - { 0x001968f8, 7}, - { 0x00196920, 2}, - { 0x00196a40, 41}, - { 0x00196aec, 1}, - { 0x00196af8, 7}, - { 0x00196b20, 2}, - { 0x00196c40, 41}, - { 0x00196cec, 1}, - { 0x00196cf8, 7}, - { 0x00196d20, 2}, - { 0x00196e40, 41}, - { 0x00196eec, 1}, - { 0x00196ef8, 7}, - { 0x00196f20, 2}, - { 0x00197040, 41}, - { 0x001970ec, 1}, - { 0x001970f8, 7}, - { 0x00197120, 2}, - { 0x00197240, 41}, - { 0x001972ec, 1}, - { 0x001972f8, 7}, - { 0x00197320, 2}, - { 0x00197440, 41}, - { 0x001974ec, 1}, - { 0x001974f8, 7}, - { 0x00197520, 2}, - { 0x00197640, 41}, - { 0x001976ec, 1}, - { 0x001976f8, 7}, - { 0x00197720, 2}, - { 0x00197840, 41}, - { 0x001978ec, 1}, - { 0x001978f8, 7}, - { 0x00197920, 2}, - { 0x00197a40, 41}, - { 0x00197aec, 1}, - { 0x00197af8, 7}, - { 0x00197b20, 2}, - { 0x00197c40, 41}, - { 0x00197cec, 1}, - { 0x00197cf8, 7}, - { 0x00197d20, 2}, - { 0x00197e40, 41}, - { 0x00197eec, 1}, - { 0x00197ef8, 7}, - { 0x00197f20, 2}, - { 0x001c80a8, 1}, - { 0x001c9100, 1}, - { 0x001cc0a8, 1}, - { 0x001cd100, 1}, - { 0x001fb000, 1}, - { 0x001fb400, 1}, - { 0x00200040, 41}, - { 0x002000ec, 1}, - { 0x002000f8, 7}, - { 0x00200120, 2}, - { 0x00200240, 41}, - { 0x002002ec, 1}, - { 0x002002f8, 7}, - { 0x00200320, 2}, - { 0x00200440, 41}, - { 0x002004ec, 1}, - { 0x002004f8, 7}, - { 0x00200520, 2}, - { 0x00200640, 41}, - { 0x002006ec, 1}, - { 0x002006f8, 7}, - { 0x00200720, 2}, - { 0x00200840, 41}, - { 0x002008ec, 1}, - { 0x002008f8, 7}, - { 0x00200920, 2}, - { 0x00200a40, 41}, - { 0x00200aec, 1}, - { 0x00200af8, 7}, - { 0x00200b20, 2}, - { 0x00200c40, 41}, - { 0x00200cec, 1}, - { 0x00200cf8, 7}, - { 0x00200d20, 2}, - { 0x00200e40, 41}, - { 0x00200eec, 1}, - { 0x00200ef8, 7}, - { 0x00200f20, 2}, - { 0x00201040, 41}, - { 0x002010ec, 1}, - { 0x002010f8, 7}, - { 0x00201120, 2}, - { 0x00201240, 41}, - { 0x002012ec, 1}, - { 0x002012f8, 7}, - { 0x00201320, 2}, - { 0x00201440, 41}, - { 0x002014ec, 1}, - { 0x002014f8, 7}, - { 0x00201520, 2}, - { 0x00201640, 41}, - { 0x002016ec, 1}, - { 0x002016f8, 7}, - { 0x00201720, 2}, - { 0x00201840, 41}, - { 0x002018ec, 1}, - { 0x002018f8, 7}, - { 0x00201920, 2}, - { 0x00201a40, 41}, - { 0x00201aec, 1}, - { 0x00201af8, 7}, - { 0x00201b20, 2}, - { 0x00201c40, 41}, - { 0x00201cec, 1}, - { 0x00201cf8, 7}, - { 0x00201d20, 2}, - { 0x00201e40, 41}, - { 0x00201eec, 1}, - { 0x00201ef8, 7}, - { 0x00201f20, 2}, - { 0x00202040, 41}, - { 0x002020ec, 1}, - { 0x002020f8, 7}, - { 0x00202120, 2}, - { 0x00202240, 41}, - { 0x002022ec, 1}, - { 0x002022f8, 7}, - { 0x00202320, 2}, - { 0x00202440, 41}, - { 0x002024ec, 1}, - { 0x002024f8, 7}, - { 0x00202520, 2}, - { 0x00202640, 41}, - { 0x002026ec, 1}, - { 0x002026f8, 7}, - { 0x00202720, 2}, - { 0x00202840, 41}, - { 0x002028ec, 1}, - { 0x002028f8, 7}, - { 0x00202920, 2}, - { 0x00202a40, 41}, - { 0x00202aec, 1}, - { 0x00202af8, 7}, - { 0x00202b20, 2}, - { 0x00202c40, 41}, - { 0x00202cec, 1}, - { 0x00202cf8, 7}, - { 0x00202d20, 2}, - { 0x00202e40, 41}, - { 0x00202eec, 1}, - { 0x00202ef8, 7}, - { 0x00202f20, 2}, - { 0x00203040, 41}, - { 0x002030ec, 1}, - { 0x002030f8, 7}, - { 0x00203120, 2}, - { 0x00203240, 41}, - { 0x002032ec, 1}, - { 0x002032f8, 7}, - { 0x00203320, 2}, - { 0x00203440, 41}, - { 0x002034ec, 1}, - { 0x002034f8, 7}, - { 0x00203520, 2}, - { 0x00203640, 41}, - { 0x002036ec, 1}, - { 0x002036f8, 7}, - { 0x00203720, 2}, - { 0x00203840, 41}, - { 0x002038ec, 1}, - { 0x002038f8, 7}, - { 0x00203920, 2}, - { 0x00203a40, 41}, - { 0x00203aec, 1}, - { 0x00203af8, 7}, - { 0x00203b20, 2}, - { 0x00203c40, 41}, - { 0x00203cec, 1}, - { 0x00203cf8, 7}, - { 0x00203d20, 2}, - { 0x00203e40, 41}, - { 0x00203eec, 1}, - { 0x00203ef8, 7}, - { 0x00203f20, 2}, - { 0x00204040, 41}, - { 0x002040ec, 1}, - { 0x002040f8, 7}, - { 0x00204120, 2}, - { 0x00204240, 41}, - { 0x002042ec, 1}, - { 0x002042f8, 7}, - { 0x00204320, 2}, - { 0x00204440, 41}, - { 0x002044ec, 1}, - { 0x002044f8, 7}, - { 0x00204520, 2}, - { 0x00204640, 41}, - { 0x002046ec, 1}, - { 0x002046f8, 7}, - { 0x00204720, 2}, - { 0x00204840, 41}, - { 0x002048ec, 1}, - { 0x002048f8, 7}, - { 0x00204920, 2}, - { 0x00204a40, 41}, - { 0x00204aec, 1}, - { 0x00204af8, 7}, - { 0x00204b20, 2}, - { 0x00204c40, 41}, - { 0x00204cec, 1}, - { 0x00204cf8, 7}, - { 0x00204d20, 2}, - { 0x00204e40, 41}, - { 0x00204eec, 1}, - { 0x00204ef8, 7}, - { 0x00204f20, 2}, - { 0x00205040, 41}, - { 0x002050ec, 1}, - { 0x002050f8, 7}, - { 0x00205120, 2}, - { 0x00205240, 41}, - { 0x002052ec, 1}, - { 0x002052f8, 7}, - { 0x00205320, 2}, - { 0x00205440, 41}, - { 0x002054ec, 1}, - { 0x002054f8, 7}, - { 0x00205520, 2}, - { 0x00205640, 41}, - { 0x002056ec, 1}, - { 0x002056f8, 7}, - { 0x00205720, 2}, - { 0x00205840, 41}, - { 0x002058ec, 1}, - { 0x002058f8, 7}, - { 0x00205920, 2}, - { 0x00205a40, 41}, - { 0x00205aec, 1}, - { 0x00205af8, 7}, - { 0x00205b20, 2}, - { 0x00205c40, 41}, - { 0x00205cec, 1}, - { 0x00205cf8, 7}, - { 0x00205d20, 2}, - { 0x00205e40, 41}, - { 0x00205eec, 1}, - { 0x00205ef8, 7}, - { 0x00205f20, 2}, - { 0x00206040, 41}, - { 0x002060ec, 1}, - { 0x002060f8, 7}, - { 0x00206120, 2}, - { 0x00206240, 41}, - { 0x002062ec, 1}, - { 0x002062f8, 7}, - { 0x00206320, 2}, - { 0x00206440, 41}, - { 0x002064ec, 1}, - { 0x002064f8, 7}, - { 0x00206520, 2}, - { 0x00206640, 41}, - { 0x002066ec, 1}, - { 0x002066f8, 7}, - { 0x00206720, 2}, - { 0x00206840, 41}, - { 0x002068ec, 1}, - { 0x002068f8, 7}, - { 0x00206920, 2}, - { 0x00206a40, 41}, - { 0x00206aec, 1}, - { 0x00206af8, 7}, - { 0x00206b20, 2}, - { 0x00206c40, 41}, - { 0x00206cec, 1}, - { 0x00206cf8, 7}, - { 0x00206d20, 2}, - { 0x00206e40, 41}, - { 0x00206eec, 1}, - { 0x00206ef8, 7}, - { 0x00206f20, 2}, - { 0x00207040, 41}, - { 0x002070ec, 1}, - { 0x002070f8, 7}, - { 0x00207120, 2}, - { 0x00207240, 41}, - { 0x002072ec, 1}, - { 0x002072f8, 7}, - { 0x00207320, 2}, - { 0x00207440, 41}, - { 0x002074ec, 1}, - { 0x002074f8, 7}, - { 0x00207520, 2}, - { 0x00207640, 41}, - { 0x002076ec, 1}, - { 0x002076f8, 7}, - { 0x00207720, 2}, - { 0x00207840, 41}, - { 0x002078ec, 1}, - { 0x002078f8, 7}, - { 0x00207920, 2}, - { 0x00207a40, 41}, - { 0x00207aec, 1}, - { 0x00207af8, 7}, - { 0x00207b20, 2}, - { 0x00207c40, 41}, - { 0x00207cec, 1}, - { 0x00207cf8, 7}, - { 0x00207d20, 2}, - { 0x00207e40, 41}, - { 0x00207eec, 1}, - { 0x00207ef8, 7}, - { 0x00207f20, 2}, - { 0x00208040, 41}, - { 0x002080ec, 1}, - { 0x002080f8, 7}, - { 0x00208120, 2}, - { 0x00208240, 41}, - { 0x002082ec, 1}, - { 0x002082f8, 7}, - { 0x00208320, 2}, - { 0x00208440, 41}, - { 0x002084ec, 1}, - { 0x002084f8, 7}, - { 0x00208520, 2}, - { 0x00208640, 41}, - { 0x002086ec, 1}, - { 0x002086f8, 7}, - { 0x00208720, 2}, - { 0x00208840, 41}, - { 0x002088ec, 1}, - { 0x002088f8, 7}, - { 0x00208920, 2}, - { 0x00208a40, 41}, - { 0x00208aec, 1}, - { 0x00208af8, 7}, - { 0x00208b20, 2}, - { 0x00208c40, 41}, - { 0x00208cec, 1}, - { 0x00208cf8, 7}, - { 0x00208d20, 2}, - { 0x00208e40, 41}, - { 0x00208eec, 1}, - { 0x00208ef8, 7}, - { 0x00208f20, 2}, - { 0x00209040, 41}, - { 0x002090ec, 1}, - { 0x002090f8, 7}, - { 0x00209120, 2}, - { 0x00209240, 41}, - { 0x002092ec, 1}, - { 0x002092f8, 7}, - { 0x00209320, 2}, - { 0x00209440, 41}, - { 0x002094ec, 1}, - { 0x002094f8, 7}, - { 0x00209520, 2}, - { 0x00209640, 41}, - { 0x002096ec, 1}, - { 0x002096f8, 7}, - { 0x00209720, 2}, - { 0x00209840, 41}, - { 0x002098ec, 1}, - { 0x002098f8, 7}, - { 0x00209920, 2}, - { 0x00209a40, 41}, - { 0x00209aec, 1}, - { 0x00209af8, 7}, - { 0x00209b20, 2}, - { 0x00209c40, 41}, - { 0x00209cec, 1}, - { 0x00209cf8, 7}, - { 0x00209d20, 2}, - { 0x00209e40, 41}, - { 0x00209eec, 1}, - { 0x00209ef8, 7}, - { 0x00209f20, 2}, - { 0x0020a040, 41}, - { 0x0020a0ec, 1}, - { 0x0020a0f8, 7}, - { 0x0020a120, 2}, - { 0x0020a240, 41}, - { 0x0020a2ec, 1}, - { 0x0020a2f8, 7}, - { 0x0020a320, 2}, - { 0x0020a440, 41}, - { 0x0020a4ec, 1}, - { 0x0020a4f8, 7}, - { 0x0020a520, 2}, - { 0x0020a640, 41}, - { 0x0020a6ec, 1}, - { 0x0020a6f8, 7}, - { 0x0020a720, 2}, - { 0x0020a840, 41}, - { 0x0020a8ec, 1}, - { 0x0020a8f8, 7}, - { 0x0020a920, 2}, - { 0x0020aa40, 41}, - { 0x0020aaec, 1}, - { 0x0020aaf8, 7}, - { 0x0020ab20, 2}, - { 0x0020ac40, 41}, - { 0x0020acec, 1}, - { 0x0020acf8, 7}, - { 0x0020ad20, 2}, - { 0x0020ae40, 41}, - { 0x0020aeec, 1}, - { 0x0020aef8, 7}, - { 0x0020af20, 2}, - { 0x0020b040, 41}, - { 0x0020b0ec, 1}, - { 0x0020b0f8, 7}, - { 0x0020b120, 2}, - { 0x0020b240, 41}, - { 0x0020b2ec, 1}, - { 0x0020b2f8, 7}, - { 0x0020b320, 2}, - { 0x0020b440, 41}, - { 0x0020b4ec, 1}, - { 0x0020b4f8, 7}, - { 0x0020b520, 2}, - { 0x0020b640, 41}, - { 0x0020b6ec, 1}, - { 0x0020b6f8, 7}, - { 0x0020b720, 2}, - { 0x0020b840, 41}, - { 0x0020b8ec, 1}, - { 0x0020b8f8, 7}, - { 0x0020b920, 2}, - { 0x0020ba40, 41}, - { 0x0020baec, 1}, - { 0x0020baf8, 7}, - { 0x0020bb20, 2}, - { 0x0020bc40, 41}, - { 0x0020bcec, 1}, - { 0x0020bcf8, 7}, - { 0x0020bd20, 2}, - { 0x0020be40, 41}, - { 0x0020beec, 1}, - { 0x0020bef8, 7}, - { 0x0020bf20, 2}, - { 0x0020c040, 41}, - { 0x0020c0ec, 1}, - { 0x0020c0f8, 7}, - { 0x0020c120, 2}, - { 0x0020c240, 41}, - { 0x0020c2ec, 1}, - { 0x0020c2f8, 7}, - { 0x0020c320, 2}, - { 0x0020c440, 41}, - { 0x0020c4ec, 1}, - { 0x0020c4f8, 7}, - { 0x0020c520, 2}, - { 0x0020c640, 41}, - { 0x0020c6ec, 1}, - { 0x0020c6f8, 7}, - { 0x0020c720, 2}, - { 0x0020c840, 41}, - { 0x0020c8ec, 1}, - { 0x0020c8f8, 7}, - { 0x0020c920, 2}, - { 0x0020ca40, 41}, - { 0x0020caec, 1}, - { 0x0020caf8, 7}, - { 0x0020cb20, 2}, - { 0x0020cc40, 41}, - { 0x0020ccec, 1}, - { 0x0020ccf8, 7}, - { 0x0020cd20, 2}, - { 0x0020ce40, 41}, - { 0x0020ceec, 1}, - { 0x0020cef8, 7}, - { 0x0020cf20, 2}, - { 0x0020d040, 41}, - { 0x0020d0ec, 1}, - { 0x0020d0f8, 7}, - { 0x0020d120, 2}, - { 0x0020d240, 41}, - { 0x0020d2ec, 1}, - { 0x0020d2f8, 7}, - { 0x0020d320, 2}, - { 0x0020d440, 41}, - { 0x0020d4ec, 1}, - { 0x0020d4f8, 7}, - { 0x0020d520, 2}, - { 0x0020d640, 41}, - { 0x0020d6ec, 1}, - { 0x0020d6f8, 7}, - { 0x0020d720, 2}, - { 0x0020d840, 41}, - { 0x0020d8ec, 1}, - { 0x0020d8f8, 7}, - { 0x0020d920, 2}, - { 0x0020da40, 41}, - { 0x0020daec, 1}, - { 0x0020daf8, 7}, - { 0x0020db20, 2}, - { 0x0020dc40, 41}, - { 0x0020dcec, 1}, - { 0x0020dcf8, 7}, - { 0x0020dd20, 2}, - { 0x0020de40, 41}, - { 0x0020deec, 1}, - { 0x0020def8, 7}, - { 0x0020df20, 2}, - { 0x0020e040, 41}, - { 0x0020e0ec, 1}, - { 0x0020e0f8, 7}, - { 0x0020e120, 2}, - { 0x0020e240, 41}, - { 0x0020e2ec, 1}, - { 0x0020e2f8, 7}, - { 0x0020e320, 2}, - { 0x0020e440, 41}, - { 0x0020e4ec, 1}, - { 0x0020e4f8, 7}, - { 0x0020e520, 2}, - { 0x0020e640, 41}, - { 0x0020e6ec, 1}, - { 0x0020e6f8, 7}, - { 0x0020e720, 2}, - { 0x0020e840, 41}, - { 0x0020e8ec, 1}, - { 0x0020e8f8, 7}, - { 0x0020e920, 2}, - { 0x0020ea40, 41}, - { 0x0020eaec, 1}, - { 0x0020eaf8, 7}, - { 0x0020eb20, 2}, - { 0x0020ec40, 41}, - { 0x0020ecec, 1}, - { 0x0020ecf8, 7}, - { 0x0020ed20, 2}, - { 0x0020ee40, 41}, - { 0x0020eeec, 1}, - { 0x0020eef8, 7}, - { 0x0020ef20, 2}, - { 0x0020f040, 41}, - { 0x0020f0ec, 1}, - { 0x0020f0f8, 7}, - { 0x0020f120, 2}, - { 0x0020f240, 41}, - { 0x0020f2ec, 1}, - { 0x0020f2f8, 7}, - { 0x0020f320, 2}, - { 0x0020f440, 41}, - { 0x0020f4ec, 1}, - { 0x0020f4f8, 7}, - { 0x0020f520, 2}, - { 0x0020f640, 41}, - { 0x0020f6ec, 1}, - { 0x0020f6f8, 7}, - { 0x0020f720, 2}, - { 0x0020f840, 41}, - { 0x0020f8ec, 1}, - { 0x0020f8f8, 7}, - { 0x0020f920, 2}, - { 0x0020fa40, 41}, - { 0x0020faec, 1}, - { 0x0020faf8, 7}, - { 0x0020fb20, 2}, - { 0x0020fc40, 41}, - { 0x0020fcec, 1}, - { 0x0020fcf8, 7}, - { 0x0020fd20, 2}, - { 0x0020fe40, 41}, - { 0x0020feec, 1}, - { 0x0020fef8, 7}, - { 0x0020ff20, 2}, - { 0x00210040, 41}, - { 0x002100ec, 1}, - { 0x002100f8, 7}, - { 0x00210120, 2}, - { 0x00210240, 41}, - { 0x002102ec, 1}, - { 0x002102f8, 7}, - { 0x00210320, 2}, - { 0x00210440, 41}, - { 0x002104ec, 1}, - { 0x002104f8, 7}, - { 0x00210520, 2}, - { 0x00210640, 41}, - { 0x002106ec, 1}, - { 0x002106f8, 7}, - { 0x00210720, 2}, - { 0x00210840, 41}, - { 0x002108ec, 1}, - { 0x002108f8, 7}, - { 0x00210920, 2}, - { 0x00210a40, 41}, - { 0x00210aec, 1}, - { 0x00210af8, 7}, - { 0x00210b20, 2}, - { 0x00210c40, 41}, - { 0x00210cec, 1}, - { 0x00210cf8, 7}, - { 0x00210d20, 2}, - { 0x00210e40, 41}, - { 0x00210eec, 1}, - { 0x00210ef8, 7}, - { 0x00210f20, 2}, - { 0x00211040, 41}, - { 0x002110ec, 1}, - { 0x002110f8, 7}, - { 0x00211120, 2}, - { 0x00211240, 41}, - { 0x002112ec, 1}, - { 0x002112f8, 7}, - { 0x00211320, 2}, - { 0x00211440, 41}, - { 0x002114ec, 1}, - { 0x002114f8, 7}, - { 0x00211520, 2}, - { 0x00211640, 41}, - { 0x002116ec, 1}, - { 0x002116f8, 7}, - { 0x00211720, 2}, - { 0x00211840, 41}, - { 0x002118ec, 1}, - { 0x002118f8, 7}, - { 0x00211920, 2}, - { 0x00211a40, 41}, - { 0x00211aec, 1}, - { 0x00211af8, 7}, - { 0x00211b20, 2}, - { 0x00211c40, 41}, - { 0x00211cec, 1}, - { 0x00211cf8, 7}, - { 0x00211d20, 2}, - { 0x00211e40, 41}, - { 0x00211eec, 1}, - { 0x00211ef8, 7}, - { 0x00211f20, 2}, - { 0x00212040, 41}, - { 0x002120ec, 1}, - { 0x002120f8, 7}, - { 0x00212120, 2}, - { 0x00212240, 41}, - { 0x002122ec, 1}, - { 0x002122f8, 7}, - { 0x00212320, 2}, - { 0x00212440, 41}, - { 0x002124ec, 1}, - { 0x002124f8, 7}, - { 0x00212520, 2}, - { 0x00212640, 41}, - { 0x002126ec, 1}, - { 0x002126f8, 7}, - { 0x00212720, 2}, - { 0x00212840, 41}, - { 0x002128ec, 1}, - { 0x002128f8, 7}, - { 0x00212920, 2}, - { 0x00212a40, 41}, - { 0x00212aec, 1}, - { 0x00212af8, 7}, - { 0x00212b20, 2}, - { 0x00212c40, 41}, - { 0x00212cec, 1}, - { 0x00212cf8, 7}, - { 0x00212d20, 2}, - { 0x00212e40, 41}, - { 0x00212eec, 1}, - { 0x00212ef8, 7}, - { 0x00212f20, 2}, - { 0x00213040, 41}, - { 0x002130ec, 1}, - { 0x002130f8, 7}, - { 0x00213120, 2}, - { 0x00213240, 41}, - { 0x002132ec, 1}, - { 0x002132f8, 7}, - { 0x00213320, 2}, - { 0x00213440, 41}, - { 0x002134ec, 1}, - { 0x002134f8, 7}, - { 0x00213520, 2}, - { 0x00213640, 41}, - { 0x002136ec, 1}, - { 0x002136f8, 7}, - { 0x00213720, 2}, - { 0x00213840, 41}, - { 0x002138ec, 1}, - { 0x002138f8, 7}, - { 0x00213920, 2}, - { 0x00213a40, 41}, - { 0x00213aec, 1}, - { 0x00213af8, 7}, - { 0x00213b20, 2}, - { 0x00213c40, 41}, - { 0x00213cec, 1}, - { 0x00213cf8, 7}, - { 0x00213d20, 2}, - { 0x00213e40, 41}, - { 0x00213eec, 1}, - { 0x00213ef8, 7}, - { 0x00213f20, 2}, - { 0x00214040, 41}, - { 0x002140ec, 1}, - { 0x002140f8, 7}, - { 0x00214120, 2}, - { 0x00214240, 41}, - { 0x002142ec, 1}, - { 0x002142f8, 7}, - { 0x00214320, 2}, - { 0x00214440, 41}, - { 0x002144ec, 1}, - { 0x002144f8, 7}, - { 0x00214520, 2}, - { 0x00214640, 41}, - { 0x002146ec, 1}, - { 0x002146f8, 7}, - { 0x00214720, 2}, - { 0x00214840, 41}, - { 0x002148ec, 1}, - { 0x002148f8, 7}, - { 0x00214920, 2}, - { 0x00214a40, 41}, - { 0x00214aec, 1}, - { 0x00214af8, 7}, - { 0x00214b20, 2}, - { 0x00214c40, 41}, - { 0x00214cec, 1}, - { 0x00214cf8, 7}, - { 0x00214d20, 2}, - { 0x00214e40, 41}, - { 0x00214eec, 1}, - { 0x00214ef8, 7}, - { 0x00214f20, 2}, - { 0x00215040, 41}, - { 0x002150ec, 1}, - { 0x002150f8, 7}, - { 0x00215120, 2}, - { 0x00215240, 41}, - { 0x002152ec, 1}, - { 0x002152f8, 7}, - { 0x00215320, 2}, - { 0x00215440, 41}, - { 0x002154ec, 1}, - { 0x002154f8, 7}, - { 0x00215520, 2}, - { 0x00215640, 41}, - { 0x002156ec, 1}, - { 0x002156f8, 7}, - { 0x00215720, 2}, - { 0x00215840, 41}, - { 0x002158ec, 1}, - { 0x002158f8, 7}, - { 0x00215920, 2}, - { 0x00215a40, 41}, - { 0x00215aec, 1}, - { 0x00215af8, 7}, - { 0x00215b20, 2}, - { 0x00215c40, 41}, - { 0x00215cec, 1}, - { 0x00215cf8, 7}, - { 0x00215d20, 2}, - { 0x00215e40, 41}, - { 0x00215eec, 1}, - { 0x00215ef8, 7}, - { 0x00215f20, 2}, - { 0x00216040, 41}, - { 0x002160ec, 1}, - { 0x002160f8, 7}, - { 0x00216120, 2}, - { 0x00216240, 41}, - { 0x002162ec, 1}, - { 0x002162f8, 7}, - { 0x00216320, 2}, - { 0x00216440, 41}, - { 0x002164ec, 1}, - { 0x002164f8, 7}, - { 0x00216520, 2}, - { 0x00216640, 41}, - { 0x002166ec, 1}, - { 0x002166f8, 7}, - { 0x00216720, 2}, - { 0x00216840, 41}, - { 0x002168ec, 1}, - { 0x002168f8, 7}, - { 0x00216920, 2}, - { 0x00216a40, 41}, - { 0x00216aec, 1}, - { 0x00216af8, 7}, - { 0x00216b20, 2}, - { 0x00216c40, 41}, - { 0x00216cec, 1}, - { 0x00216cf8, 7}, - { 0x00216d20, 2}, - { 0x00216e40, 41}, - { 0x00216eec, 1}, - { 0x00216ef8, 7}, - { 0x00216f20, 2}, - { 0x00217040, 41}, - { 0x002170ec, 1}, - { 0x002170f8, 7}, - { 0x00217120, 2}, - { 0x00217240, 41}, - { 0x002172ec, 1}, - { 0x002172f8, 7}, - { 0x00217320, 2}, - { 0x00217440, 41}, - { 0x002174ec, 1}, - { 0x002174f8, 7}, - { 0x00217520, 2}, - { 0x00217640, 41}, - { 0x002176ec, 1}, - { 0x002176f8, 7}, - { 0x00217720, 2}, - { 0x00217840, 41}, - { 0x002178ec, 1}, - { 0x002178f8, 7}, - { 0x00217920, 2}, - { 0x00217a40, 41}, - { 0x00217aec, 1}, - { 0x00217af8, 7}, - { 0x00217b20, 2}, - { 0x00217c40, 41}, - { 0x00217cec, 1}, - { 0x00217cf8, 7}, - { 0x00217d20, 2}, - { 0x00217e40, 41}, - { 0x00217eec, 1}, - { 0x00217ef8, 7}, - { 0x00217f20, 2}, - { 0x00218040, 41}, - { 0x002180ec, 1}, - { 0x002180f8, 7}, - { 0x00218120, 2}, - { 0x00218240, 41}, - { 0x002182ec, 1}, - { 0x002182f8, 7}, - { 0x00218320, 2}, - { 0x00218440, 41}, - { 0x002184ec, 1}, - { 0x002184f8, 7}, - { 0x00218520, 2}, - { 0x00218640, 41}, - { 0x002186ec, 1}, - { 0x002186f8, 7}, - { 0x00218720, 2}, - { 0x00218840, 41}, - { 0x002188ec, 1}, - { 0x002188f8, 7}, - { 0x00218920, 2}, - { 0x00218a40, 41}, - { 0x00218aec, 1}, - { 0x00218af8, 7}, - { 0x00218b20, 2}, - { 0x00218c40, 41}, - { 0x00218cec, 1}, - { 0x00218cf8, 7}, - { 0x00218d20, 2}, - { 0x00218e40, 41}, - { 0x00218eec, 1}, - { 0x00218ef8, 7}, - { 0x00218f20, 2}, - { 0x00219040, 41}, - { 0x002190ec, 1}, - { 0x002190f8, 7}, - { 0x00219120, 2}, - { 0x00219240, 41}, - { 0x002192ec, 1}, - { 0x002192f8, 7}, - { 0x00219320, 2}, - { 0x00219440, 41}, - { 0x002194ec, 1}, - { 0x002194f8, 7}, - { 0x00219520, 2}, - { 0x00219640, 41}, - { 0x002196ec, 1}, - { 0x002196f8, 7}, - { 0x00219720, 2}, - { 0x00219840, 41}, - { 0x002198ec, 1}, - { 0x002198f8, 7}, - { 0x00219920, 2}, - { 0x00219a40, 41}, - { 0x00219aec, 1}, - { 0x00219af8, 7}, - { 0x00219b20, 2}, - { 0x00219c40, 41}, - { 0x00219cec, 1}, - { 0x00219cf8, 7}, - { 0x00219d20, 2}, - { 0x00219e40, 41}, - { 0x00219eec, 1}, - { 0x00219ef8, 7}, - { 0x00219f20, 2}, - { 0x0021a040, 41}, - { 0x0021a0ec, 1}, - { 0x0021a0f8, 7}, - { 0x0021a120, 2}, - { 0x0021a240, 41}, - { 0x0021a2ec, 1}, - { 0x0021a2f8, 7}, - { 0x0021a320, 2}, - { 0x0021a440, 41}, - { 0x0021a4ec, 1}, - { 0x0021a4f8, 7}, - { 0x0021a520, 2}, - { 0x0021a640, 41}, - { 0x0021a6ec, 1}, - { 0x0021a6f8, 7}, - { 0x0021a720, 2}, - { 0x0021a840, 41}, - { 0x0021a8ec, 1}, - { 0x0021a8f8, 7}, - { 0x0021a920, 2}, - { 0x0021aa40, 41}, - { 0x0021aaec, 1}, - { 0x0021aaf8, 7}, - { 0x0021ab20, 2}, - { 0x0021ac40, 41}, - { 0x0021acec, 1}, - { 0x0021acf8, 7}, - { 0x0021ad20, 2}, - { 0x0021ae40, 41}, - { 0x0021aeec, 1}, - { 0x0021aef8, 7}, - { 0x0021af20, 2}, - { 0x0021b040, 41}, - { 0x0021b0ec, 1}, - { 0x0021b0f8, 7}, - { 0x0021b120, 2}, - { 0x0021b240, 41}, - { 0x0021b2ec, 1}, - { 0x0021b2f8, 7}, - { 0x0021b320, 2}, - { 0x0021b440, 41}, - { 0x0021b4ec, 1}, - { 0x0021b4f8, 7}, - { 0x0021b520, 2}, - { 0x0021b640, 41}, - { 0x0021b6ec, 1}, - { 0x0021b6f8, 7}, - { 0x0021b720, 2}, - { 0x0021b840, 41}, - { 0x0021b8ec, 1}, - { 0x0021b8f8, 7}, - { 0x0021b920, 2}, - { 0x0021ba40, 41}, - { 0x0021baec, 1}, - { 0x0021baf8, 7}, - { 0x0021bb20, 2}, - { 0x0021bc40, 41}, - { 0x0021bcec, 1}, - { 0x0021bcf8, 7}, - { 0x0021bd20, 2}, - { 0x0021be40, 41}, - { 0x0021beec, 1}, - { 0x0021bef8, 7}, - { 0x0021bf20, 2}, - { 0x0021c040, 41}, - { 0x0021c0ec, 1}, - { 0x0021c0f8, 7}, - { 0x0021c120, 2}, - { 0x0021c240, 41}, - { 0x0021c2ec, 1}, - { 0x0021c2f8, 7}, - { 0x0021c320, 2}, - { 0x0021c440, 41}, - { 0x0021c4ec, 1}, - { 0x0021c4f8, 7}, - { 0x0021c520, 2}, - { 0x0021c640, 41}, - { 0x0021c6ec, 1}, - { 0x0021c6f8, 7}, - { 0x0021c720, 2}, - { 0x0021c840, 41}, - { 0x0021c8ec, 1}, - { 0x0021c8f8, 7}, - { 0x0021c920, 2}, - { 0x0021ca40, 41}, - { 0x0021caec, 1}, - { 0x0021caf8, 7}, - { 0x0021cb20, 2}, - { 0x0021cc40, 41}, - { 0x0021ccec, 1}, - { 0x0021ccf8, 7}, - { 0x0021cd20, 2}, - { 0x0021ce40, 41}, - { 0x0021ceec, 1}, - { 0x0021cef8, 7}, - { 0x0021cf20, 2}, - { 0x0021d040, 41}, - { 0x0021d0ec, 1}, - { 0x0021d0f8, 7}, - { 0x0021d120, 2}, - { 0x0021d240, 41}, - { 0x0021d2ec, 1}, - { 0x0021d2f8, 7}, - { 0x0021d320, 2}, - { 0x0021d440, 41}, - { 0x0021d4ec, 1}, - { 0x0021d4f8, 7}, - { 0x0021d520, 2}, - { 0x0021d640, 41}, - { 0x0021d6ec, 1}, - { 0x0021d6f8, 7}, - { 0x0021d720, 2}, - { 0x0021d840, 41}, - { 0x0021d8ec, 1}, - { 0x0021d8f8, 7}, - { 0x0021d920, 2}, - { 0x0021da40, 41}, - { 0x0021daec, 1}, - { 0x0021daf8, 7}, - { 0x0021db20, 2}, - { 0x0021dc40, 41}, - { 0x0021dcec, 1}, - { 0x0021dcf8, 7}, - { 0x0021dd20, 2}, - { 0x0021de40, 41}, - { 0x0021deec, 1}, - { 0x0021def8, 7}, - { 0x0021df20, 2}, - { 0x0021e040, 41}, - { 0x0021e0ec, 1}, - { 0x0021e0f8, 7}, - { 0x0021e120, 2}, - { 0x0021e240, 41}, - { 0x0021e2ec, 1}, - { 0x0021e2f8, 7}, - { 0x0021e320, 2}, - { 0x0021e440, 41}, - { 0x0021e4ec, 1}, - { 0x0021e4f8, 7}, - { 0x0021e520, 2}, - { 0x0021e640, 41}, - { 0x0021e6ec, 1}, - { 0x0021e6f8, 7}, - { 0x0021e720, 2}, - { 0x0021e840, 41}, - { 0x0021e8ec, 1}, - { 0x0021e8f8, 7}, - { 0x0021e920, 2}, - { 0x0021ea40, 41}, - { 0x0021eaec, 1}, - { 0x0021eaf8, 7}, - { 0x0021eb20, 2}, - { 0x0021ec40, 41}, - { 0x0021ecec, 1}, - { 0x0021ecf8, 7}, - { 0x0021ed20, 2}, - { 0x0021ee40, 41}, - { 0x0021eeec, 1}, - { 0x0021eef8, 7}, - { 0x0021ef20, 2}, - { 0x0021f040, 41}, - { 0x0021f0ec, 1}, - { 0x0021f0f8, 7}, - { 0x0021f120, 2}, - { 0x0021f240, 41}, - { 0x0021f2ec, 1}, - { 0x0021f2f8, 7}, - { 0x0021f320, 2}, - { 0x0021f440, 41}, - { 0x0021f4ec, 1}, - { 0x0021f4f8, 7}, - { 0x0021f520, 2}, - { 0x0021f640, 41}, - { 0x0021f6ec, 1}, - { 0x0021f6f8, 7}, - { 0x0021f720, 2}, - { 0x0021f840, 41}, - { 0x0021f8ec, 1}, - { 0x0021f8f8, 7}, - { 0x0021f920, 2}, - { 0x0021fa40, 41}, - { 0x0021faec, 1}, - { 0x0021faf8, 7}, - { 0x0021fb20, 2}, - { 0x0021fc40, 41}, - { 0x0021fcec, 1}, - { 0x0021fcf8, 7}, - { 0x0021fd20, 2}, - { 0x0021fe40, 41}, - { 0x0021feec, 1}, - { 0x0021fef8, 7}, - { 0x0021ff20, 2}, - { 0x00240040, 41}, - { 0x002400ec, 1}, - { 0x002400f8, 7}, - { 0x00240120, 2}, - { 0x00240240, 41}, - { 0x002402ec, 1}, - { 0x002402f8, 7}, - { 0x00240320, 2}, - { 0x00240440, 41}, - { 0x002404ec, 1}, - { 0x002404f8, 7}, - { 0x00240520, 2}, - { 0x00240640, 41}, - { 0x002406ec, 1}, - { 0x002406f8, 7}, - { 0x00240720, 2}, - { 0x00240840, 41}, - { 0x002408ec, 1}, - { 0x002408f8, 7}, - { 0x00240920, 2}, - { 0x00240a40, 41}, - { 0x00240aec, 1}, - { 0x00240af8, 7}, - { 0x00240b20, 2}, - { 0x00240c40, 41}, - { 0x00240cec, 1}, - { 0x00240cf8, 7}, - { 0x00240d20, 2}, - { 0x00240e40, 41}, - { 0x00240eec, 1}, - { 0x00240ef8, 7}, - { 0x00240f20, 2}, - { 0x00241040, 41}, - { 0x002410ec, 1}, - { 0x002410f8, 7}, - { 0x00241120, 2}, - { 0x00241240, 41}, - { 0x002412ec, 1}, - { 0x002412f8, 7}, - { 0x00241320, 2}, - { 0x00241440, 41}, - { 0x002414ec, 1}, - { 0x002414f8, 7}, - { 0x00241520, 2}, - { 0x00241640, 41}, - { 0x002416ec, 1}, - { 0x002416f8, 7}, - { 0x00241720, 2}, - { 0x00241840, 41}, - { 0x002418ec, 1}, - { 0x002418f8, 7}, - { 0x00241920, 2}, - { 0x00241a40, 41}, - { 0x00241aec, 1}, - { 0x00241af8, 7}, - { 0x00241b20, 2}, - { 0x00241c40, 41}, - { 0x00241cec, 1}, - { 0x00241cf8, 7}, - { 0x00241d20, 2}, - { 0x00241e40, 41}, - { 0x00241eec, 1}, - { 0x00241ef8, 7}, - { 0x00241f20, 2}, - { 0x00242040, 41}, - { 0x002420ec, 1}, - { 0x002420f8, 7}, - { 0x00242120, 2}, - { 0x00242240, 41}, - { 0x002422ec, 1}, - { 0x002422f8, 7}, - { 0x00242320, 2}, - { 0x00242440, 41}, - { 0x002424ec, 1}, - { 0x002424f8, 7}, - { 0x00242520, 2}, - { 0x00242640, 41}, - { 0x002426ec, 1}, - { 0x002426f8, 7}, - { 0x00242720, 2}, - { 0x00242840, 41}, - { 0x002428ec, 1}, - { 0x002428f8, 7}, - { 0x00242920, 2}, - { 0x00242a40, 41}, - { 0x00242aec, 1}, - { 0x00242af8, 7}, - { 0x00242b20, 2}, - { 0x00242c40, 41}, - { 0x00242cec, 1}, - { 0x00242cf8, 7}, - { 0x00242d20, 2}, - { 0x00242e40, 41}, - { 0x00242eec, 1}, - { 0x00242ef8, 7}, - { 0x00242f20, 2}, - { 0x00243040, 41}, - { 0x002430ec, 1}, - { 0x002430f8, 7}, - { 0x00243120, 2}, - { 0x00243240, 41}, - { 0x002432ec, 1}, - { 0x002432f8, 7}, - { 0x00243320, 2}, - { 0x00243440, 41}, - { 0x002434ec, 1}, - { 0x002434f8, 7}, - { 0x00243520, 2}, - { 0x00243640, 41}, - { 0x002436ec, 1}, - { 0x002436f8, 7}, - { 0x00243720, 2}, - { 0x00243840, 41}, - { 0x002438ec, 1}, - { 0x002438f8, 7}, - { 0x00243920, 2}, - { 0x00243a40, 41}, - { 0x00243aec, 1}, - { 0x00243af8, 7}, - { 0x00243b20, 2}, - { 0x00243c40, 41}, - { 0x00243cec, 1}, - { 0x00243cf8, 7}, - { 0x00243d20, 2}, - { 0x00243e40, 41}, - { 0x00243eec, 1}, - { 0x00243ef8, 7}, - { 0x00243f20, 2}, - { 0x00244000, 1}, - { 0x00244008, 1}, - { 0x00244010, 2}, - { 0x00244200, 1}, - { 0x00244208, 1}, - { 0x00244210, 2}, - { 0x00244400, 1}, - { 0x00244408, 1}, - { 0x00244410, 2}, - { 0x00244600, 1}, - { 0x00244608, 1}, - { 0x00244610, 2}, - { 0x00244800, 1}, - { 0x00244808, 1}, - { 0x00244810, 2}, - { 0x00244a00, 1}, - { 0x00244a08, 1}, - { 0x00244a10, 2}, - { 0x00246000, 1}, - { 0x00246008, 1}, - { 0x00246010, 2}, - { 0x00246200, 1}, - { 0x00246208, 1}, - { 0x00246210, 2}, - { 0x00246400, 1}, - { 0x00246408, 1}, - { 0x00246410, 2}, - { 0x00246600, 1}, - { 0x00246608, 1}, - { 0x00246610, 2}, - { 0x00246800, 1}, - { 0x00246808, 1}, - { 0x00246810, 2}, - { 0x00246a00, 1}, - { 0x00246a08, 1}, - { 0x00246a10, 2}, - { 0x00246c00, 1}, - { 0x00246c08, 1}, - { 0x00246c10, 2}, - { 0x00246e00, 1}, - { 0x00246e08, 1}, - { 0x00246e10, 2}, - { 0x00248000, 1}, - { 0x00248008, 1}, - { 0x00248010, 2}, - { 0x0024a000, 1}, - { 0x0024a008, 1}, - { 0x0024a010, 11}, - { 0x0024a040, 3}, - { 0x0024a050, 3}, - { 0x0024a060, 4}, - { 0x0024a074, 7}, - { 0x0024a094, 3}, - { 0x0024a0a4, 1}, - { 0x0024a100, 6}, - { 0x0024a600, 3}, - { 0x00250040, 33}, - { 0x002500c8, 7}, - { 0x002500ec, 1}, - { 0x002500f8, 7}, - { 0x00250120, 2}, - { 0x00250240, 33}, - { 0x002502c8, 7}, - { 0x002502ec, 1}, - { 0x002502f8, 7}, - { 0x00250320, 2}, - { 0x002504a4, 8}, - { 0x00250840, 33}, - { 0x002508c8, 7}, - { 0x002508ec, 1}, - { 0x002508f8, 7}, - { 0x00250920, 2}, - { 0x00250a40, 33}, - { 0x00250ac8, 7}, - { 0x00250aec, 1}, - { 0x00250af8, 7}, - { 0x00250b20, 2}, - { 0x00251040, 33}, - { 0x002510c8, 7}, - { 0x002510ec, 1}, - { 0x002510f8, 7}, - { 0x00251120, 2}, - { 0x00251240, 33}, - { 0x002512c8, 7}, - { 0x002512ec, 1}, - { 0x002512f8, 7}, - { 0x00251320, 2}, - { 0x00251800, 3}, - { 0x00251810, 2}, - { 0x00251a00, 3}, - { 0x00251a10, 2}, - { 0x00254040, 33}, - { 0x002540c8, 7}, - { 0x002540ec, 1}, - { 0x002540f8, 7}, - { 0x00254120, 2}, - { 0x00254240, 33}, - { 0x002542c8, 7}, - { 0x002542ec, 1}, - { 0x002542f8, 7}, - { 0x00254320, 2}, - { 0x002544a4, 8}, - { 0x00254840, 33}, - { 0x002548c8, 7}, - { 0x002548ec, 1}, - { 0x002548f8, 7}, - { 0x00254920, 2}, - { 0x00254a40, 33}, - { 0x00254ac8, 7}, - { 0x00254aec, 1}, - { 0x00254af8, 7}, - { 0x00254b20, 2}, - { 0x00255800, 3}, - { 0x00255810, 2}, - { 0x00255a00, 3}, - { 0x00255a10, 2}, - { 0x00258040, 33}, - { 0x002580c8, 7}, - { 0x002580ec, 1}, - { 0x002580f8, 7}, - { 0x00258120, 2}, - { 0x00258240, 33}, - { 0x002582c8, 7}, - { 0x002582ec, 1}, - { 0x002582f8, 7}, - { 0x00258320, 2}, - { 0x002584a4, 8}, - { 0x00258840, 33}, - { 0x002588c8, 7}, - { 0x002588ec, 1}, - { 0x002588f8, 7}, - { 0x00258920, 2}, - { 0x00258a40, 33}, - { 0x00258ac8, 7}, - { 0x00258aec, 1}, - { 0x00258af8, 7}, - { 0x00258b20, 2}, - { 0x00259800, 3}, - { 0x00259810, 2}, - { 0x00259a00, 3}, - { 0x00259a10, 2}, - { 0x0025c040, 33}, - { 0x0025c0c8, 7}, - { 0x0025c0ec, 1}, - { 0x0025c0f8, 7}, - { 0x0025c120, 2}, - { 0x0025c240, 33}, - { 0x0025c2c8, 7}, - { 0x0025c2ec, 1}, - { 0x0025c2f8, 7}, - { 0x0025c320, 2}, - { 0x0025c4a4, 8}, - { 0x0025c840, 33}, - { 0x0025c8c8, 7}, - { 0x0025c8ec, 1}, - { 0x0025c8f8, 7}, - { 0x0025c920, 2}, - { 0x0025ca40, 33}, - { 0x0025cac8, 7}, - { 0x0025caec, 1}, - { 0x0025caf8, 7}, - { 0x0025cb20, 2}, - { 0x0025d800, 3}, - { 0x0025d810, 2}, - { 0x0025da00, 3}, - { 0x0025da10, 2}, - { 0x00260040, 33}, - { 0x002600c8, 7}, - { 0x002600ec, 1}, - { 0x002600f8, 7}, - { 0x00260120, 2}, - { 0x00260240, 33}, - { 0x002602c8, 7}, - { 0x002602ec, 1}, - { 0x002602f8, 7}, - { 0x00260320, 2}, - { 0x002604a4, 8}, - { 0x00260840, 33}, - { 0x002608c8, 7}, - { 0x002608ec, 1}, - { 0x002608f8, 7}, - { 0x00260920, 2}, - { 0x00260a40, 33}, - { 0x00260ac8, 7}, - { 0x00260aec, 1}, - { 0x00260af8, 7}, - { 0x00260b20, 2}, - { 0x00261800, 3}, - { 0x00261810, 2}, - { 0x00261a00, 3}, - { 0x00261a10, 2}, - { 0x00264040, 33}, - { 0x002640c8, 7}, - { 0x002640ec, 1}, - { 0x002640f8, 7}, - { 0x00264120, 2}, - { 0x00264240, 33}, - { 0x002642c8, 7}, - { 0x002642ec, 1}, - { 0x002642f8, 7}, - { 0x00264320, 2}, - { 0x002644a4, 8}, - { 0x00264840, 33}, - { 0x002648c8, 7}, - { 0x002648ec, 1}, - { 0x002648f8, 7}, - { 0x00264920, 2}, - { 0x00264a40, 33}, - { 0x00264ac8, 7}, - { 0x00264aec, 1}, - { 0x00264af8, 7}, - { 0x00264b20, 2}, - { 0x00265800, 3}, - { 0x00265810, 2}, - { 0x00265a00, 3}, - { 0x00265a10, 2}, - { 0x00268840, 33}, - { 0x002688c8, 7}, - { 0x002688ec, 1}, - { 0x002688f8, 7}, - { 0x00268920, 2}, - { 0x00268a40, 33}, - { 0x00268ac8, 7}, - { 0x00268aec, 1}, - { 0x00268af8, 7}, - { 0x00268b20, 2}, - { 0x00269a00, 3}, - { 0x00269a10, 2}, - { 0x0026c840, 33}, - { 0x0026c8c8, 7}, - { 0x0026c8ec, 1}, - { 0x0026c8f8, 7}, - { 0x0026c920, 2}, - { 0x0026ca40, 33}, - { 0x0026cac8, 7}, - { 0x0026caec, 1}, - { 0x0026caf8, 7}, - { 0x0026cb20, 2}, - { 0x0026da00, 3}, - { 0x0026da10, 2}, - { 0x00278040, 25}, - { 0x002780c8, 7}, - { 0x002780ec, 1}, - { 0x002780f8, 7}, - { 0x00278120, 2}, - { 0x00278240, 25}, - { 0x002782c8, 7}, - { 0x002782ec, 1}, - { 0x002782f8, 7}, - { 0x00278320, 2}, - { 0x00278440, 25}, - { 0x002784c8, 7}, - { 0x002784ec, 1}, - { 0x002784f8, 7}, - { 0x00278520, 2}, - { 0x00278640, 25}, - { 0x002786c8, 7}, - { 0x002786ec, 1}, - { 0x002786f8, 7}, - { 0x00278720, 2}, - { 0x00278840, 25}, - { 0x002788c8, 7}, - { 0x002788ec, 1}, - { 0x002788f8, 7}, - { 0x00278920, 2}, - { 0x00278a40, 25}, - { 0x00278ac8, 7}, - { 0x00278aec, 1}, - { 0x00278af8, 7}, - { 0x00278b20, 2}, - { 0x00278c40, 25}, - { 0x00278cc8, 7}, - { 0x00278cec, 1}, - { 0x00278cf8, 7}, - { 0x00278d20, 2}, - { 0x00278e40, 25}, - { 0x00278ec8, 7}, - { 0x00278eec, 1}, - { 0x00278ef8, 7}, - { 0x00278f20, 2}, - { 0x00279040, 25}, - { 0x002790c8, 7}, - { 0x002790ec, 1}, - { 0x002790f8, 7}, - { 0x00279120, 2}, - { 0x00279240, 25}, - { 0x002792c8, 7}, - { 0x002792ec, 1}, - { 0x002792f8, 7}, - { 0x00279320, 2}, - { 0x00279440, 25}, - { 0x002794c8, 7}, - { 0x002794ec, 1}, - { 0x002794f8, 7}, - { 0x00279520, 2}, - { 0x00279640, 25}, - { 0x002796c8, 7}, - { 0x002796ec, 1}, - { 0x002796f8, 7}, - { 0x00279720, 2}, - { 0x00279840, 25}, - { 0x002798c8, 7}, - { 0x002798ec, 1}, - { 0x002798f8, 7}, - { 0x00279920, 2}, - { 0x00279a40, 25}, - { 0x00279ac8, 7}, - { 0x00279aec, 1}, - { 0x00279af8, 7}, - { 0x00279b20, 2}, - { 0x00279c40, 25}, - { 0x00279cc8, 7}, - { 0x00279cec, 1}, - { 0x00279cf8, 7}, - { 0x00279d20, 2}, - { 0x00279e40, 25}, - { 0x00279ec8, 7}, - { 0x00279eec, 1}, - { 0x00279ef8, 7}, - { 0x00279f20, 2}, - { 0x0027a040, 25}, - { 0x0027a0c8, 7}, - { 0x0027a0ec, 1}, - { 0x0027a0f8, 7}, - { 0x0027a120, 2}, - { 0x0027a240, 25}, - { 0x0027a2c8, 7}, - { 0x0027a2ec, 1}, - { 0x0027a2f8, 7}, - { 0x0027a320, 2}, - { 0x0027a440, 25}, - { 0x0027a4c8, 7}, - { 0x0027a4ec, 1}, - { 0x0027a4f8, 7}, - { 0x0027a520, 2}, - { 0x0027a640, 25}, - { 0x0027a6c8, 7}, - { 0x0027a6ec, 1}, - { 0x0027a6f8, 7}, - { 0x0027a720, 2}, - { 0x0027a840, 25}, - { 0x0027a8c8, 7}, - { 0x0027a8ec, 1}, - { 0x0027a8f8, 7}, - { 0x0027a920, 2}, - { 0x0027aa40, 25}, - { 0x0027aac8, 7}, - { 0x0027aaec, 1}, - { 0x0027aaf8, 7}, - { 0x0027ab20, 2}, - { 0x0027ac40, 25}, - { 0x0027acc8, 7}, - { 0x0027acec, 1}, - { 0x0027acf8, 7}, - { 0x0027ad20, 2}, - { 0x0027ae40, 25}, - { 0x0027aec8, 7}, - { 0x0027aeec, 1}, - { 0x0027aef8, 7}, - { 0x0027af20, 2}, - { 0x0027b040, 25}, - { 0x0027b0c8, 7}, - { 0x0027b0ec, 1}, - { 0x0027b0f8, 7}, - { 0x0027b120, 2}, - { 0x0027b240, 25}, - { 0x0027b2c8, 7}, - { 0x0027b2ec, 1}, - { 0x0027b2f8, 7}, - { 0x0027b320, 2}, - { 0x0027b440, 25}, - { 0x0027b4c8, 7}, - { 0x0027b4ec, 1}, - { 0x0027b4f8, 7}, - { 0x0027b520, 2}, - { 0x0027b640, 25}, - { 0x0027b6c8, 7}, - { 0x0027b6ec, 1}, - { 0x0027b6f8, 7}, - { 0x0027b720, 2}, - { 0x0027b840, 25}, - { 0x0027b8c8, 7}, - { 0x0027b8ec, 1}, - { 0x0027b8f8, 7}, - { 0x0027b920, 2}, - { 0x0027ba40, 25}, - { 0x0027bac8, 7}, - { 0x0027baec, 1}, - { 0x0027baf8, 7}, - { 0x0027bb20, 2}, - { 0x0027bc40, 25}, - { 0x0027bcc8, 7}, - { 0x0027bcec, 1}, - { 0x0027bcf8, 7}, - { 0x0027bd20, 2}, - { 0x0027be40, 25}, - { 0x0027bec8, 7}, - { 0x0027beec, 1}, - { 0x0027bef8, 7}, - { 0x0027bf20, 2}, - { 0x0027c040, 25}, - { 0x0027c0c8, 7}, - { 0x0027c0ec, 1}, - { 0x0027c0f8, 7}, - { 0x0027c120, 2}, - { 0x0027c240, 25}, - { 0x0027c2c8, 7}, - { 0x0027c2ec, 1}, - { 0x0027c2f8, 7}, - { 0x0027c320, 2}, - { 0x0027c440, 25}, - { 0x0027c4c8, 7}, - { 0x0027c4ec, 1}, - { 0x0027c4f8, 7}, - { 0x0027c520, 2}, - { 0x0027c640, 25}, - { 0x0027c6c8, 7}, - { 0x0027c6ec, 1}, - { 0x0027c6f8, 7}, - { 0x0027c720, 2}, - { 0x0027c840, 25}, - { 0x0027c8c8, 7}, - { 0x0027c8ec, 1}, - { 0x0027c8f8, 7}, - { 0x0027c920, 2}, - { 0x0027ca40, 25}, - { 0x0027cac8, 7}, - { 0x0027caec, 1}, - { 0x0027caf8, 7}, - { 0x0027cb20, 2}, - { 0x0027cc40, 25}, - { 0x0027ccc8, 7}, - { 0x0027ccec, 1}, - { 0x0027ccf8, 7}, - { 0x0027cd20, 2}, - { 0x0027ce40, 25}, - { 0x0027cec8, 7}, - { 0x0027ceec, 1}, - { 0x0027cef8, 7}, - { 0x0027cf20, 2}, - { 0x0027d040, 25}, - { 0x0027d0c8, 7}, - { 0x0027d0ec, 1}, - { 0x0027d0f8, 7}, - { 0x0027d120, 2}, - { 0x0027d240, 25}, - { 0x0027d2c8, 7}, - { 0x0027d2ec, 1}, - { 0x0027d2f8, 7}, - { 0x0027d320, 2}, - { 0x0027d440, 25}, - { 0x0027d4c8, 7}, - { 0x0027d4ec, 1}, - { 0x0027d4f8, 7}, - { 0x0027d520, 2}, - { 0x0027d640, 25}, - { 0x0027d6c8, 7}, - { 0x0027d6ec, 1}, - { 0x0027d6f8, 7}, - { 0x0027d720, 2}, - { 0x0027d840, 25}, - { 0x0027d8c8, 7}, - { 0x0027d8ec, 1}, - { 0x0027d8f8, 7}, - { 0x0027d920, 2}, - { 0x0027da40, 25}, - { 0x0027dac8, 7}, - { 0x0027daec, 1}, - { 0x0027daf8, 7}, - { 0x0027db20, 2}, - { 0x0027dc40, 25}, - { 0x0027dcc8, 7}, - { 0x0027dcec, 1}, - { 0x0027dcf8, 7}, - { 0x0027dd20, 2}, - { 0x0027de40, 25}, - { 0x0027dec8, 7}, - { 0x0027deec, 1}, - { 0x0027def8, 7}, - { 0x0027df20, 2}, - { 0x0027e040, 25}, - { 0x0027e0c8, 7}, - { 0x0027e0ec, 1}, - { 0x0027e0f8, 7}, - { 0x0027e120, 2}, - { 0x0027e240, 25}, - { 0x0027e2c8, 7}, - { 0x0027e2ec, 1}, - { 0x0027e2f8, 7}, - { 0x0027e320, 2}, - { 0x0027e440, 25}, - { 0x0027e4c8, 7}, - { 0x0027e4ec, 1}, - { 0x0027e4f8, 7}, - { 0x0027e520, 2}, - { 0x0027e640, 25}, - { 0x0027e6c8, 7}, - { 0x0027e6ec, 1}, - { 0x0027e6f8, 7}, - { 0x0027e720, 2}, - { 0x0027e840, 25}, - { 0x0027e8c8, 7}, - { 0x0027e8ec, 1}, - { 0x0027e8f8, 7}, - { 0x0027e920, 2}, - { 0x0027ea40, 25}, - { 0x0027eac8, 7}, - { 0x0027eaec, 1}, - { 0x0027eaf8, 7}, - { 0x0027eb20, 2}, - { 0x0027ec40, 25}, - { 0x0027ecc8, 7}, - { 0x0027ecec, 1}, - { 0x0027ecf8, 7}, - { 0x0027ed20, 2}, - { 0x0027ee40, 25}, - { 0x0027eec8, 7}, - { 0x0027eeec, 1}, - { 0x0027eef8, 7}, - { 0x0027ef20, 2}, - { 0x0027f040, 25}, - { 0x0027f0c8, 7}, - { 0x0027f0ec, 1}, - { 0x0027f0f8, 7}, - { 0x0027f120, 2}, - { 0x0027f240, 25}, - { 0x0027f2c8, 7}, - { 0x0027f2ec, 1}, - { 0x0027f2f8, 7}, - { 0x0027f320, 2}, - { 0x0027f440, 25}, - { 0x0027f4c8, 7}, - { 0x0027f4ec, 1}, - { 0x0027f4f8, 7}, - { 0x0027f520, 2}, - { 0x0027f640, 25}, - { 0x0027f6c8, 7}, - { 0x0027f6ec, 1}, - { 0x0027f6f8, 7}, - { 0x0027f720, 2}, - { 0x0027f840, 25}, - { 0x0027f8c8, 7}, - { 0x0027f8ec, 1}, - { 0x0027f8f8, 7}, - { 0x0027f920, 2}, - { 0x0027fa40, 25}, - { 0x0027fac8, 7}, - { 0x0027faec, 1}, - { 0x0027faf8, 7}, - { 0x0027fb20, 2}, - { 0x0027fc40, 25}, - { 0x0027fcc8, 7}, - { 0x0027fcec, 1}, - { 0x0027fcf8, 7}, - { 0x0027fd20, 2}, - { 0x0027fe40, 25}, - { 0x0027fec8, 7}, - { 0x0027feec, 1}, - { 0x0027fef8, 7}, - { 0x0027ff20, 2}, - { 0x00280040, 25}, - { 0x002800c8, 7}, - { 0x002800ec, 1}, - { 0x002800f8, 7}, - { 0x00280120, 2}, - { 0x00280240, 25}, - { 0x002802c8, 7}, - { 0x002802ec, 1}, - { 0x002802f8, 7}, - { 0x00280320, 2}, - { 0x00280440, 25}, - { 0x002804c8, 7}, - { 0x002804ec, 1}, - { 0x002804f8, 7}, - { 0x00280520, 2}, - { 0x00280640, 25}, - { 0x002806c8, 7}, - { 0x002806ec, 1}, - { 0x002806f8, 7}, - { 0x00280720, 2}, - { 0x00280840, 25}, - { 0x002808c8, 7}, - { 0x002808ec, 1}, - { 0x002808f8, 7}, - { 0x00280920, 2}, - { 0x00280a40, 25}, - { 0x00280ac8, 7}, - { 0x00280aec, 1}, - { 0x00280af8, 7}, - { 0x00280b20, 2}, - { 0x00280c40, 25}, - { 0x00280cc8, 7}, - { 0x00280cec, 1}, - { 0x00280cf8, 7}, - { 0x00280d20, 2}, - { 0x00280e40, 25}, - { 0x00280ec8, 7}, - { 0x00280eec, 1}, - { 0x00280ef8, 7}, - { 0x00280f20, 2}, - { 0x00281040, 25}, - { 0x002810c8, 7}, - { 0x002810ec, 1}, - { 0x002810f8, 7}, - { 0x00281120, 2}, - { 0x00281240, 25}, - { 0x002812c8, 7}, - { 0x002812ec, 1}, - { 0x002812f8, 7}, - { 0x00281320, 2}, - { 0x00281440, 25}, - { 0x002814c8, 7}, - { 0x002814ec, 1}, - { 0x002814f8, 7}, - { 0x00281520, 2}, - { 0x00281640, 25}, - { 0x002816c8, 7}, - { 0x002816ec, 1}, - { 0x002816f8, 7}, - { 0x00281720, 2}, - { 0x00281840, 25}, - { 0x002818c8, 7}, - { 0x002818ec, 1}, - { 0x002818f8, 7}, - { 0x00281920, 2}, - { 0x00281a40, 25}, - { 0x00281ac8, 7}, - { 0x00281aec, 1}, - { 0x00281af8, 7}, - { 0x00281b20, 2}, - { 0x00281c40, 25}, - { 0x00281cc8, 7}, - { 0x00281cec, 1}, - { 0x00281cf8, 7}, - { 0x00281d20, 2}, - { 0x00281e40, 25}, - { 0x00281ec8, 7}, - { 0x00281eec, 1}, - { 0x00281ef8, 7}, - { 0x00281f20, 2}, - { 0x00282040, 25}, - { 0x002820c8, 7}, - { 0x002820ec, 1}, - { 0x002820f8, 7}, - { 0x00282120, 2}, - { 0x00282240, 25}, - { 0x002822c8, 7}, - { 0x002822ec, 1}, - { 0x002822f8, 7}, - { 0x00282320, 2}, - { 0x00282440, 25}, - { 0x002824c8, 7}, - { 0x002824ec, 1}, - { 0x002824f8, 7}, - { 0x00282520, 2}, - { 0x00282640, 25}, - { 0x002826c8, 7}, - { 0x002826ec, 1}, - { 0x002826f8, 7}, - { 0x00282720, 2}, - { 0x00282840, 25}, - { 0x002828c8, 7}, - { 0x002828ec, 1}, - { 0x002828f8, 7}, - { 0x00282920, 2}, - { 0x00282a40, 25}, - { 0x00282ac8, 7}, - { 0x00282aec, 1}, - { 0x00282af8, 7}, - { 0x00282b20, 2}, - { 0x00282c40, 25}, - { 0x00282cc8, 7}, - { 0x00282cec, 1}, - { 0x00282cf8, 7}, - { 0x00282d20, 2}, - { 0x00282e40, 25}, - { 0x00282ec8, 7}, - { 0x00282eec, 1}, - { 0x00282ef8, 7}, - { 0x00282f20, 2}, - { 0x00283040, 25}, - { 0x002830c8, 7}, - { 0x002830ec, 1}, - { 0x002830f8, 7}, - { 0x00283120, 2}, - { 0x00283240, 25}, - { 0x002832c8, 7}, - { 0x002832ec, 1}, - { 0x002832f8, 7}, - { 0x00283320, 2}, - { 0x00283440, 25}, - { 0x002834c8, 7}, - { 0x002834ec, 1}, - { 0x002834f8, 7}, - { 0x00283520, 2}, - { 0x00283640, 25}, - { 0x002836c8, 7}, - { 0x002836ec, 1}, - { 0x002836f8, 7}, - { 0x00283720, 2}, - { 0x00283840, 25}, - { 0x002838c8, 7}, - { 0x002838ec, 1}, - { 0x002838f8, 7}, - { 0x00283920, 2}, - { 0x00283a40, 25}, - { 0x00283ac8, 7}, - { 0x00283aec, 1}, - { 0x00283af8, 7}, - { 0x00283b20, 2}, - { 0x00283c40, 25}, - { 0x00283cc8, 7}, - { 0x00283cec, 1}, - { 0x00283cf8, 7}, - { 0x00283d20, 2}, - { 0x00283e40, 25}, - { 0x00283ec8, 7}, - { 0x00283eec, 1}, - { 0x00283ef8, 7}, - { 0x00283f20, 2}, - { 0x00284040, 25}, - { 0x002840c8, 7}, - { 0x002840ec, 1}, - { 0x002840f8, 7}, - { 0x00284120, 2}, - { 0x00284240, 25}, - { 0x002842c8, 7}, - { 0x002842ec, 1}, - { 0x002842f8, 7}, - { 0x00284320, 2}, - { 0x00284440, 25}, - { 0x002844c8, 7}, - { 0x002844ec, 1}, - { 0x002844f8, 7}, - { 0x00284520, 2}, - { 0x00284640, 25}, - { 0x002846c8, 7}, - { 0x002846ec, 1}, - { 0x002846f8, 7}, - { 0x00284720, 2}, - { 0x00284840, 25}, - { 0x002848c8, 7}, - { 0x002848ec, 1}, - { 0x002848f8, 7}, - { 0x00284920, 2}, - { 0x00284a40, 25}, - { 0x00284ac8, 7}, - { 0x00284aec, 1}, - { 0x00284af8, 7}, - { 0x00284b20, 2}, - { 0x00284c40, 25}, - { 0x00284cc8, 7}, - { 0x00284cec, 1}, - { 0x00284cf8, 7}, - { 0x00284d20, 2}, - { 0x00284e40, 25}, - { 0x00284ec8, 7}, - { 0x00284eec, 1}, - { 0x00284ef8, 7}, - { 0x00284f20, 2}, - { 0x00285040, 25}, - { 0x002850c8, 7}, - { 0x002850ec, 1}, - { 0x002850f8, 7}, - { 0x00285120, 2}, - { 0x00285240, 25}, - { 0x002852c8, 7}, - { 0x002852ec, 1}, - { 0x002852f8, 7}, - { 0x00285320, 2}, - { 0x00285440, 25}, - { 0x002854c8, 7}, - { 0x002854ec, 1}, - { 0x002854f8, 7}, - { 0x00285520, 2}, - { 0x00285640, 25}, - { 0x002856c8, 7}, - { 0x002856ec, 1}, - { 0x002856f8, 7}, - { 0x00285720, 2}, - { 0x00285840, 25}, - { 0x002858c8, 7}, - { 0x002858ec, 1}, - { 0x002858f8, 7}, - { 0x00285920, 2}, - { 0x00285a40, 25}, - { 0x00285ac8, 7}, - { 0x00285aec, 1}, - { 0x00285af8, 7}, - { 0x00285b20, 2}, - { 0x00285c40, 25}, - { 0x00285cc8, 7}, - { 0x00285cec, 1}, - { 0x00285cf8, 7}, - { 0x00285d20, 2}, - { 0x00285e40, 25}, - { 0x00285ec8, 7}, - { 0x00285eec, 1}, - { 0x00285ef8, 7}, - { 0x00285f20, 2}, - { 0x00286040, 25}, - { 0x002860c8, 7}, - { 0x002860ec, 1}, - { 0x002860f8, 7}, - { 0x00286120, 2}, - { 0x00286240, 25}, - { 0x002862c8, 7}, - { 0x002862ec, 1}, - { 0x002862f8, 7}, - { 0x00286320, 2}, - { 0x00286440, 25}, - { 0x002864c8, 7}, - { 0x002864ec, 1}, - { 0x002864f8, 7}, - { 0x00286520, 2}, - { 0x00286640, 25}, - { 0x002866c8, 7}, - { 0x002866ec, 1}, - { 0x002866f8, 7}, - { 0x00286720, 2}, - { 0x00286840, 25}, - { 0x002868c8, 7}, - { 0x002868ec, 1}, - { 0x002868f8, 7}, - { 0x00286920, 2}, - { 0x00286a40, 25}, - { 0x00286ac8, 7}, - { 0x00286aec, 1}, - { 0x00286af8, 7}, - { 0x00286b20, 2}, - { 0x00286c40, 25}, - { 0x00286cc8, 7}, - { 0x00286cec, 1}, - { 0x00286cf8, 7}, - { 0x00286d20, 2}, - { 0x00286e40, 25}, - { 0x00286ec8, 7}, - { 0x00286eec, 1}, - { 0x00286ef8, 7}, - { 0x00286f20, 2}, - { 0x00287040, 25}, - { 0x002870c8, 7}, - { 0x002870ec, 1}, - { 0x002870f8, 7}, - { 0x00287120, 2}, - { 0x00287240, 25}, - { 0x002872c8, 7}, - { 0x002872ec, 1}, - { 0x002872f8, 7}, - { 0x00287320, 2}, - { 0x00287440, 25}, - { 0x002874c8, 7}, - { 0x002874ec, 1}, - { 0x002874f8, 7}, - { 0x00287520, 2}, - { 0x00287640, 25}, - { 0x002876c8, 7}, - { 0x002876ec, 1}, - { 0x002876f8, 7}, - { 0x00287720, 2}, - { 0x00287840, 25}, - { 0x002878c8, 7}, - { 0x002878ec, 1}, - { 0x002878f8, 7}, - { 0x00287920, 2}, - { 0x00287a40, 25}, - { 0x00287ac8, 7}, - { 0x00287aec, 1}, - { 0x00287af8, 7}, - { 0x00287b20, 2}, - { 0x00287c40, 25}, - { 0x00287cc8, 7}, - { 0x00287cec, 1}, - { 0x00287cf8, 7}, - { 0x00287d20, 2}, - { 0x00287e40, 25}, - { 0x00287ec8, 7}, - { 0x00287eec, 1}, - { 0x00287ef8, 7}, - { 0x00287f20, 2}, - { 0x00288040, 25}, - { 0x002880c8, 7}, - { 0x002880ec, 1}, - { 0x002880f8, 7}, - { 0x00288120, 2}, - { 0x00288240, 25}, - { 0x002882c8, 7}, - { 0x002882ec, 1}, - { 0x002882f8, 7}, - { 0x00288320, 2}, - { 0x00288440, 25}, - { 0x002884c8, 7}, - { 0x002884ec, 1}, - { 0x002884f8, 7}, - { 0x00288520, 2}, - { 0x00288640, 25}, - { 0x002886c8, 7}, - { 0x002886ec, 1}, - { 0x002886f8, 7}, - { 0x00288720, 2}, - { 0x00288840, 25}, - { 0x002888c8, 7}, - { 0x002888ec, 1}, - { 0x002888f8, 7}, - { 0x00288920, 2}, - { 0x00288a40, 25}, - { 0x00288ac8, 7}, - { 0x00288aec, 1}, - { 0x00288af8, 7}, - { 0x00288b20, 2}, - { 0x00288c40, 25}, - { 0x00288cc8, 7}, - { 0x00288cec, 1}, - { 0x00288cf8, 7}, - { 0x00288d20, 2}, - { 0x00288e40, 25}, - { 0x00288ec8, 7}, - { 0x00288eec, 1}, - { 0x00288ef8, 7}, - { 0x00288f20, 2}, - { 0x00289040, 25}, - { 0x002890c8, 7}, - { 0x002890ec, 1}, - { 0x002890f8, 7}, - { 0x00289120, 2}, - { 0x00289240, 25}, - { 0x002892c8, 7}, - { 0x002892ec, 1}, - { 0x002892f8, 7}, - { 0x00289320, 2}, - { 0x00289440, 25}, - { 0x002894c8, 7}, - { 0x002894ec, 1}, - { 0x002894f8, 7}, - { 0x00289520, 2}, - { 0x00289640, 25}, - { 0x002896c8, 7}, - { 0x002896ec, 1}, - { 0x002896f8, 7}, - { 0x00289720, 2}, - { 0x00289840, 25}, - { 0x002898c8, 7}, - { 0x002898ec, 1}, - { 0x002898f8, 7}, - { 0x00289920, 2}, - { 0x00289a40, 25}, - { 0x00289ac8, 7}, - { 0x00289aec, 1}, - { 0x00289af8, 7}, - { 0x00289b20, 2}, - { 0x00289c40, 25}, - { 0x00289cc8, 7}, - { 0x00289cec, 1}, - { 0x00289cf8, 7}, - { 0x00289d20, 2}, - { 0x00289e40, 25}, - { 0x00289ec8, 7}, - { 0x00289eec, 1}, - { 0x00289ef8, 7}, - { 0x00289f20, 2}, - { 0x0028a040, 25}, - { 0x0028a0c8, 7}, - { 0x0028a0ec, 1}, - { 0x0028a0f8, 7}, - { 0x0028a120, 2}, - { 0x0028a240, 25}, - { 0x0028a2c8, 7}, - { 0x0028a2ec, 1}, - { 0x0028a2f8, 7}, - { 0x0028a320, 2}, - { 0x0028a440, 25}, - { 0x0028a4c8, 7}, - { 0x0028a4ec, 1}, - { 0x0028a4f8, 7}, - { 0x0028a520, 2}, - { 0x0028a640, 25}, - { 0x0028a6c8, 7}, - { 0x0028a6ec, 1}, - { 0x0028a6f8, 7}, - { 0x0028a720, 2}, - { 0x0028a840, 25}, - { 0x0028a8c8, 7}, - { 0x0028a8ec, 1}, - { 0x0028a8f8, 7}, - { 0x0028a920, 2}, - { 0x0028aa40, 25}, - { 0x0028aac8, 7}, - { 0x0028aaec, 1}, - { 0x0028aaf8, 7}, - { 0x0028ab20, 2}, - { 0x0028ac40, 25}, - { 0x0028acc8, 7}, - { 0x0028acec, 1}, - { 0x0028acf8, 7}, - { 0x0028ad20, 2}, - { 0x0028ae40, 25}, - { 0x0028aec8, 7}, - { 0x0028aeec, 1}, - { 0x0028aef8, 7}, - { 0x0028af20, 2}, - { 0x0028b040, 25}, - { 0x0028b0c8, 7}, - { 0x0028b0ec, 1}, - { 0x0028b0f8, 7}, - { 0x0028b120, 2}, - { 0x0028b240, 25}, - { 0x0028b2c8, 7}, - { 0x0028b2ec, 1}, - { 0x0028b2f8, 7}, - { 0x0028b320, 2}, - { 0x0028b440, 25}, - { 0x0028b4c8, 7}, - { 0x0028b4ec, 1}, - { 0x0028b4f8, 7}, - { 0x0028b520, 2}, - { 0x0028b640, 25}, - { 0x0028b6c8, 7}, - { 0x0028b6ec, 1}, - { 0x0028b6f8, 7}, - { 0x0028b720, 2}, - { 0x0028b840, 25}, - { 0x0028b8c8, 7}, - { 0x0028b8ec, 1}, - { 0x0028b8f8, 7}, - { 0x0028b920, 2}, - { 0x0028ba40, 25}, - { 0x0028bac8, 7}, - { 0x0028baec, 1}, - { 0x0028baf8, 7}, - { 0x0028bb20, 2}, - { 0x0028bc40, 25}, - { 0x0028bcc8, 7}, - { 0x0028bcec, 1}, - { 0x0028bcf8, 7}, - { 0x0028bd20, 2}, - { 0x0028be40, 25}, - { 0x0028bec8, 7}, - { 0x0028beec, 1}, - { 0x0028bef8, 7}, - { 0x0028bf20, 2}, - { 0x0028c040, 25}, - { 0x0028c0c8, 7}, - { 0x0028c0ec, 1}, - { 0x0028c0f8, 7}, - { 0x0028c120, 2}, - { 0x0028c240, 25}, - { 0x0028c2c8, 7}, - { 0x0028c2ec, 1}, - { 0x0028c2f8, 7}, - { 0x0028c320, 2}, - { 0x0028c440, 25}, - { 0x0028c4c8, 7}, - { 0x0028c4ec, 1}, - { 0x0028c4f8, 7}, - { 0x0028c520, 2}, - { 0x0028c640, 25}, - { 0x0028c6c8, 7}, - { 0x0028c6ec, 1}, - { 0x0028c6f8, 7}, - { 0x0028c720, 2}, - { 0x0028c840, 25}, - { 0x0028c8c8, 7}, - { 0x0028c8ec, 1}, - { 0x0028c8f8, 7}, - { 0x0028c920, 2}, - { 0x0028ca40, 25}, - { 0x0028cac8, 7}, - { 0x0028caec, 1}, - { 0x0028caf8, 7}, - { 0x0028cb20, 2}, - { 0x0028cc40, 25}, - { 0x0028ccc8, 7}, - { 0x0028ccec, 1}, - { 0x0028ccf8, 7}, - { 0x0028cd20, 2}, - { 0x0028ce40, 25}, - { 0x0028cec8, 7}, - { 0x0028ceec, 1}, - { 0x0028cef8, 7}, - { 0x0028cf20, 2}, - { 0x0028d040, 25}, - { 0x0028d0c8, 7}, - { 0x0028d0ec, 1}, - { 0x0028d0f8, 7}, - { 0x0028d120, 2}, - { 0x0028d240, 25}, - { 0x0028d2c8, 7}, - { 0x0028d2ec, 1}, - { 0x0028d2f8, 7}, - { 0x0028d320, 2}, - { 0x0028d440, 25}, - { 0x0028d4c8, 7}, - { 0x0028d4ec, 1}, - { 0x0028d4f8, 7}, - { 0x0028d520, 2}, - { 0x0028d640, 25}, - { 0x0028d6c8, 7}, - { 0x0028d6ec, 1}, - { 0x0028d6f8, 7}, - { 0x0028d720, 2}, - { 0x0028d840, 25}, - { 0x0028d8c8, 7}, - { 0x0028d8ec, 1}, - { 0x0028d8f8, 7}, - { 0x0028d920, 2}, - { 0x0028da40, 25}, - { 0x0028dac8, 7}, - { 0x0028daec, 1}, - { 0x0028daf8, 7}, - { 0x0028db20, 2}, - { 0x0028dc40, 25}, - { 0x0028dcc8, 7}, - { 0x0028dcec, 1}, - { 0x0028dcf8, 7}, - { 0x0028dd20, 2}, - { 0x0028de40, 25}, - { 0x0028dec8, 7}, - { 0x0028deec, 1}, - { 0x0028def8, 7}, - { 0x0028df20, 2}, - { 0x0028e040, 25}, - { 0x0028e0c8, 7}, - { 0x0028e0ec, 1}, - { 0x0028e0f8, 7}, - { 0x0028e120, 2}, - { 0x0028e240, 25}, - { 0x0028e2c8, 7}, - { 0x0028e2ec, 1}, - { 0x0028e2f8, 7}, - { 0x0028e320, 2}, - { 0x0028e440, 25}, - { 0x0028e4c8, 7}, - { 0x0028e4ec, 1}, - { 0x0028e4f8, 7}, - { 0x0028e520, 2}, - { 0x0028e640, 25}, - { 0x0028e6c8, 7}, - { 0x0028e6ec, 1}, - { 0x0028e6f8, 7}, - { 0x0028e720, 2}, - { 0x0028e840, 25}, - { 0x0028e8c8, 7}, - { 0x0028e8ec, 1}, - { 0x0028e8f8, 7}, - { 0x0028e920, 2}, - { 0x0028ea40, 25}, - { 0x0028eac8, 7}, - { 0x0028eaec, 1}, - { 0x0028eaf8, 7}, - { 0x0028eb20, 2}, - { 0x0028ec40, 25}, - { 0x0028ecc8, 7}, - { 0x0028ecec, 1}, - { 0x0028ecf8, 7}, - { 0x0028ed20, 2}, - { 0x0028ee40, 25}, - { 0x0028eec8, 7}, - { 0x0028eeec, 1}, - { 0x0028eef8, 7}, - { 0x0028ef20, 2}, - { 0x0028f040, 25}, - { 0x0028f0c8, 7}, - { 0x0028f0ec, 1}, - { 0x0028f0f8, 7}, - { 0x0028f120, 2}, - { 0x0028f240, 25}, - { 0x0028f2c8, 7}, - { 0x0028f2ec, 1}, - { 0x0028f2f8, 7}, - { 0x0028f320, 2}, - { 0x0028f440, 25}, - { 0x0028f4c8, 7}, - { 0x0028f4ec, 1}, - { 0x0028f4f8, 7}, - { 0x0028f520, 2}, - { 0x0028f640, 25}, - { 0x0028f6c8, 7}, - { 0x0028f6ec, 1}, - { 0x0028f6f8, 7}, - { 0x0028f720, 2}, - { 0x0028f840, 25}, - { 0x0028f8c8, 7}, - { 0x0028f8ec, 1}, - { 0x0028f8f8, 7}, - { 0x0028f920, 2}, - { 0x0028fa40, 25}, - { 0x0028fac8, 7}, - { 0x0028faec, 1}, - { 0x0028faf8, 7}, - { 0x0028fb20, 2}, - { 0x0028fc40, 25}, - { 0x0028fcc8, 7}, - { 0x0028fcec, 1}, - { 0x0028fcf8, 7}, - { 0x0028fd20, 2}, - { 0x0028fe40, 25}, - { 0x0028fec8, 7}, - { 0x0028feec, 1}, - { 0x0028fef8, 7}, - { 0x0028ff20, 2}, - { 0x00290040, 25}, - { 0x002900c8, 7}, - { 0x002900ec, 1}, - { 0x002900f8, 7}, - { 0x00290120, 2}, - { 0x00290240, 25}, - { 0x002902c8, 7}, - { 0x002902ec, 1}, - { 0x002902f8, 7}, - { 0x00290320, 2}, - { 0x00290440, 25}, - { 0x002904c8, 7}, - { 0x002904ec, 1}, - { 0x002904f8, 7}, - { 0x00290520, 2}, - { 0x00290640, 25}, - { 0x002906c8, 7}, - { 0x002906ec, 1}, - { 0x002906f8, 7}, - { 0x00290720, 2}, - { 0x00290840, 25}, - { 0x002908c8, 7}, - { 0x002908ec, 1}, - { 0x002908f8, 7}, - { 0x00290920, 2}, - { 0x00290a40, 25}, - { 0x00290ac8, 7}, - { 0x00290aec, 1}, - { 0x00290af8, 7}, - { 0x00290b20, 2}, - { 0x00290c40, 25}, - { 0x00290cc8, 7}, - { 0x00290cec, 1}, - { 0x00290cf8, 7}, - { 0x00290d20, 2}, - { 0x00290e40, 25}, - { 0x00290ec8, 7}, - { 0x00290eec, 1}, - { 0x00290ef8, 7}, - { 0x00290f20, 2}, - { 0x00291040, 25}, - { 0x002910c8, 7}, - { 0x002910ec, 1}, - { 0x002910f8, 7}, - { 0x00291120, 2}, - { 0x00291240, 25}, - { 0x002912c8, 7}, - { 0x002912ec, 1}, - { 0x002912f8, 7}, - { 0x00291320, 2}, - { 0x00291440, 25}, - { 0x002914c8, 7}, - { 0x002914ec, 1}, - { 0x002914f8, 7}, - { 0x00291520, 2}, - { 0x00291640, 25}, - { 0x002916c8, 7}, - { 0x002916ec, 1}, - { 0x002916f8, 7}, - { 0x00291720, 2}, - { 0x00291840, 25}, - { 0x002918c8, 7}, - { 0x002918ec, 1}, - { 0x002918f8, 7}, - { 0x00291920, 2}, - { 0x00291a40, 25}, - { 0x00291ac8, 7}, - { 0x00291aec, 1}, - { 0x00291af8, 7}, - { 0x00291b20, 2}, - { 0x00291c40, 25}, - { 0x00291cc8, 7}, - { 0x00291cec, 1}, - { 0x00291cf8, 7}, - { 0x00291d20, 2}, - { 0x00291e40, 25}, - { 0x00291ec8, 7}, - { 0x00291eec, 1}, - { 0x00291ef8, 7}, - { 0x00291f20, 2}, - { 0x00292040, 25}, - { 0x002920c8, 7}, - { 0x002920ec, 1}, - { 0x002920f8, 7}, - { 0x00292120, 2}, - { 0x00292240, 25}, - { 0x002922c8, 7}, - { 0x002922ec, 1}, - { 0x002922f8, 7}, - { 0x00292320, 2}, - { 0x00292440, 25}, - { 0x002924c8, 7}, - { 0x002924ec, 1}, - { 0x002924f8, 7}, - { 0x00292520, 2}, - { 0x00292640, 25}, - { 0x002926c8, 7}, - { 0x002926ec, 1}, - { 0x002926f8, 7}, - { 0x00292720, 2}, - { 0x00292840, 25}, - { 0x002928c8, 7}, - { 0x002928ec, 1}, - { 0x002928f8, 7}, - { 0x00292920, 2}, - { 0x00292a40, 25}, - { 0x00292ac8, 7}, - { 0x00292aec, 1}, - { 0x00292af8, 7}, - { 0x00292b20, 2}, - { 0x00292c40, 25}, - { 0x00292cc8, 7}, - { 0x00292cec, 1}, - { 0x00292cf8, 7}, - { 0x00292d20, 2}, - { 0x00292e40, 25}, - { 0x00292ec8, 7}, - { 0x00292eec, 1}, - { 0x00292ef8, 7}, - { 0x00292f20, 2}, - { 0x00293040, 25}, - { 0x002930c8, 7}, - { 0x002930ec, 1}, - { 0x002930f8, 7}, - { 0x00293120, 2}, - { 0x00293240, 25}, - { 0x002932c8, 7}, - { 0x002932ec, 1}, - { 0x002932f8, 7}, - { 0x00293320, 2}, - { 0x00293440, 25}, - { 0x002934c8, 7}, - { 0x002934ec, 1}, - { 0x002934f8, 7}, - { 0x00293520, 2}, - { 0x00293640, 25}, - { 0x002936c8, 7}, - { 0x002936ec, 1}, - { 0x002936f8, 7}, - { 0x00293720, 2}, - { 0x00293840, 25}, - { 0x002938c8, 7}, - { 0x002938ec, 1}, - { 0x002938f8, 7}, - { 0x00293920, 2}, - { 0x00293a40, 25}, - { 0x00293ac8, 7}, - { 0x00293aec, 1}, - { 0x00293af8, 7}, - { 0x00293b20, 2}, - { 0x00293c40, 25}, - { 0x00293cc8, 7}, - { 0x00293cec, 1}, - { 0x00293cf8, 7}, - { 0x00293d20, 2}, - { 0x00293e40, 25}, - { 0x00293ec8, 7}, - { 0x00293eec, 1}, - { 0x00293ef8, 7}, - { 0x00293f20, 2}, - { 0x00294040, 25}, - { 0x002940c8, 7}, - { 0x002940ec, 1}, - { 0x002940f8, 7}, - { 0x00294120, 2}, - { 0x00294240, 25}, - { 0x002942c8, 7}, - { 0x002942ec, 1}, - { 0x002942f8, 7}, - { 0x00294320, 2}, - { 0x00294440, 25}, - { 0x002944c8, 7}, - { 0x002944ec, 1}, - { 0x002944f8, 7}, - { 0x00294520, 2}, - { 0x00294640, 25}, - { 0x002946c8, 7}, - { 0x002946ec, 1}, - { 0x002946f8, 7}, - { 0x00294720, 2}, - { 0x00294840, 25}, - { 0x002948c8, 7}, - { 0x002948ec, 1}, - { 0x002948f8, 7}, - { 0x00294920, 2}, - { 0x00294a40, 25}, - { 0x00294ac8, 7}, - { 0x00294aec, 1}, - { 0x00294af8, 7}, - { 0x00294b20, 2}, - { 0x00294c40, 25}, - { 0x00294cc8, 7}, - { 0x00294cec, 1}, - { 0x00294cf8, 7}, - { 0x00294d20, 2}, - { 0x00294e40, 25}, - { 0x00294ec8, 7}, - { 0x00294eec, 1}, - { 0x00294ef8, 7}, - { 0x00294f20, 2}, - { 0x00295040, 25}, - { 0x002950c8, 7}, - { 0x002950ec, 1}, - { 0x002950f8, 7}, - { 0x00295120, 2}, - { 0x00295240, 25}, - { 0x002952c8, 7}, - { 0x002952ec, 1}, - { 0x002952f8, 7}, - { 0x00295320, 2}, - { 0x00295440, 25}, - { 0x002954c8, 7}, - { 0x002954ec, 1}, - { 0x002954f8, 7}, - { 0x00295520, 2}, - { 0x00295640, 25}, - { 0x002956c8, 7}, - { 0x002956ec, 1}, - { 0x002956f8, 7}, - { 0x00295720, 2}, - { 0x00295840, 25}, - { 0x002958c8, 7}, - { 0x002958ec, 1}, - { 0x002958f8, 7}, - { 0x00295920, 2}, - { 0x00295a40, 25}, - { 0x00295ac8, 7}, - { 0x00295aec, 1}, - { 0x00295af8, 7}, - { 0x00295b20, 2}, - { 0x00295c40, 25}, - { 0x00295cc8, 7}, - { 0x00295cec, 1}, - { 0x00295cf8, 7}, - { 0x00295d20, 2}, - { 0x00295e40, 25}, - { 0x00295ec8, 7}, - { 0x00295eec, 1}, - { 0x00295ef8, 7}, - { 0x00295f20, 2}, - { 0x00296040, 25}, - { 0x002960c8, 7}, - { 0x002960ec, 1}, - { 0x002960f8, 7}, - { 0x00296120, 2}, - { 0x00296240, 25}, - { 0x002962c8, 7}, - { 0x002962ec, 1}, - { 0x002962f8, 7}, - { 0x00296320, 2}, - { 0x00296440, 25}, - { 0x002964c8, 7}, - { 0x002964ec, 1}, - { 0x002964f8, 7}, - { 0x00296520, 2}, - { 0x00296640, 25}, - { 0x002966c8, 7}, - { 0x002966ec, 1}, - { 0x002966f8, 7}, - { 0x00296720, 2}, - { 0x00296840, 25}, - { 0x002968c8, 7}, - { 0x002968ec, 1}, - { 0x002968f8, 7}, - { 0x00296920, 2}, - { 0x00296a40, 25}, - { 0x00296ac8, 7}, - { 0x00296aec, 1}, - { 0x00296af8, 7}, - { 0x00296b20, 2}, - { 0x00296c40, 25}, - { 0x00296cc8, 7}, - { 0x00296cec, 1}, - { 0x00296cf8, 7}, - { 0x00296d20, 2}, - { 0x00296e40, 25}, - { 0x00296ec8, 7}, - { 0x00296eec, 1}, - { 0x00296ef8, 7}, - { 0x00296f20, 2}, - { 0x00297040, 25}, - { 0x002970c8, 7}, - { 0x002970ec, 1}, - { 0x002970f8, 7}, - { 0x00297120, 2}, - { 0x00297240, 25}, - { 0x002972c8, 7}, - { 0x002972ec, 1}, - { 0x002972f8, 7}, - { 0x00297320, 2}, - { 0x00297440, 25}, - { 0x002974c8, 7}, - { 0x002974ec, 1}, - { 0x002974f8, 7}, - { 0x00297520, 2}, - { 0x00297640, 25}, - { 0x002976c8, 7}, - { 0x002976ec, 1}, - { 0x002976f8, 7}, - { 0x00297720, 2}, - { 0x00297840, 25}, - { 0x002978c8, 7}, - { 0x002978ec, 1}, - { 0x002978f8, 7}, - { 0x00297920, 2}, - { 0x00297a40, 25}, - { 0x00297ac8, 7}, - { 0x00297aec, 1}, - { 0x00297af8, 7}, - { 0x00297b20, 2}, - { 0x00297c40, 25}, - { 0x00297cc8, 7}, - { 0x00297cec, 1}, - { 0x00297cf8, 7}, - { 0x00297d20, 2}, - { 0x00297e40, 25}, - { 0x00297ec8, 7}, - { 0x00297eec, 1}, - { 0x00297ef8, 7}, - { 0x00297f20, 2}, - { 0x00298040, 25}, - { 0x002980c8, 7}, - { 0x002980ec, 1}, - { 0x002980f8, 7}, - { 0x00298120, 2}, - { 0x00298240, 25}, - { 0x002982c8, 7}, - { 0x002982ec, 1}, - { 0x002982f8, 7}, - { 0x00298320, 2}, - { 0x00298440, 25}, - { 0x002984c8, 7}, - { 0x002984ec, 1}, - { 0x002984f8, 7}, - { 0x00298520, 2}, - { 0x00298640, 25}, - { 0x002986c8, 7}, - { 0x002986ec, 1}, - { 0x002986f8, 7}, - { 0x00298720, 2}, - { 0x00298840, 25}, - { 0x002988c8, 7}, - { 0x002988ec, 1}, - { 0x002988f8, 7}, - { 0x00298920, 2}, - { 0x00298a40, 25}, - { 0x00298ac8, 7}, - { 0x00298aec, 1}, - { 0x00298af8, 7}, - { 0x00298b20, 2}, - { 0x00298c40, 25}, - { 0x00298cc8, 7}, - { 0x00298cec, 1}, - { 0x00298cf8, 7}, - { 0x00298d20, 2}, - { 0x00298e40, 25}, - { 0x00298ec8, 7}, - { 0x00298eec, 1}, - { 0x00298ef8, 7}, - { 0x00298f20, 2}, - { 0x00299040, 25}, - { 0x002990c8, 7}, - { 0x002990ec, 1}, - { 0x002990f8, 7}, - { 0x00299120, 2}, - { 0x00299240, 25}, - { 0x002992c8, 7}, - { 0x002992ec, 1}, - { 0x002992f8, 7}, - { 0x00299320, 2}, - { 0x00299440, 25}, - { 0x002994c8, 7}, - { 0x002994ec, 1}, - { 0x002994f8, 7}, - { 0x00299520, 2}, - { 0x00299640, 25}, - { 0x002996c8, 7}, - { 0x002996ec, 1}, - { 0x002996f8, 7}, - { 0x00299720, 2}, - { 0x00299840, 25}, - { 0x002998c8, 7}, - { 0x002998ec, 1}, - { 0x002998f8, 7}, - { 0x00299920, 2}, - { 0x00299a40, 25}, - { 0x00299ac8, 7}, - { 0x00299aec, 1}, - { 0x00299af8, 7}, - { 0x00299b20, 2}, - { 0x00299c40, 25}, - { 0x00299cc8, 7}, - { 0x00299cec, 1}, - { 0x00299cf8, 7}, - { 0x00299d20, 2}, - { 0x00299e40, 25}, - { 0x00299ec8, 7}, - { 0x00299eec, 1}, - { 0x00299ef8, 7}, - { 0x00299f20, 2}, - { 0x0029a040, 25}, - { 0x0029a0c8, 7}, - { 0x0029a0ec, 1}, - { 0x0029a0f8, 7}, - { 0x0029a120, 2}, - { 0x0029a240, 25}, - { 0x0029a2c8, 7}, - { 0x0029a2ec, 1}, - { 0x0029a2f8, 7}, - { 0x0029a320, 2}, - { 0x0029a440, 25}, - { 0x0029a4c8, 7}, - { 0x0029a4ec, 1}, - { 0x0029a4f8, 7}, - { 0x0029a520, 2}, - { 0x0029a640, 25}, - { 0x0029a6c8, 7}, - { 0x0029a6ec, 1}, - { 0x0029a6f8, 7}, - { 0x0029a720, 2}, - { 0x0029a840, 25}, - { 0x0029a8c8, 7}, - { 0x0029a8ec, 1}, - { 0x0029a8f8, 7}, - { 0x0029a920, 2}, - { 0x0029aa40, 25}, - { 0x0029aac8, 7}, - { 0x0029aaec, 1}, - { 0x0029aaf8, 7}, - { 0x0029ab20, 2}, - { 0x0029ac40, 25}, - { 0x0029acc8, 7}, - { 0x0029acec, 1}, - { 0x0029acf8, 7}, - { 0x0029ad20, 2}, - { 0x0029ae40, 25}, - { 0x0029aec8, 7}, - { 0x0029aeec, 1}, - { 0x0029aef8, 7}, - { 0x0029af20, 2}, - { 0x0029b040, 25}, - { 0x0029b0c8, 7}, - { 0x0029b0ec, 1}, - { 0x0029b0f8, 7}, - { 0x0029b120, 2}, - { 0x0029b240, 25}, - { 0x0029b2c8, 7}, - { 0x0029b2ec, 1}, - { 0x0029b2f8, 7}, - { 0x0029b320, 2}, - { 0x0029b440, 25}, - { 0x0029b4c8, 7}, - { 0x0029b4ec, 1}, - { 0x0029b4f8, 7}, - { 0x0029b520, 2}, - { 0x0029b640, 25}, - { 0x0029b6c8, 7}, - { 0x0029b6ec, 1}, - { 0x0029b6f8, 7}, - { 0x0029b720, 2}, - { 0x0029b840, 25}, - { 0x0029b8c8, 7}, - { 0x0029b8ec, 1}, - { 0x0029b8f8, 7}, - { 0x0029b920, 2}, - { 0x0029ba40, 25}, - { 0x0029bac8, 7}, - { 0x0029baec, 1}, - { 0x0029baf8, 7}, - { 0x0029bb20, 2}, - { 0x0029bc40, 25}, - { 0x0029bcc8, 7}, - { 0x0029bcec, 1}, - { 0x0029bcf8, 7}, - { 0x0029bd20, 2}, - { 0x0029be40, 25}, - { 0x0029bec8, 7}, - { 0x0029beec, 1}, - { 0x0029bef8, 7}, - { 0x0029bf20, 2}, - { 0x00400500, 1}, - { 0x0040415c, 1}, - { 0x00404498, 1}, - { 0x00405800, 1}, - { 0x00405840, 2}, - { 0x00405850, 1}, - { 0x00405908, 1}, - { 0x00405a00, 1}, - { 0x00405b50, 1}, - { 0x00406024, 5}, - { 0x00407010, 1}, - { 0x00407808, 1}, - { 0x0040803c, 1}, - { 0x00408804, 1}, - { 0x0040880c, 1}, - { 0x00408900, 2}, - { 0x00408910, 1}, - { 0x00408944, 1}, - { 0x00408984, 1}, - { 0x004090a8, 1}, - { 0x004098a0, 1}, - { 0x00409b00, 1}, - { 0x0041000c, 1}, - { 0x00410110, 1}, - { 0x00410184, 1}, - { 0x0041040c, 1}, - { 0x00410510, 1}, - { 0x00410584, 1}, - { 0x0041080c, 1}, - { 0x00410910, 1}, - { 0x00410984, 1}, - { 0x00410c0c, 1}, - { 0x00410d10, 1}, - { 0x00410d84, 1}, - { 0x0041100c, 1}, - { 0x00411110, 1}, - { 0x00411184, 1}, - { 0x0041140c, 1}, - { 0x00411510, 1}, - { 0x00411584, 1}, - { 0x0041180c, 1}, - { 0x00411910, 1}, - { 0x00411984, 1}, - { 0x00411c0c, 1}, - { 0x00411d10, 1}, - { 0x00411d84, 1}, - { 0x0041200c, 1}, - { 0x00412110, 1}, - { 0x00412184, 1}, - { 0x0041240c, 1}, - { 0x00412510, 1}, - { 0x00412584, 1}, - { 0x0041280c, 1}, - { 0x00412910, 1}, - { 0x00412984, 1}, - { 0x00412c0c, 1}, - { 0x00412d10, 1}, - { 0x00412d84, 1}, - { 0x0041300c, 1}, - { 0x00413110, 1}, - { 0x00413184, 1}, - { 0x0041340c, 1}, - { 0x00413510, 1}, - { 0x00413584, 1}, - { 0x0041380c, 1}, - { 0x00413910, 1}, - { 0x00413984, 1}, - { 0x00413c0c, 1}, - { 0x00413d10, 1}, - { 0x00413d84, 1}, - { 0x00418000, 1}, - { 0x00418008, 1}, - { 0x00418380, 2}, - { 0x00418400, 2}, - { 0x004184a0, 1}, - { 0x00418604, 1}, - { 0x00418680, 1}, - { 0x00418704, 1}, - { 0x00418714, 1}, - { 0x00418800, 1}, - { 0x0041881c, 1}, - { 0x00418830, 1}, - { 0x00418884, 1}, - { 0x004188b0, 1}, - { 0x004188c8, 3}, - { 0x004188fc, 1}, - { 0x00418b04, 1}, - { 0x00418c04, 1}, - { 0x00418c10, 8}, - { 0x00418c88, 1}, - { 0x00418d00, 1}, - { 0x00418e00, 1}, - { 0x00418e08, 1}, - { 0x00418e34, 1}, - { 0x00418e40, 4}, - { 0x00418e58, 16}, - { 0x00418f08, 1}, - { 0x00419000, 1}, - { 0x0041900c, 1}, - { 0x00419018, 1}, - { 0x00419854, 1}, - { 0x00419864, 1}, - { 0x00419a04, 2}, - { 0x00419ab0, 1}, - { 0x00419b04, 1}, - { 0x00419b3c, 1}, - { 0x00419b48, 1}, - { 0x00419b50, 1}, - { 0x00419ba0, 2}, - { 0x00419bb0, 1}, - { 0x00419bdc, 1}, - { 0x00419c0c, 1}, - { 0x00419d00, 1}, - { 0x00419d08, 2}, - { 0x00419e08, 1}, - { 0x00419e80, 8}, - { 0x00419ea8, 5}, - { 0x00419f00, 8}, - { 0x00419f28, 5}, - { 0x00419f80, 8}, - { 0x00419fa8, 5}, - { 0x0041a02c, 2}, - { 0x0041a0a8, 1}, - { 0x0041a8a0, 3}, - { 0x0041b014, 1}, - { 0x0041b0cc, 1}, - { 0x0041b1dc, 1}, - { 0x0041b214, 1}, - { 0x0041b2cc, 1}, - { 0x0041b3dc, 1}, - { 0x0041b414, 1}, - { 0x0041b4cc, 1}, - { 0x0041b5dc, 1}, - { 0x0041be0c, 3}, - { 0x0041becc, 1}, - { 0x0041bfdc, 1}, - { 0x0041c054, 1}, - { 0x0041c2b0, 1}, - { 0x0041c304, 1}, - { 0x0041c33c, 1}, - { 0x0041c348, 1}, - { 0x0041c350, 1}, - { 0x0041c3a0, 2}, - { 0x0041c3b0, 1}, - { 0x0041c3dc, 1}, - { 0x0041c40c, 1}, - { 0x0041c500, 1}, - { 0x0041c508, 2}, - { 0x0041c608, 1}, - { 0x0041c680, 8}, - { 0x0041c6a8, 5}, - { 0x0041c700, 8}, - { 0x0041c728, 5}, - { 0x0041c780, 8}, - { 0x0041c7a8, 5}, - { 0x0041c854, 1}, - { 0x0041cab0, 1}, - { 0x0041cb04, 1}, - { 0x0041cb3c, 1}, - { 0x0041cb48, 1}, - { 0x0041cb50, 1}, - { 0x0041cba0, 2}, - { 0x0041cbb0, 1}, - { 0x0041cbdc, 1}, - { 0x0041cc0c, 1}, - { 0x0041cd00, 1}, - { 0x0041cd08, 2}, - { 0x0041ce08, 1}, - { 0x0041ce80, 8}, - { 0x0041cea8, 5}, - { 0x0041cf00, 8}, - { 0x0041cf28, 5}, - { 0x0041cf80, 8}, - { 0x0041cfa8, 5}, - { 0x0041d054, 1}, - { 0x0041d2b0, 1}, - { 0x0041d304, 1}, - { 0x0041d33c, 1}, - { 0x0041d348, 1}, - { 0x0041d350, 1}, - { 0x0041d3a0, 2}, - { 0x0041d3b0, 1}, - { 0x0041d3dc, 1}, - { 0x0041d40c, 1}, - { 0x0041d500, 1}, - { 0x0041d508, 2}, - { 0x0041d608, 1}, - { 0x0041d680, 8}, - { 0x0041d6a8, 5}, - { 0x0041d700, 8}, - { 0x0041d728, 5}, - { 0x0041d780, 8}, - { 0x0041d7a8, 5}, - { 0x0041d854, 1}, - { 0x0041dab0, 1}, - { 0x0041db04, 1}, - { 0x0041db3c, 1}, - { 0x0041db48, 1}, - { 0x0041db50, 1}, - { 0x0041dba0, 2}, - { 0x0041dbb0, 1}, - { 0x0041dbdc, 1}, - { 0x0041dc0c, 1}, - { 0x0041dd00, 1}, - { 0x0041dd08, 2}, - { 0x0041de08, 1}, - { 0x0041de80, 8}, - { 0x0041dea8, 5}, - { 0x0041df00, 8}, - { 0x0041df28, 5}, - { 0x0041df80, 8}, - { 0x0041dfa8, 5}, - { 0x0041e054, 1}, - { 0x0041e2b0, 1}, - { 0x0041e304, 1}, - { 0x0041e33c, 1}, - { 0x0041e348, 1}, - { 0x0041e350, 1}, - { 0x0041e3a0, 2}, - { 0x0041e3b0, 1}, - { 0x0041e3dc, 1}, - { 0x0041e40c, 1}, - { 0x0041e500, 1}, - { 0x0041e508, 2}, - { 0x0041e608, 1}, - { 0x0041e680, 8}, - { 0x0041e6a8, 5}, - { 0x0041e700, 8}, - { 0x0041e728, 5}, - { 0x0041e780, 8}, - { 0x0041e7a8, 5}, - { 0x0041e854, 1}, - { 0x0041eab0, 1}, - { 0x0041eb04, 1}, - { 0x0041eb3c, 1}, - { 0x0041eb48, 1}, - { 0x0041eb50, 1}, - { 0x0041eba0, 2}, - { 0x0041ebb0, 1}, - { 0x0041ebdc, 1}, - { 0x0041ec0c, 1}, - { 0x0041ed00, 1}, - { 0x0041ed08, 2}, - { 0x0041ee08, 1}, - { 0x0041ee80, 8}, - { 0x0041eea8, 5}, - { 0x0041ef00, 8}, - { 0x0041ef28, 5}, - { 0x0041ef80, 8}, - { 0x0041efa8, 5}, - { 0x00481a00, 19}, - { 0x00481b00, 50}, - { 0x00481e00, 50}, - { 0x00481f00, 50}, - { 0x00484200, 19}, - { 0x00484300, 50}, - { 0x00484600, 50}, - { 0x00484700, 50}, - { 0x00484a00, 19}, - { 0x00484b00, 50}, - { 0x00484e00, 50}, - { 0x00484f00, 50}, - { 0x00485200, 19}, - { 0x00485300, 50}, - { 0x00485600, 50}, - { 0x00485700, 50}, - { 0x00485a00, 19}, - { 0x00485b00, 50}, - { 0x00485e00, 50}, - { 0x00485f00, 50}, - { 0x00486200, 19}, - { 0x00486300, 50}, - { 0x00486600, 50}, - { 0x00486700, 50}, - { 0x00486a00, 19}, - { 0x00486b00, 50}, - { 0x00486e00, 50}, - { 0x00486f00, 50}, - { 0x00500384, 1}, - { 0x005004a0, 1}, - { 0x00500604, 1}, - { 0x00500680, 1}, - { 0x00500714, 1}, - { 0x0050081c, 1}, - { 0x00500884, 1}, - { 0x005008b0, 1}, - { 0x005008c8, 3}, - { 0x005008fc, 1}, - { 0x00500b04, 1}, - { 0x00500c04, 1}, - { 0x00500c10, 8}, - { 0x00500c88, 1}, - { 0x00500d00, 1}, - { 0x00500e08, 1}, - { 0x00500f08, 1}, - { 0x00501000, 1}, - { 0x0050100c, 1}, - { 0x00501018, 1}, - { 0x00501854, 1}, - { 0x00501ab0, 1}, - { 0x00501b04, 1}, - { 0x00501b3c, 1}, - { 0x00501b48, 1}, - { 0x00501b50, 1}, - { 0x00501ba0, 2}, - { 0x00501bb0, 1}, - { 0x00501bdc, 1}, - { 0x00501c0c, 1}, - { 0x00501d00, 1}, - { 0x00501d08, 2}, - { 0x00501e08, 1}, - { 0x00501e80, 8}, - { 0x00501ea8, 5}, - { 0x00501f00, 8}, - { 0x00501f28, 5}, - { 0x00501f80, 8}, - { 0x00501fa8, 5}, - { 0x0050202c, 2}, - { 0x005020a8, 1}, - { 0x005028a0, 3}, - { 0x00503014, 1}, - { 0x005030cc, 1}, - { 0x005031dc, 1}, - { 0x00503214, 1}, - { 0x005032cc, 1}, - { 0x005033dc, 1}, - { 0x00503414, 1}, - { 0x005034cc, 1}, - { 0x005035dc, 1}, - { 0x00503e14, 1}, - { 0x00503ecc, 1}, - { 0x00503fdc, 1}, - { 0x00504054, 1}, - { 0x005042b0, 1}, - { 0x00504304, 1}, - { 0x0050433c, 1}, - { 0x00504348, 1}, - { 0x00504350, 1}, - { 0x005043a0, 2}, - { 0x005043b0, 1}, - { 0x005043dc, 1}, - { 0x0050440c, 1}, - { 0x00504500, 1}, - { 0x00504508, 2}, - { 0x00504608, 1}, - { 0x00504680, 8}, - { 0x005046a8, 5}, - { 0x00504700, 8}, - { 0x00504728, 5}, - { 0x00504780, 8}, - { 0x005047a8, 5}, - { 0x00504854, 1}, - { 0x00504ab0, 1}, - { 0x00504b04, 1}, - { 0x00504b3c, 1}, - { 0x00504b48, 1}, - { 0x00504b50, 1}, - { 0x00504ba0, 2}, - { 0x00504bb0, 1}, - { 0x00504bdc, 1}, - { 0x00504c0c, 1}, - { 0x00504d00, 1}, - { 0x00504d08, 2}, - { 0x00504e08, 1}, - { 0x00504e80, 8}, - { 0x00504ea8, 5}, - { 0x00504f00, 8}, - { 0x00504f28, 5}, - { 0x00504f80, 8}, - { 0x00504fa8, 5}, - { 0x00505054, 1}, - { 0x005052b0, 1}, - { 0x00505304, 1}, - { 0x0050533c, 1}, - { 0x00505348, 1}, - { 0x00505350, 1}, - { 0x005053a0, 2}, - { 0x005053b0, 1}, - { 0x005053dc, 1}, - { 0x0050540c, 1}, - { 0x00505500, 1}, - { 0x00505508, 2}, - { 0x00505608, 1}, - { 0x00505680, 8}, - { 0x005056a8, 5}, - { 0x00505700, 8}, - { 0x00505728, 5}, - { 0x00505780, 8}, - { 0x005057a8, 5}, - { 0x00505854, 1}, - { 0x00505ab0, 1}, - { 0x00505b04, 1}, - { 0x00505b3c, 1}, - { 0x00505b48, 1}, - { 0x00505b50, 1}, - { 0x00505ba0, 2}, - { 0x00505bb0, 1}, - { 0x00505bdc, 1}, - { 0x00505c0c, 1}, - { 0x00505d00, 1}, - { 0x00505d08, 2}, - { 0x00505e08, 1}, - { 0x00505e80, 8}, - { 0x00505ea8, 5}, - { 0x00505f00, 8}, - { 0x00505f28, 5}, - { 0x00505f80, 8}, - { 0x00505fa8, 5}, - { 0x00506054, 1}, - { 0x005062b0, 1}, - { 0x00506304, 1}, - { 0x0050633c, 1}, - { 0x00506348, 1}, - { 0x00506350, 1}, - { 0x005063a0, 2}, - { 0x005063b0, 1}, - { 0x005063dc, 1}, - { 0x0050640c, 1}, - { 0x00506500, 1}, - { 0x00506508, 2}, - { 0x00506608, 1}, - { 0x00506680, 8}, - { 0x005066a8, 5}, - { 0x00506700, 8}, - { 0x00506728, 5}, - { 0x00506780, 8}, - { 0x005067a8, 5}, - { 0x00506854, 1}, - { 0x00506ab0, 1}, - { 0x00506b04, 1}, - { 0x00506b3c, 1}, - { 0x00506b48, 1}, - { 0x00506b50, 1}, - { 0x00506ba0, 2}, - { 0x00506bb0, 1}, - { 0x00506bdc, 1}, - { 0x00506c0c, 1}, - { 0x00506d00, 1}, - { 0x00506d08, 2}, - { 0x00506e08, 1}, - { 0x00506e80, 8}, - { 0x00506ea8, 5}, - { 0x00506f00, 8}, - { 0x00506f28, 5}, - { 0x00506f80, 8}, - { 0x00506fa8, 5}, - { 0x00508384, 1}, - { 0x005084a0, 1}, - { 0x00508604, 1}, - { 0x00508680, 1}, - { 0x00508714, 1}, - { 0x0050881c, 1}, - { 0x00508884, 1}, - { 0x005088b0, 1}, - { 0x005088c8, 2}, - { 0x00508b04, 1}, - { 0x00508c04, 1}, - { 0x00508c10, 8}, - { 0x00508c88, 1}, - { 0x00508d00, 1}, - { 0x00508e08, 1}, - { 0x00508f08, 1}, - { 0x00509000, 1}, - { 0x0050900c, 1}, - { 0x00509018, 1}, - { 0x00509854, 1}, - { 0x00509ab0, 1}, - { 0x00509b04, 1}, - { 0x00509b3c, 1}, - { 0x00509b48, 1}, - { 0x00509b50, 1}, - { 0x00509ba0, 2}, - { 0x00509bb0, 1}, - { 0x00509bdc, 1}, - { 0x00509c0c, 1}, - { 0x00509d00, 1}, - { 0x00509d08, 2}, - { 0x00509e08, 1}, - { 0x00509e80, 8}, - { 0x00509ea8, 5}, - { 0x00509f00, 8}, - { 0x00509f28, 5}, - { 0x00509f80, 8}, - { 0x00509fa8, 5}, - { 0x0050a02c, 2}, - { 0x0050a0a8, 1}, - { 0x0050a8a0, 3}, - { 0x0050b014, 1}, - { 0x0050b0cc, 1}, - { 0x0050b1dc, 1}, - { 0x0050b214, 1}, - { 0x0050b2cc, 1}, - { 0x0050b3dc, 1}, - { 0x0050b414, 1}, - { 0x0050b4cc, 1}, - { 0x0050b5dc, 1}, - { 0x0050be14, 1}, - { 0x0050becc, 1}, - { 0x0050bfdc, 1}, - { 0x0050c054, 1}, - { 0x0050c2b0, 1}, - { 0x0050c304, 1}, - { 0x0050c33c, 1}, - { 0x0050c348, 1}, - { 0x0050c350, 1}, - { 0x0050c3a0, 2}, - { 0x0050c3b0, 1}, - { 0x0050c3dc, 1}, - { 0x0050c40c, 1}, - { 0x0050c500, 1}, - { 0x0050c508, 2}, - { 0x0050c608, 1}, - { 0x0050c680, 8}, - { 0x0050c6a8, 5}, - { 0x0050c700, 8}, - { 0x0050c728, 5}, - { 0x0050c780, 8}, - { 0x0050c7a8, 5}, - { 0x0050c854, 1}, - { 0x0050cab0, 1}, - { 0x0050cb04, 1}, - { 0x0050cb3c, 1}, - { 0x0050cb48, 1}, - { 0x0050cb50, 1}, - { 0x0050cba0, 2}, - { 0x0050cbb0, 1}, - { 0x0050cbdc, 1}, - { 0x0050cc0c, 1}, - { 0x0050cd00, 1}, - { 0x0050cd08, 2}, - { 0x0050ce08, 1}, - { 0x0050ce80, 8}, - { 0x0050cea8, 5}, - { 0x0050cf00, 8}, - { 0x0050cf28, 5}, - { 0x0050cf80, 8}, - { 0x0050cfa8, 5}, - { 0x0050d054, 1}, - { 0x0050d2b0, 1}, - { 0x0050d304, 1}, - { 0x0050d33c, 1}, - { 0x0050d348, 1}, - { 0x0050d350, 1}, - { 0x0050d3a0, 2}, - { 0x0050d3b0, 1}, - { 0x0050d3dc, 1}, - { 0x0050d40c, 1}, - { 0x0050d500, 1}, - { 0x0050d508, 2}, - { 0x0050d608, 1}, - { 0x0050d680, 8}, - { 0x0050d6a8, 5}, - { 0x0050d700, 8}, - { 0x0050d728, 5}, - { 0x0050d780, 8}, - { 0x0050d7a8, 5}, - { 0x0050d854, 1}, - { 0x0050dab0, 1}, - { 0x0050db04, 1}, - { 0x0050db3c, 1}, - { 0x0050db48, 1}, - { 0x0050db50, 1}, - { 0x0050dba0, 2}, - { 0x0050dbb0, 1}, - { 0x0050dbdc, 1}, - { 0x0050dc0c, 1}, - { 0x0050dd00, 1}, - { 0x0050dd08, 2}, - { 0x0050de08, 1}, - { 0x0050de80, 8}, - { 0x0050dea8, 5}, - { 0x0050df00, 8}, - { 0x0050df28, 5}, - { 0x0050df80, 8}, - { 0x0050dfa8, 5}, - { 0x0050e054, 1}, - { 0x0050e2b0, 1}, - { 0x0050e304, 1}, - { 0x0050e33c, 1}, - { 0x0050e348, 1}, - { 0x0050e350, 1}, - { 0x0050e3a0, 2}, - { 0x0050e3b0, 1}, - { 0x0050e3dc, 1}, - { 0x0050e40c, 1}, - { 0x0050e500, 1}, - { 0x0050e508, 2}, - { 0x0050e608, 1}, - { 0x0050e680, 8}, - { 0x0050e6a8, 5}, - { 0x0050e700, 8}, - { 0x0050e728, 5}, - { 0x0050e780, 8}, - { 0x0050e7a8, 5}, - { 0x0050e854, 1}, - { 0x0050eab0, 1}, - { 0x0050eb04, 1}, - { 0x0050eb3c, 1}, - { 0x0050eb48, 1}, - { 0x0050eb50, 1}, - { 0x0050eba0, 2}, - { 0x0050ebb0, 1}, - { 0x0050ebdc, 1}, - { 0x0050ec0c, 1}, - { 0x0050ed00, 1}, - { 0x0050ed08, 2}, - { 0x0050ee08, 1}, - { 0x0050ee80, 8}, - { 0x0050eea8, 5}, - { 0x0050ef00, 8}, - { 0x0050ef28, 5}, - { 0x0050ef80, 8}, - { 0x0050efa8, 5}, - { 0x00510384, 1}, - { 0x005104a0, 1}, - { 0x00510604, 1}, - { 0x00510680, 1}, - { 0x00510714, 1}, - { 0x0051081c, 1}, - { 0x00510884, 1}, - { 0x005108b0, 1}, - { 0x005108c8, 2}, - { 0x00510b04, 1}, - { 0x00510c04, 1}, - { 0x00510c10, 8}, - { 0x00510c88, 1}, - { 0x00510d00, 1}, - { 0x00510e08, 1}, - { 0x00510f08, 1}, - { 0x00511000, 1}, - { 0x0051100c, 1}, - { 0x00511018, 1}, - { 0x00511854, 1}, - { 0x00511ab0, 1}, - { 0x00511b04, 1}, - { 0x00511b3c, 1}, - { 0x00511b48, 1}, - { 0x00511b50, 1}, - { 0x00511ba0, 2}, - { 0x00511bb0, 1}, - { 0x00511bdc, 1}, - { 0x00511c0c, 1}, - { 0x00511d00, 1}, - { 0x00511d08, 2}, - { 0x00511e08, 1}, - { 0x00511e80, 8}, - { 0x00511ea8, 5}, - { 0x00511f00, 8}, - { 0x00511f28, 5}, - { 0x00511f80, 8}, - { 0x00511fa8, 5}, - { 0x0051202c, 2}, - { 0x005120a8, 1}, - { 0x005128a0, 3}, - { 0x00513014, 1}, - { 0x005130cc, 1}, - { 0x005131dc, 1}, - { 0x00513214, 1}, - { 0x005132cc, 1}, - { 0x005133dc, 1}, - { 0x00513414, 1}, - { 0x005134cc, 1}, - { 0x005135dc, 1}, - { 0x00513e14, 1}, - { 0x00513ecc, 1}, - { 0x00513fdc, 1}, - { 0x00514054, 1}, - { 0x005142b0, 1}, - { 0x00514304, 1}, - { 0x0051433c, 1}, - { 0x00514348, 1}, - { 0x00514350, 1}, - { 0x005143a0, 2}, - { 0x005143b0, 1}, - { 0x005143dc, 1}, - { 0x0051440c, 1}, - { 0x00514500, 1}, - { 0x00514508, 2}, - { 0x00514608, 1}, - { 0x00514680, 8}, - { 0x005146a8, 5}, - { 0x00514700, 8}, - { 0x00514728, 5}, - { 0x00514780, 8}, - { 0x005147a8, 5}, - { 0x00514854, 1}, - { 0x00514ab0, 1}, - { 0x00514b04, 1}, - { 0x00514b3c, 1}, - { 0x00514b48, 1}, - { 0x00514b50, 1}, - { 0x00514ba0, 2}, - { 0x00514bb0, 1}, - { 0x00514bdc, 1}, - { 0x00514c0c, 1}, - { 0x00514d00, 1}, - { 0x00514d08, 2}, - { 0x00514e08, 1}, - { 0x00514e80, 8}, - { 0x00514ea8, 5}, - { 0x00514f00, 8}, - { 0x00514f28, 5}, - { 0x00514f80, 8}, - { 0x00514fa8, 5}, - { 0x00515054, 1}, - { 0x005152b0, 1}, - { 0x00515304, 1}, - { 0x0051533c, 1}, - { 0x00515348, 1}, - { 0x00515350, 1}, - { 0x005153a0, 2}, - { 0x005153b0, 1}, - { 0x005153dc, 1}, - { 0x0051540c, 1}, - { 0x00515500, 1}, - { 0x00515508, 2}, - { 0x00515608, 1}, - { 0x00515680, 8}, - { 0x005156a8, 5}, - { 0x00515700, 8}, - { 0x00515728, 5}, - { 0x00515780, 8}, - { 0x005157a8, 5}, - { 0x00515854, 1}, - { 0x00515ab0, 1}, - { 0x00515b04, 1}, - { 0x00515b3c, 1}, - { 0x00515b48, 1}, - { 0x00515b50, 1}, - { 0x00515ba0, 2}, - { 0x00515bb0, 1}, - { 0x00515bdc, 1}, - { 0x00515c0c, 1}, - { 0x00515d00, 1}, - { 0x00515d08, 2}, - { 0x00515e08, 1}, - { 0x00515e80, 8}, - { 0x00515ea8, 5}, - { 0x00515f00, 8}, - { 0x00515f28, 5}, - { 0x00515f80, 8}, - { 0x00515fa8, 5}, - { 0x00516054, 1}, - { 0x005162b0, 1}, - { 0x00516304, 1}, - { 0x0051633c, 1}, - { 0x00516348, 1}, - { 0x00516350, 1}, - { 0x005163a0, 2}, - { 0x005163b0, 1}, - { 0x005163dc, 1}, - { 0x0051640c, 1}, - { 0x00516500, 1}, - { 0x00516508, 2}, - { 0x00516608, 1}, - { 0x00516680, 8}, - { 0x005166a8, 5}, - { 0x00516700, 8}, - { 0x00516728, 5}, - { 0x00516780, 8}, - { 0x005167a8, 5}, - { 0x00516854, 1}, - { 0x00516ab0, 1}, - { 0x00516b04, 1}, - { 0x00516b3c, 1}, - { 0x00516b48, 1}, - { 0x00516b50, 1}, - { 0x00516ba0, 2}, - { 0x00516bb0, 1}, - { 0x00516bdc, 1}, - { 0x00516c0c, 1}, - { 0x00516d00, 1}, - { 0x00516d08, 2}, - { 0x00516e08, 1}, - { 0x00516e80, 8}, - { 0x00516ea8, 5}, - { 0x00516f00, 8}, - { 0x00516f28, 5}, - { 0x00516f80, 8}, - { 0x00516fa8, 5}, - { 0x00518384, 1}, - { 0x005184a0, 1}, - { 0x00518604, 1}, - { 0x00518680, 1}, - { 0x00518714, 1}, - { 0x0051881c, 1}, - { 0x00518884, 1}, - { 0x005188b0, 1}, - { 0x005188c8, 2}, - { 0x00518b04, 1}, - { 0x00518c04, 1}, - { 0x00518c10, 8}, - { 0x00518c88, 1}, - { 0x00518d00, 1}, - { 0x00518e08, 1}, - { 0x00518f08, 1}, - { 0x00519000, 1}, - { 0x0051900c, 1}, - { 0x00519018, 1}, - { 0x00519854, 1}, - { 0x00519ab0, 1}, - { 0x00519b04, 1}, - { 0x00519b3c, 1}, - { 0x00519b48, 1}, - { 0x00519b50, 1}, - { 0x00519ba0, 2}, - { 0x00519bb0, 1}, - { 0x00519bdc, 1}, - { 0x00519c0c, 1}, - { 0x00519d00, 1}, - { 0x00519d08, 2}, - { 0x00519e08, 1}, - { 0x00519e80, 8}, - { 0x00519ea8, 5}, - { 0x00519f00, 8}, - { 0x00519f28, 5}, - { 0x00519f80, 8}, - { 0x00519fa8, 5}, - { 0x0051a02c, 2}, - { 0x0051a0a8, 1}, - { 0x0051a8a0, 3}, - { 0x0051b014, 1}, - { 0x0051b0cc, 1}, - { 0x0051b1dc, 1}, - { 0x0051b214, 1}, - { 0x0051b2cc, 1}, - { 0x0051b3dc, 1}, - { 0x0051b414, 1}, - { 0x0051b4cc, 1}, - { 0x0051b5dc, 1}, - { 0x0051be14, 1}, - { 0x0051becc, 1}, - { 0x0051bfdc, 1}, - { 0x0051c054, 1}, - { 0x0051c2b0, 1}, - { 0x0051c304, 1}, - { 0x0051c33c, 1}, - { 0x0051c348, 1}, - { 0x0051c350, 1}, - { 0x0051c3a0, 2}, - { 0x0051c3b0, 1}, - { 0x0051c3dc, 1}, - { 0x0051c40c, 1}, - { 0x0051c500, 1}, - { 0x0051c508, 2}, - { 0x0051c608, 1}, - { 0x0051c680, 8}, - { 0x0051c6a8, 5}, - { 0x0051c700, 8}, - { 0x0051c728, 5}, - { 0x0051c780, 8}, - { 0x0051c7a8, 5}, - { 0x0051c854, 1}, - { 0x0051cab0, 1}, - { 0x0051cb04, 1}, - { 0x0051cb3c, 1}, - { 0x0051cb48, 1}, - { 0x0051cb50, 1}, - { 0x0051cba0, 2}, - { 0x0051cbb0, 1}, - { 0x0051cbdc, 1}, - { 0x0051cc0c, 1}, - { 0x0051cd00, 1}, - { 0x0051cd08, 2}, - { 0x0051ce08, 1}, - { 0x0051ce80, 8}, - { 0x0051cea8, 5}, - { 0x0051cf00, 8}, - { 0x0051cf28, 5}, - { 0x0051cf80, 8}, - { 0x0051cfa8, 5}, - { 0x0051d054, 1}, - { 0x0051d2b0, 1}, - { 0x0051d304, 1}, - { 0x0051d33c, 1}, - { 0x0051d348, 1}, - { 0x0051d350, 1}, - { 0x0051d3a0, 2}, - { 0x0051d3b0, 1}, - { 0x0051d3dc, 1}, - { 0x0051d40c, 1}, - { 0x0051d500, 1}, - { 0x0051d508, 2}, - { 0x0051d608, 1}, - { 0x0051d680, 8}, - { 0x0051d6a8, 5}, - { 0x0051d700, 8}, - { 0x0051d728, 5}, - { 0x0051d780, 8}, - { 0x0051d7a8, 5}, - { 0x0051d854, 1}, - { 0x0051dab0, 1}, - { 0x0051db04, 1}, - { 0x0051db3c, 1}, - { 0x0051db48, 1}, - { 0x0051db50, 1}, - { 0x0051dba0, 2}, - { 0x0051dbb0, 1}, - { 0x0051dbdc, 1}, - { 0x0051dc0c, 1}, - { 0x0051dd00, 1}, - { 0x0051dd08, 2}, - { 0x0051de08, 1}, - { 0x0051de80, 8}, - { 0x0051dea8, 5}, - { 0x0051df00, 8}, - { 0x0051df28, 5}, - { 0x0051df80, 8}, - { 0x0051dfa8, 5}, - { 0x0051e054, 1}, - { 0x0051e2b0, 1}, - { 0x0051e304, 1}, - { 0x0051e33c, 1}, - { 0x0051e348, 1}, - { 0x0051e350, 1}, - { 0x0051e3a0, 2}, - { 0x0051e3b0, 1}, - { 0x0051e3dc, 1}, - { 0x0051e40c, 1}, - { 0x0051e500, 1}, - { 0x0051e508, 2}, - { 0x0051e608, 1}, - { 0x0051e680, 8}, - { 0x0051e6a8, 5}, - { 0x0051e700, 8}, - { 0x0051e728, 5}, - { 0x0051e780, 8}, - { 0x0051e7a8, 5}, - { 0x0051e854, 1}, - { 0x0051eab0, 1}, - { 0x0051eb04, 1}, - { 0x0051eb3c, 1}, - { 0x0051eb48, 1}, - { 0x0051eb50, 1}, - { 0x0051eba0, 2}, - { 0x0051ebb0, 1}, - { 0x0051ebdc, 1}, - { 0x0051ec0c, 1}, - { 0x0051ed00, 1}, - { 0x0051ed08, 2}, - { 0x0051ee08, 1}, - { 0x0051ee80, 8}, - { 0x0051eea8, 5}, - { 0x0051ef00, 8}, - { 0x0051ef28, 5}, - { 0x0051ef80, 8}, - { 0x0051efa8, 5}, - { 0x00520384, 1}, - { 0x005204a0, 1}, - { 0x00520604, 1}, - { 0x00520680, 1}, - { 0x00520714, 1}, - { 0x0052081c, 1}, - { 0x00520884, 1}, - { 0x005208b0, 1}, - { 0x005208c8, 2}, - { 0x00520b04, 1}, - { 0x00520c04, 1}, - { 0x00520c10, 8}, - { 0x00520c88, 1}, - { 0x00520d00, 1}, - { 0x00520e08, 1}, - { 0x00520f08, 1}, - { 0x00521000, 1}, - { 0x0052100c, 1}, - { 0x00521018, 1}, - { 0x00521854, 1}, - { 0x00521ab0, 1}, - { 0x00521b04, 1}, - { 0x00521b3c, 1}, - { 0x00521b48, 1}, - { 0x00521b50, 1}, - { 0x00521ba0, 2}, - { 0x00521bb0, 1}, - { 0x00521bdc, 1}, - { 0x00521c0c, 1}, - { 0x00521d00, 1}, - { 0x00521d08, 2}, - { 0x00521e08, 1}, - { 0x00521e80, 8}, - { 0x00521ea8, 5}, - { 0x00521f00, 8}, - { 0x00521f28, 5}, - { 0x00521f80, 8}, - { 0x00521fa8, 5}, - { 0x0052202c, 2}, - { 0x005220a8, 1}, - { 0x005228a0, 3}, - { 0x00523014, 1}, - { 0x005230cc, 1}, - { 0x005231dc, 1}, - { 0x00523214, 1}, - { 0x005232cc, 1}, - { 0x005233dc, 1}, - { 0x00523414, 1}, - { 0x005234cc, 1}, - { 0x005235dc, 1}, - { 0x00523e14, 1}, - { 0x00523ecc, 1}, - { 0x00523fdc, 1}, - { 0x00524054, 1}, - { 0x005242b0, 1}, - { 0x00524304, 1}, - { 0x0052433c, 1}, - { 0x00524348, 1}, - { 0x00524350, 1}, - { 0x005243a0, 2}, - { 0x005243b0, 1}, - { 0x005243dc, 1}, - { 0x0052440c, 1}, - { 0x00524500, 1}, - { 0x00524508, 2}, - { 0x00524608, 1}, - { 0x00524680, 8}, - { 0x005246a8, 5}, - { 0x00524700, 8}, - { 0x00524728, 5}, - { 0x00524780, 8}, - { 0x005247a8, 5}, - { 0x00524854, 1}, - { 0x00524ab0, 1}, - { 0x00524b04, 1}, - { 0x00524b3c, 1}, - { 0x00524b48, 1}, - { 0x00524b50, 1}, - { 0x00524ba0, 2}, - { 0x00524bb0, 1}, - { 0x00524bdc, 1}, - { 0x00524c0c, 1}, - { 0x00524d00, 1}, - { 0x00524d08, 2}, - { 0x00524e08, 1}, - { 0x00524e80, 8}, - { 0x00524ea8, 5}, - { 0x00524f00, 8}, - { 0x00524f28, 5}, - { 0x00524f80, 8}, - { 0x00524fa8, 5}, - { 0x00525054, 1}, - { 0x005252b0, 1}, - { 0x00525304, 1}, - { 0x0052533c, 1}, - { 0x00525348, 1}, - { 0x00525350, 1}, - { 0x005253a0, 2}, - { 0x005253b0, 1}, - { 0x005253dc, 1}, - { 0x0052540c, 1}, - { 0x00525500, 1}, - { 0x00525508, 2}, - { 0x00525608, 1}, - { 0x00525680, 8}, - { 0x005256a8, 5}, - { 0x00525700, 8}, - { 0x00525728, 5}, - { 0x00525780, 8}, - { 0x005257a8, 5}, - { 0x00525854, 1}, - { 0x00525ab0, 1}, - { 0x00525b04, 1}, - { 0x00525b3c, 1}, - { 0x00525b48, 1}, - { 0x00525b50, 1}, - { 0x00525ba0, 2}, - { 0x00525bb0, 1}, - { 0x00525bdc, 1}, - { 0x00525c0c, 1}, - { 0x00525d00, 1}, - { 0x00525d08, 2}, - { 0x00525e08, 1}, - { 0x00525e80, 8}, - { 0x00525ea8, 5}, - { 0x00525f00, 8}, - { 0x00525f28, 5}, - { 0x00525f80, 8}, - { 0x00525fa8, 5}, - { 0x00526054, 1}, - { 0x005262b0, 1}, - { 0x00526304, 1}, - { 0x0052633c, 1}, - { 0x00526348, 1}, - { 0x00526350, 1}, - { 0x005263a0, 2}, - { 0x005263b0, 1}, - { 0x005263dc, 1}, - { 0x0052640c, 1}, - { 0x00526500, 1}, - { 0x00526508, 2}, - { 0x00526608, 1}, - { 0x00526680, 8}, - { 0x005266a8, 5}, - { 0x00526700, 8}, - { 0x00526728, 5}, - { 0x00526780, 8}, - { 0x005267a8, 5}, - { 0x00526854, 1}, - { 0x00526ab0, 1}, - { 0x00526b04, 1}, - { 0x00526b3c, 1}, - { 0x00526b48, 1}, - { 0x00526b50, 1}, - { 0x00526ba0, 2}, - { 0x00526bb0, 1}, - { 0x00526bdc, 1}, - { 0x00526c0c, 1}, - { 0x00526d00, 1}, - { 0x00526d08, 2}, - { 0x00526e08, 1}, - { 0x00526e80, 8}, - { 0x00526ea8, 5}, - { 0x00526f00, 8}, - { 0x00526f28, 5}, - { 0x00526f80, 8}, - { 0x00526fa8, 5}, - { 0x00528384, 1}, - { 0x005284a0, 1}, - { 0x00528604, 1}, - { 0x00528680, 1}, - { 0x00528714, 1}, - { 0x0052881c, 1}, - { 0x00528884, 1}, - { 0x005288b0, 1}, - { 0x005288c8, 2}, - { 0x00528b04, 1}, - { 0x00528c04, 1}, - { 0x00528c10, 8}, - { 0x00528c88, 1}, - { 0x00528d00, 1}, - { 0x00528e08, 1}, - { 0x00528f08, 1}, - { 0x00529000, 1}, - { 0x0052900c, 1}, - { 0x00529018, 1}, - { 0x00529854, 1}, - { 0x00529ab0, 1}, - { 0x00529b04, 1}, - { 0x00529b3c, 1}, - { 0x00529b48, 1}, - { 0x00529b50, 1}, - { 0x00529ba0, 2}, - { 0x00529bb0, 1}, - { 0x00529bdc, 1}, - { 0x00529c0c, 1}, - { 0x00529d00, 1}, - { 0x00529d08, 2}, - { 0x00529e08, 1}, - { 0x00529e80, 8}, - { 0x00529ea8, 5}, - { 0x00529f00, 8}, - { 0x00529f28, 5}, - { 0x00529f80, 8}, - { 0x00529fa8, 5}, - { 0x0052a02c, 2}, - { 0x0052a0a8, 1}, - { 0x0052a8a0, 3}, - { 0x0052b014, 1}, - { 0x0052b0cc, 1}, - { 0x0052b1dc, 1}, - { 0x0052b214, 1}, - { 0x0052b2cc, 1}, - { 0x0052b3dc, 1}, - { 0x0052b414, 1}, - { 0x0052b4cc, 1}, - { 0x0052b5dc, 1}, - { 0x0052be14, 1}, - { 0x0052becc, 1}, - { 0x0052bfdc, 1}, - { 0x0052c054, 1}, - { 0x0052c2b0, 1}, - { 0x0052c304, 1}, - { 0x0052c33c, 1}, - { 0x0052c348, 1}, - { 0x0052c350, 1}, - { 0x0052c3a0, 2}, - { 0x0052c3b0, 1}, - { 0x0052c3dc, 1}, - { 0x0052c40c, 1}, - { 0x0052c500, 1}, - { 0x0052c508, 2}, - { 0x0052c608, 1}, - { 0x0052c680, 8}, - { 0x0052c6a8, 5}, - { 0x0052c700, 8}, - { 0x0052c728, 5}, - { 0x0052c780, 8}, - { 0x0052c7a8, 5}, - { 0x0052c854, 1}, - { 0x0052cab0, 1}, - { 0x0052cb04, 1}, - { 0x0052cb3c, 1}, - { 0x0052cb48, 1}, - { 0x0052cb50, 1}, - { 0x0052cba0, 2}, - { 0x0052cbb0, 1}, - { 0x0052cbdc, 1}, - { 0x0052cc0c, 1}, - { 0x0052cd00, 1}, - { 0x0052cd08, 2}, - { 0x0052ce08, 1}, - { 0x0052ce80, 8}, - { 0x0052cea8, 5}, - { 0x0052cf00, 8}, - { 0x0052cf28, 5}, - { 0x0052cf80, 8}, - { 0x0052cfa8, 5}, - { 0x0052d054, 1}, - { 0x0052d2b0, 1}, - { 0x0052d304, 1}, - { 0x0052d33c, 1}, - { 0x0052d348, 1}, - { 0x0052d350, 1}, - { 0x0052d3a0, 2}, - { 0x0052d3b0, 1}, - { 0x0052d3dc, 1}, - { 0x0052d40c, 1}, - { 0x0052d500, 1}, - { 0x0052d508, 2}, - { 0x0052d608, 1}, - { 0x0052d680, 8}, - { 0x0052d6a8, 5}, - { 0x0052d700, 8}, - { 0x0052d728, 5}, - { 0x0052d780, 8}, - { 0x0052d7a8, 5}, - { 0x0052d854, 1}, - { 0x0052dab0, 1}, - { 0x0052db04, 1}, - { 0x0052db3c, 1}, - { 0x0052db48, 1}, - { 0x0052db50, 1}, - { 0x0052dba0, 2}, - { 0x0052dbb0, 1}, - { 0x0052dbdc, 1}, - { 0x0052dc0c, 1}, - { 0x0052dd00, 1}, - { 0x0052dd08, 2}, - { 0x0052de08, 1}, - { 0x0052de80, 8}, - { 0x0052dea8, 5}, - { 0x0052df00, 8}, - { 0x0052df28, 5}, - { 0x0052df80, 8}, - { 0x0052dfa8, 5}, - { 0x0052e054, 1}, - { 0x0052e2b0, 1}, - { 0x0052e304, 1}, - { 0x0052e33c, 1}, - { 0x0052e348, 1}, - { 0x0052e350, 1}, - { 0x0052e3a0, 2}, - { 0x0052e3b0, 1}, - { 0x0052e3dc, 1}, - { 0x0052e40c, 1}, - { 0x0052e500, 1}, - { 0x0052e508, 2}, - { 0x0052e608, 1}, - { 0x0052e680, 8}, - { 0x0052e6a8, 5}, - { 0x0052e700, 8}, - { 0x0052e728, 5}, - { 0x0052e780, 8}, - { 0x0052e7a8, 5}, - { 0x0052e854, 1}, - { 0x0052eab0, 1}, - { 0x0052eb04, 1}, - { 0x0052eb3c, 1}, - { 0x0052eb48, 1}, - { 0x0052eb50, 1}, - { 0x0052eba0, 2}, - { 0x0052ebb0, 1}, - { 0x0052ebdc, 1}, - { 0x0052ec0c, 1}, - { 0x0052ed00, 1}, - { 0x0052ed08, 2}, - { 0x0052ee08, 1}, - { 0x0052ee80, 8}, - { 0x0052eea8, 5}, - { 0x0052ef00, 8}, - { 0x0052ef28, 5}, - { 0x0052ef80, 8}, - { 0x0052efa8, 5}, - { 0x00581a00, 19}, - { 0x00581b00, 50}, - { 0x00581e00, 50}, - { 0x00581f00, 50}, - { 0x00584200, 19}, - { 0x00584300, 50}, - { 0x00584600, 50}, - { 0x00584700, 50}, - { 0x00584a00, 19}, - { 0x00584b00, 50}, - { 0x00584e00, 50}, - { 0x00584f00, 50}, - { 0x00585200, 19}, - { 0x00585300, 50}, - { 0x00585600, 50}, - { 0x00585700, 50}, - { 0x00585a00, 19}, - { 0x00585b00, 50}, - { 0x00585e00, 50}, - { 0x00585f00, 50}, - { 0x00586200, 19}, - { 0x00586300, 50}, - { 0x00586600, 50}, - { 0x00586700, 50}, - { 0x00586a00, 19}, - { 0x00586b00, 50}, - { 0x00586e00, 50}, - { 0x00586f00, 50}, - { 0x00589a00, 19}, - { 0x00589b00, 50}, - { 0x00589e00, 50}, - { 0x00589f00, 50}, - { 0x0058c200, 19}, - { 0x0058c300, 50}, - { 0x0058c600, 50}, - { 0x0058c700, 50}, - { 0x0058ca00, 19}, - { 0x0058cb00, 50}, - { 0x0058ce00, 50}, - { 0x0058cf00, 50}, - { 0x0058d200, 19}, - { 0x0058d300, 50}, - { 0x0058d600, 50}, - { 0x0058d700, 50}, - { 0x0058da00, 19}, - { 0x0058db00, 50}, - { 0x0058de00, 50}, - { 0x0058df00, 50}, - { 0x0058e200, 19}, - { 0x0058e300, 50}, - { 0x0058e600, 50}, - { 0x0058e700, 50}, - { 0x0058ea00, 19}, - { 0x0058eb00, 50}, - { 0x0058ee00, 50}, - { 0x0058ef00, 50}, - { 0x00591a00, 19}, - { 0x00591b00, 50}, - { 0x00591e00, 50}, - { 0x00591f00, 50}, - { 0x00594200, 19}, - { 0x00594300, 50}, - { 0x00594600, 50}, - { 0x00594700, 50}, - { 0x00594a00, 19}, - { 0x00594b00, 50}, - { 0x00594e00, 50}, - { 0x00594f00, 50}, - { 0x00595200, 19}, - { 0x00595300, 50}, - { 0x00595600, 50}, - { 0x00595700, 50}, - { 0x00595a00, 19}, - { 0x00595b00, 50}, - { 0x00595e00, 50}, - { 0x00595f00, 50}, - { 0x00596200, 19}, - { 0x00596300, 50}, - { 0x00596600, 50}, - { 0x00596700, 50}, - { 0x00596a00, 19}, - { 0x00596b00, 50}, - { 0x00596e00, 50}, - { 0x00596f00, 50}, - { 0x00599a00, 19}, - { 0x00599b00, 50}, - { 0x00599e00, 50}, - { 0x00599f00, 50}, - { 0x0059c200, 19}, - { 0x0059c300, 50}, - { 0x0059c600, 50}, - { 0x0059c700, 50}, - { 0x0059ca00, 19}, - { 0x0059cb00, 50}, - { 0x0059ce00, 50}, - { 0x0059cf00, 50}, - { 0x0059d200, 19}, - { 0x0059d300, 50}, - { 0x0059d600, 50}, - { 0x0059d700, 50}, - { 0x0059da00, 19}, - { 0x0059db00, 50}, - { 0x0059de00, 50}, - { 0x0059df00, 50}, - { 0x0059e200, 19}, - { 0x0059e300, 50}, - { 0x0059e600, 50}, - { 0x0059e700, 50}, - { 0x0059ea00, 19}, - { 0x0059eb00, 50}, - { 0x0059ee00, 50}, - { 0x0059ef00, 50}, - { 0x005a1a00, 19}, - { 0x005a1b00, 50}, - { 0x005a1e00, 50}, - { 0x005a1f00, 50}, - { 0x005a4200, 19}, - { 0x005a4300, 50}, - { 0x005a4600, 50}, - { 0x005a4700, 50}, - { 0x005a4a00, 19}, - { 0x005a4b00, 50}, - { 0x005a4e00, 50}, - { 0x005a4f00, 50}, - { 0x005a5200, 19}, - { 0x005a5300, 50}, - { 0x005a5600, 50}, - { 0x005a5700, 50}, - { 0x005a5a00, 19}, - { 0x005a5b00, 50}, - { 0x005a5e00, 50}, - { 0x005a5f00, 50}, - { 0x005a6200, 19}, - { 0x005a6300, 50}, - { 0x005a6600, 50}, - { 0x005a6700, 50}, - { 0x005a6a00, 19}, - { 0x005a6b00, 50}, - { 0x005a6e00, 50}, - { 0x005a6f00, 50}, - { 0x005a9a00, 19}, - { 0x005a9b00, 50}, - { 0x005a9e00, 50}, - { 0x005a9f00, 50}, - { 0x005ac200, 19}, - { 0x005ac300, 50}, - { 0x005ac600, 50}, - { 0x005ac700, 50}, - { 0x005aca00, 19}, - { 0x005acb00, 50}, - { 0x005ace00, 50}, - { 0x005acf00, 50}, - { 0x005ad200, 19}, - { 0x005ad300, 50}, - { 0x005ad600, 50}, - { 0x005ad700, 50}, - { 0x005ada00, 19}, - { 0x005adb00, 50}, - { 0x005ade00, 50}, - { 0x005adf00, 50}, - { 0x005ae200, 19}, - { 0x005ae300, 50}, - { 0x005ae600, 50}, - { 0x005ae700, 50}, - { 0x005aea00, 19}, - { 0x005aeb00, 50}, - { 0x005aee00, 50}, - { 0x005aef00, 50}, - { 0x008300a8, 1}, - { 0x00830b5c, 1}, - { 0x008340a8, 1}, - { 0x00834b5c, 1}, - { 0x008380a8, 1}, - { 0x00838b5c, 1}, - { 0x008400a8, 1}, - { 0x00900100, 1}, - { 0x00904100, 1}, - { 0x00908100, 1}, - { 0x0090c100, 1}, - { 0x00910100, 1}, - { 0x00914100, 1}, - { 0x00918100, 1}, - { 0x0091c100, 1}, - { 0x009a0100, 1}, - { 0x00a00160, 2}, - { 0x00a007d0, 1}, - { 0x00a04200, 1}, - { 0x00a04470, 2}, - { 0x00a08190, 1}, - { 0x00a08198, 4}, - { 0x00a0c020, 2}, - { 0x00a0c820, 2}, - { 0x00a0cc20, 2}, - { 0x00a0e470, 2}, - { 0x00a0e490, 9}, - { 0x00a0e6a8, 7}, - { 0x00a0e6c8, 2}, - { 0x00a0e6d4, 7}, - { 0x00a0e6f4, 2}, - { 0x00a0ec70, 2}, - { 0x00a0ec90, 9}, - { 0x00a0eea8, 7}, - { 0x00a0eec8, 2}, - { 0x00a0eed4, 7}, - { 0x00a0eef4, 2}, - { 0x00a10190, 1}, - { 0x00a10198, 4}, - { 0x00a14020, 2}, - { 0x00a14820, 2}, - { 0x00a14c20, 2}, - { 0x00a16470, 2}, - { 0x00a16490, 9}, - { 0x00a166a8, 7}, - { 0x00a166c8, 2}, - { 0x00a166d4, 7}, - { 0x00a166f4, 2}, - { 0x00a16c70, 2}, - { 0x00a16c90, 9}, - { 0x00a16ea8, 7}, - { 0x00a16ec8, 2}, - { 0x00a16ed4, 7}, - { 0x00a16ef4, 2}, - { 0x00a18190, 1}, - { 0x00a18198, 4}, - { 0x00a1c020, 2}, - { 0x00a1c820, 2}, - { 0x00a1cc20, 2}, - { 0x00a1e470, 2}, - { 0x00a1e490, 9}, - { 0x00a1e6a8, 7}, - { 0x00a1e6c8, 2}, - { 0x00a1e6d4, 7}, - { 0x00a1e6f4, 2}, - { 0x00a1ec70, 2}, - { 0x00a1ec90, 9}, - { 0x00a1eea8, 7}, - { 0x00a1eec8, 2}, - { 0x00a1eed4, 7}, - { 0x00a1eef4, 2}, -}; - -static const u64 tu104_global_whitelist_ranges_count = - ARRAY_SIZE(tu104_global_whitelist_ranges); - -/* context */ - -/* runcontrol */ -static const u32 tu104_runcontrol_whitelist[] = { -}; -static const u64 tu104_runcontrol_whitelist_count = - ARRAY_SIZE(tu104_runcontrol_whitelist); - -/* quad ctl */ -static const u32 tu104_qctl_whitelist[] = { -}; -static const u64 tu104_qctl_whitelist_count = - ARRAY_SIZE(tu104_qctl_whitelist); - -const struct regop_offset_range *tu104_get_global_whitelist_ranges(void) -{ - return tu104_global_whitelist_ranges; -} - -u64 tu104_get_global_whitelist_ranges_count(void) -{ - return tu104_global_whitelist_ranges_count; -} - -const struct regop_offset_range *tu104_get_context_whitelist_ranges(void) -{ - return tu104_global_whitelist_ranges; -} - -u64 tu104_get_context_whitelist_ranges_count(void) -{ - return tu104_global_whitelist_ranges_count; -} - -const u32 *tu104_get_runcontrol_whitelist(void) -{ - return tu104_runcontrol_whitelist; -} - -u64 tu104_get_runcontrol_whitelist_count(void) -{ - return tu104_runcontrol_whitelist_count; -} - -const u32 *tu104_get_qctl_whitelist(void) -{ - return tu104_qctl_whitelist; -} - -u64 tu104_get_qctl_whitelist_count(void) -{ - return tu104_qctl_whitelist_count; -} diff --git a/drivers/gpu/nvgpu/tu104/regops_tu104.h b/drivers/gpu/nvgpu/tu104/regops_tu104.h deleted file mode 100644 index b6e3d6798..000000000 --- a/drivers/gpu/nvgpu/tu104/regops_tu104.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __REGOPS_TU104_H_ -#define __REGOPS_TU104_H_ - -const struct regop_offset_range *tu104_get_global_whitelist_ranges(void); -u64 tu104_get_global_whitelist_ranges_count(void); -const struct regop_offset_range *tu104_get_context_whitelist_ranges(void); -u64 tu104_get_context_whitelist_ranges_count(void); -const u32 *tu104_get_runcontrol_whitelist(void); -u64 tu104_get_runcontrol_whitelist_count(void); -const struct regop_offset_range *tu104_get_runcontrol_whitelist_ranges(void); -u64 tu104_get_runcontrol_whitelist_ranges_count(void); -const u32 *tu104_get_qctl_whitelist(void); -u64 tu104_get_qctl_whitelist_count(void); -const struct regop_offset_range *tu104_get_qctl_whitelist_ranges(void); -u64 tu104_get_qctl_whitelist_ranges_count(void); -int tu104_apply_smpc_war(struct dbg_session_gk20a *dbg_s); - -#endif /* __REGOPS_TU104_H_ */ diff --git a/drivers/gpu/nvgpu/tu104/sec2_tu104.c b/drivers/gpu/nvgpu/tu104/sec2_tu104.c deleted file mode 100644 index d5182dc45..000000000 --- a/drivers/gpu/nvgpu/tu104/sec2_tu104.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sec2_tu104.h" - -#include -#include - -int tu104_sec2_reset(struct gk20a *g) -{ - nvgpu_log_fn(g, " "); - - gk20a_writel(g, psec_falcon_engine_r(), - psec_falcon_engine_reset_true_f()); - nvgpu_udelay(10); - gk20a_writel(g, psec_falcon_engine_r(), - psec_falcon_engine_reset_false_f()); - - nvgpu_log_fn(g, "done"); - return 0; -} - -static int tu104_sec2_emem_transfer(struct gk20a *g, u32 dmem_addr, u8 *buf, - u32 size_in_bytes, u8 port, bool is_copy_from) -{ - u32 *data = (u32 *)(void *)buf; - u32 num_words = 0; - u32 num_bytes = 0; - u32 start_emem = 0; - u32 end_emem = 0; - u32 reg = 0; - u32 i = 0; - u32 emem_c_offset = 0; - u32 emem_d_offset = 0; - u8 max_emem_ports = (u8)psec_ememc__size_1_v(); - int status = 0; - - if (size_in_bytes == 0U) { - nvgpu_err(g, "zero-byte copy requested"); - status = -EINVAL; - goto exit; - } - - if (port >= max_emem_ports) { - nvgpu_err(g, "only %d ports supported. Accessed port=%d\n", - max_emem_ports, port); - status = -EINVAL; - goto exit; - } - - /* - * Get the EMEMC/D register addresses - * for the specified port - */ - emem_c_offset = psec_ememc_r(port); - emem_d_offset = psec_ememd_r(port); - - /* - * EMEM is mapped at the top of DMEM VA space - * START_EMEM = DMEM_VA_MAX = 2^(DMEM_TAG_WIDTH + 8) - */ - start_emem = (u32)1U << ((u32)psec_falcon_hwcfg1_dmem_tag_width_v( - gk20a_readl(g, psec_falcon_hwcfg1_r())) + (u32)8U); - - end_emem = start_emem + - ((u32)psec_hwcfg_emem_size_f(gk20a_readl(g, psec_hwcfg_r())) - * (u32)256U); - - if (dmem_addr < start_emem || - (dmem_addr + size_in_bytes) > end_emem) { - nvgpu_err(g, "copy must be in emem aperature [0x%x, 0x%x]", - start_emem, end_emem); - status = -EINVAL; - goto exit; - } - - /* Convert to emem offset for use by EMEMC/EMEMD */ - dmem_addr -= start_emem; - - /* Mask off all but the OFFSET and BLOCK in EMEM offset */ - reg = dmem_addr & (psec_ememc_offs_m() | - psec_ememc_blk_m()); - - if (is_copy_from) { - /* mark auto-increment on read */ - reg |= psec_ememc_aincr_m(); - } else { - /* mark auto-increment on write */ - reg |= psec_ememc_aincw_m(); - } - - gk20a_writel(g, emem_c_offset, reg); - - /* Calculate the number of words and bytes */ - num_words = size_in_bytes >> 2U; - num_bytes = size_in_bytes & 0x3U; - - /* Directly copy words to emem*/ - for (i = 0; i < num_words; i++) { - if (is_copy_from) { - data[i] = gk20a_readl(g, emem_d_offset); - } else { - gk20a_writel(g, emem_d_offset, data[i]); - } - } - - /* Check if there are leftover bytes to copy */ - if (num_bytes > 0U) { - u32 bytes_copied = num_words << 2U; - - reg = gk20a_readl(g, emem_d_offset); - if (is_copy_from) { - for (i = 0; i < num_bytes; i++) { - buf[bytes_copied + i] = ((u8 *)®)[i]; - } - } else { - for (i = 0; i < num_bytes; i++) { - ((u8 *)®)[i] = buf[bytes_copied + i]; - } - gk20a_writel(g, emem_d_offset, reg); - } - } - -exit: - return status; -} - -int tu104_sec2_flcn_copy_to_emem(struct nvgpu_falcon *flcn, - u32 dst, u8 *src, u32 size, u8 port) -{ - struct gk20a *g = flcn->g; - - return tu104_sec2_emem_transfer(g, dst, src, size, port, false); -} - -int tu104_sec2_flcn_copy_from_emem(struct nvgpu_falcon *flcn, - u32 src, u8 *dst, u32 size, u8 port) -{ - struct gk20a *g = flcn->g; - - return tu104_sec2_emem_transfer(g, src, dst, size, port, true); -} - -static int tu104_sec2_flcn_bl_bootstrap(struct gk20a *g, - struct nvgpu_falcon_bl_info *bl_info) -{ - struct mm_gk20a *mm = &g->mm; - u32 data = 0; - - nvgpu_log_fn(g, " "); - - /* SEC2 Config */ - gk20a_writel(g, psec_falcon_itfen_r(), - gk20a_readl(g, psec_falcon_itfen_r()) | - psec_falcon_itfen_ctxen_enable_f()); - - gk20a_writel(g, psec_falcon_nxtctx_r(), - pwr_pmu_new_instblk_ptr_f( - nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) | - pwr_pmu_new_instblk_valid_f(1U) | - nvgpu_aperture_mask(g, &mm->pmu.inst_block, - pwr_pmu_new_instblk_target_sys_ncoh_f(), - pwr_pmu_new_instblk_target_sys_coh_f(), - pwr_pmu_new_instblk_target_fb_f())); - - data = gk20a_readl(g, psec_falcon_debug1_r()); - data |= psec_falcon_debug1_ctxsw_mode_m(); - gk20a_writel(g, psec_falcon_debug1_r(), data); - - data = gk20a_readl(g, psec_falcon_engctl_r()); - data |= (1U << 3U); - gk20a_writel(g, psec_falcon_engctl_r(), data); - - return nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info); -} - -int tu104_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g, - struct hs_acr *acr_desc, - struct nvgpu_falcon_bl_info *bl_info) -{ - u32 data = 0U; - - nvgpu_log_fn(g, " "); - - nvgpu_flcn_reset(&g->sec2_flcn); - - data = gk20a_readl(g, psec_fbif_ctl_r()); - data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f(); - gk20a_writel(g, psec_fbif_ctl_r(), data); - - /* setup apertures - virtual */ - gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), - psec_fbif_transcfg_mem_type_physical_f() | - psec_fbif_transcfg_target_local_fb_f()); - gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), - psec_fbif_transcfg_mem_type_virtual_f()); - /* setup apertures - physical */ - gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), - psec_fbif_transcfg_mem_type_physical_f() | - psec_fbif_transcfg_target_local_fb_f()); - gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), - psec_fbif_transcfg_mem_type_physical_f() | - psec_fbif_transcfg_target_coherent_sysmem_f()); - gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), - psec_fbif_transcfg_mem_type_physical_f() | - psec_fbif_transcfg_target_noncoherent_sysmem_f()); - - return tu104_sec2_flcn_bl_bootstrap(g, bl_info); -} - -int tu104_sec2_queue_head(struct gk20a *g, struct nvgpu_falcon_queue *queue, - u32 *head, bool set) -{ - u32 queue_head_size = 8; - - if (queue->id <= SEC2_NV_CMDQ_LOG_ID__LAST) { - if (queue->index >= queue_head_size) { - return -EINVAL; - } - - if (!set) { - *head = psec_queue_head_address_v( - gk20a_readl(g, psec_queue_head_r(queue->index))); - } else { - gk20a_writel(g, psec_queue_head_r(queue->index), - psec_queue_head_address_f(*head)); - } - } else { - if (!set) { - *head = psec_msgq_head_val_v( - gk20a_readl(g, psec_msgq_head_r(0U))); - } else { - gk20a_writel(g, - psec_msgq_head_r(0U), - psec_msgq_head_val_f(*head)); - } - } - - return 0; -} - -int tu104_sec2_queue_tail(struct gk20a *g, struct nvgpu_falcon_queue *queue, - u32 *tail, bool set) -{ - u32 queue_tail_size = 8; - - if (queue->id <= SEC2_NV_CMDQ_LOG_ID__LAST) { - if (queue->index >= queue_tail_size) { - return -EINVAL; - } - - if (!set) { - *tail = psec_queue_tail_address_v( - gk20a_readl(g, psec_queue_tail_r(queue->index))); - } else { - gk20a_writel(g, - psec_queue_tail_r(queue->index), - psec_queue_tail_address_f(*tail)); - } - } else { - if (!set) { - *tail = psec_msgq_tail_val_v( - gk20a_readl(g, psec_msgq_tail_r(0U))); - } else { - gk20a_writel(g, psec_msgq_tail_r(0U), - psec_msgq_tail_val_f(*tail)); - } - } - - return 0; -} - -void tu104_sec2_msgq_tail(struct gk20a *g, struct nvgpu_sec2 *sec2, - u32 *tail, bool set) -{ - if (!set) { - *tail = gk20a_readl(g, psec_msgq_tail_r(0U)); - } else { - gk20a_writel(g, psec_msgq_tail_r(0U), *tail); - } -} - -void tu104_sec2_enable_irq(struct nvgpu_sec2 *sec2, bool enable) -{ - struct gk20a *g = sec2->g; - u32 intr_mask; - u32 intr_dest; - - nvgpu_flcn_set_irq(&g->sec2_flcn, false, 0x0, 0x0); - - if (enable) { - /* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */ - intr_dest = psec_falcon_irqdest_host_gptmr_f(0) | - psec_falcon_irqdest_host_wdtmr_f(1) | - psec_falcon_irqdest_host_mthd_f(0) | - psec_falcon_irqdest_host_ctxsw_f(0) | - psec_falcon_irqdest_host_halt_f(1) | - psec_falcon_irqdest_host_exterr_f(0) | - psec_falcon_irqdest_host_swgen0_f(1) | - psec_falcon_irqdest_host_swgen1_f(0) | - psec_falcon_irqdest_host_ext_f(0xff) | - psec_falcon_irqdest_target_gptmr_f(1) | - psec_falcon_irqdest_target_wdtmr_f(0) | - psec_falcon_irqdest_target_mthd_f(0) | - psec_falcon_irqdest_target_ctxsw_f(0) | - psec_falcon_irqdest_target_halt_f(0) | - psec_falcon_irqdest_target_exterr_f(0) | - psec_falcon_irqdest_target_swgen0_f(0) | - psec_falcon_irqdest_target_swgen1_f(0) | - psec_falcon_irqdest_target_ext_f(0xff); - - /* 0=disable, 1=enable */ - intr_mask = psec_falcon_irqmset_gptmr_f(1) | - psec_falcon_irqmset_wdtmr_f(1) | - psec_falcon_irqmset_mthd_f(0) | - psec_falcon_irqmset_ctxsw_f(0) | - psec_falcon_irqmset_halt_f(1) | - psec_falcon_irqmset_exterr_f(1) | - psec_falcon_irqmset_swgen0_f(1) | - psec_falcon_irqmset_swgen1_f(1); - - nvgpu_flcn_set_irq(&g->sec2_flcn, true, intr_mask, intr_dest); - } -} - -bool tu104_sec2_is_interrupted(struct nvgpu_sec2 *sec2) -{ - struct gk20a *g = sec2->g; - u32 servicedpmuint = 0U; - - servicedpmuint = psec_falcon_irqstat_halt_true_f() | - psec_falcon_irqstat_exterr_true_f() | - psec_falcon_irqstat_swgen0_true_f(); - - if (gk20a_readl(g, psec_falcon_irqstat_r()) & - servicedpmuint) { - return true; - } - - return false; -} - -void tu104_sec2_isr(struct gk20a *g) -{ - struct nvgpu_sec2 *sec2 = &g->sec2; - struct nvgpu_falcon_queue *queue; - u32 intr, mask; - bool recheck = false; - - nvgpu_mutex_acquire(&sec2->isr_mutex); - if (!sec2->isr_enabled) { - nvgpu_mutex_release(&sec2->isr_mutex); - return; - } - - mask = gk20a_readl(g, psec_falcon_irqmask_r()) & - gk20a_readl(g, psec_falcon_irqdest_r()); - - intr = gk20a_readl(g, psec_falcon_irqstat_r()); - - intr = gk20a_readl(g, psec_falcon_irqstat_r()) & mask; - if (!intr) { - gk20a_writel(g, psec_falcon_irqsclr_r(), intr); - nvgpu_mutex_release(&sec2->isr_mutex); - return; - } - - if (intr & psec_falcon_irqstat_halt_true_f()) { - nvgpu_err(g, "sec2 halt intr not implemented"); - nvgpu_flcn_dump_stats(&g->sec2_flcn); - } - if (intr & psec_falcon_irqstat_exterr_true_f()) { - nvgpu_err(g, - "sec2 exterr intr not implemented. Clearing interrupt."); - - gk20a_writel(g, psec_falcon_exterrstat_r(), - gk20a_readl(g, psec_falcon_exterrstat_r()) & - ~psec_falcon_exterrstat_valid_m()); - } - - if (intr & psec_falcon_irqstat_swgen0_true_f()) { - if (nvgpu_sec2_process_message(sec2)) { - gk20a_writel(g, psec_falcon_irqsclr_r(), intr); - goto exit; - } - recheck = true; - } - - gk20a_writel(g, psec_falcon_irqsclr_r(), intr); - - if (recheck) { - queue = &sec2->queue[SEC2_NV_MSGQ_LOG_ID]; - if (!nvgpu_flcn_queue_is_empty(sec2->flcn, queue)) { - gk20a_writel(g, psec_falcon_irqsset_r(), - psec_falcon_irqsset_swgen0_set_f()); - } - } - -exit: - nvgpu_sec2_dbg(g, "Done"); - nvgpu_mutex_release(&sec2->isr_mutex); -} - -void tu104_start_sec2_secure(struct gk20a *g) -{ - gk20a_writel(g, psec_falcon_cpuctl_alias_r(), - psec_falcon_cpuctl_alias_startcpu_f(1U)); -} diff --git a/drivers/gpu/nvgpu/tu104/sec2_tu104.h b/drivers/gpu/nvgpu/tu104/sec2_tu104.h deleted file mode 100644 index 00ee86a0d..000000000 --- a/drivers/gpu/nvgpu/tu104/sec2_tu104.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __SEC2_TU104_H__ -#define __SEC2_TU104_H__ - -struct nvgpu_sec2; - -int tu104_sec2_reset(struct gk20a *g); -int tu104_sec2_flcn_copy_to_emem(struct nvgpu_falcon *flcn, - u32 dst, u8 *src, u32 size, u8 port); -int tu104_sec2_flcn_copy_from_emem(struct nvgpu_falcon *flcn, - u32 src, u8 *dst, u32 size, u8 port); -int tu104_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g, - struct hs_acr *acr_desc, - struct nvgpu_falcon_bl_info *bl_info); - -int tu104_sec2_queue_head(struct gk20a *g, struct nvgpu_falcon_queue *queue, - u32 *head, bool set); -int tu104_sec2_queue_tail(struct gk20a *g, struct nvgpu_falcon_queue *queue, - u32 *tail, bool set); -void tu104_sec2_msgq_tail(struct gk20a *g, struct nvgpu_sec2 *sec2, - u32 *tail, bool set); - -void tu104_sec2_isr(struct gk20a *g); -bool tu104_sec2_is_interrupted(struct nvgpu_sec2 *sec2); -void tu104_sec2_enable_irq(struct nvgpu_sec2 *sec2, bool enable); -void tu104_start_sec2_secure(struct gk20a *g); - -#endif /*__SEC2_TU104_H__*/ diff --git a/userspace/Makefile b/userspace/Makefile index fec34aa60..7ce5179da 100644 --- a/userspace/Makefile +++ b/userspace/Makefile @@ -39,6 +39,8 @@ CORE_OUT=$(OUT)/nvgpu_unit_core # Nvgpu driver code. NVGPU_SRC=$(TWD)/../drivers/gpu/nvgpu NVGPU_OUT=$(OUT)/libnvgpu +# Nvgpu_next driver code. +NVGPU_NEXT_SRC=$(TWD)/../../nvgpu-next/drivers/gpu/nvgpu # Unit tests themselves. UNIT_SRC=$(TWD)/units @@ -47,6 +49,8 @@ UNIT_OUT=$(OUT)/units INCLUDES= \ -I$(NVGPU_SRC) \ -I$(NVGPU_SRC)/include \ + -I$(NVGPU_NEXT_SRC) \ + -I$(NVGPU_NEXT_SRC)/include \ -I$(TWD)/../include \ -I$(TWD)/../include/uapi \ -I$(TWD)/include @@ -107,6 +111,14 @@ $(NVGPU_OUT)/%.o : $(NVGPU_SRC)/%.c $(HEADERS) fi $(CC) --coverage $(CFLAGS) $(configs) -c -o $@ $< +# Default build target for all the nvgpu-next driver object files we want to +# build in userspace. These too get bundled into libnvgpu-drv.so. +$(NVGPU_OUT)/%.o : $(NVGPU_NEXT_SRC)/%.c $(HEADERS) $(HEADERS_NEXT) + @if [ ! -d $(dir $@) ] ; then \ + mkdir -p $(dir $@) ; \ + fi + $(CC) --coverage $(CFLAGS) $(configs) -c -o $@ $< + # Build target for unit test files. These are not part of the libnvgpu-drv.so. # These comprise the unit test framework. $(CORE_OUT)/%.o : $(CORE_SRC)/%.c $(CORE_HEADERS) diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 4f387de4a..a7b89cfeb 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -21,8 +21,9 @@ # DEALINGS IN THE SOFTWARE. include $(NVGPU_SRC)/Makefile.sources +-include $(NVGPU_NEXT_SRC)/Makefile.sources -OBJS := $(srcs:%.c=$(NVGPU_OUT)/%.o) +OBJS := $(srcs:%.c=$(NVGPU_OUT)/%.o) $(srcs_next:%.c=$(NVGPU_OUT)/%.o) HEADERS := \ $(NVGPU_SRC)/include/nvgpu/*.h \ @@ -30,8 +31,7 @@ HEADERS := \ $(NVGPU_SRC)/gk20a/*.h \ $(NVGPU_SRC)/gm20b/*.h \ $(NVGPU_SRC)/gp10b/*.h \ - $(NVGPU_SRC)/gv11b/*.h \ - $(NVGPU_SRC)/tu104/*.h + $(NVGPU_SRC)/gv11b/*.h CORE_OBJS := \ $(CORE_OUT)/unit_main.o \