diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 95accdc4d..50180551d 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -351,6 +351,7 @@ struct gpu_ops {
 		void (*load_tpc_mask)(struct gk20a *g);
 		int (*set_czf_bypass)(struct gk20a *g,
 				      struct channel_gk20a *ch);
+		void (*disable_rd_coalesce)(struct gk20a *g);
 	} gr;
 	const char *name;
 	struct {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 12fe2fdc1..2eef936ab 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4822,6 +4822,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
 	if (g->ops.ltc.init_cbc)
 		g->ops.ltc.init_cbc(g, gr);
 
+	if (g->ops.gr.disable_rd_coalesce)
+			g->ops.gr.disable_rd_coalesce(g);
+
 	/* load ctx init */
 	for (i = 0; i < sw_ctx_load->count; i++)
 		gk20a_writel(g, sw_ctx_load->l[i].addr,
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 5b5fa82c2..d40d7ffb8 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1517,6 +1517,23 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
 					priv_addr_table, priv_addr_table_index);
 }
 
+/*
+ *  * Disable both surface and LG coalesce.
+ *   */
+void gm20a_gr_disable_rd_coalesce(struct gk20a *g)
+{
+	u32 dbg2_reg;
+
+	dbg2_reg = gk20a_readl(g, gr_gpcs_tpcs_tex_m_dbg2_r());
+	dbg2_reg = set_field(dbg2_reg,
+			             gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(),
+						 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(0));
+	dbg2_reg = set_field(dbg2_reg,
+					     gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(),
+					     gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(0));
+	gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg);
+}
+
 void gm20b_init_gr(struct gpu_ops *gops)
 {
 	gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu;