From b811a0b755a633acba3ac4c99f2c9dd95677b94b Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 30 Jan 2020 14:03:37 -0800 Subject: [PATCH] gpu: nvgpu: add hal for fecs ctsw clear mailbox Add hal to have chip specific fecs ctxsw mailbox clear function. This hal has following prototype with mailbox reg_index and bitmask for clear_val: void (*fecs_ctxsw_clear_mailbox)(struct gk20a *g, u32 reg_index, u32 clear_val); JIRA NVGPU-4870 Change-Id: I1d20309224f856872dc97040ecf7628c60fb2802 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287921 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Alex Waterman Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 3 +-- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h | 2 ++ .../hal/gr/falcon/gr_falcon_gm20b_fusa.c | 19 ++++++++++++------- drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 2 ++ drivers/gpu/nvgpu/include/nvgpu/gops_gr.h | 13 +++++++++++++ 8 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 749d89ce9..1fda77877 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -198,8 +198,7 @@ void gm20b_gr_falcon_start_ucode(struct gk20a *g) { nvgpu_log_fn(g, " "); - nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0U), - gr_fecs_ctxsw_mailbox_clear_value_f(~U32(0U))); + g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 0U, (~U32(0U))); nvgpu_writel(g, gr_gpccs_dmactl_r(), gr_gpccs_dmactl_require_ctx_f(0U)); nvgpu_writel(g, gr_fecs_dmactl_r(), gr_fecs_dmactl_require_ctx_f(0U)); diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h index 35c0fb337..1998964f9 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h @@ -30,6 +30,8 @@ struct nvgpu_fecs_method_op; struct nvgpu_fecs_host_intr_status; struct nvgpu_gr_falcon_query_sizes; +void gm20b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g, + u32 reg_index, u32 clear_val); u32 gm20b_gr_falcon_read_fecs_ctxsw_mailbox(struct gk20a *g, u32 reg_index); void gm20b_gr_falcon_fecs_host_clear_intr(struct gk20a *g, u32 fecs_intr); u32 gm20b_gr_falcon_fecs_host_intr_status(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c index de4475e97..884bcc3e4 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c @@ -51,6 +51,12 @@ #define CTXSW_INTR0 BIT32(0) #define CTXSW_INTR1 BIT32(1) +void gm20b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g, + u32 reg_index, u32 clear_val) +{ + nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(reg_index), + gr_fecs_ctxsw_mailbox_clear_value_f(clear_val)); +} u32 gm20b_gr_falcon_get_gpccs_start_reg_offset(void) { @@ -80,9 +86,9 @@ void gm20b_gr_falcon_start_gpccs(struct gk20a *g) void gm20b_gr_falcon_start_fecs(struct gk20a *g) { - nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0U), ~U32(0U)); + g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 0U, ~U32(0U)); nvgpu_writel(g, gr_fecs_ctxsw_mailbox_r(1U), 1U); - nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(6U), 0xffffffffU); + g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 6U, 0xffffffffU); nvgpu_writel(g, gr_fecs_cpuctl_alias_r(), gr_fecs_cpuctl_startcpu_f(1U)); } @@ -127,7 +133,7 @@ void gm20b_gr_falcon_bind_instblk(struct gk20a *g, FECS_ARB_CMD_TIMEOUT_DEFAULT_US; u32 inst_ptr_u32; - nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), U32_MAX); + g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 0U, U32_MAX); while (((nvgpu_readl(g, gr_fecs_ctxsw_status_1_r()) & gr_fecs_ctxsw_status_1_arb_busy_m()) != 0U) && @@ -641,8 +647,7 @@ int gm20b_gr_falcon_submit_fecs_method_op(struct gk20a *g, op.mailbox.data); } - nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), - gr_fecs_ctxsw_mailbox_clear_value_f(op.mailbox.clr)); + g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 0U, op.mailbox.clr); nvgpu_writel(g, gr_fecs_method_data_r(), op.method.data); nvgpu_writel(g, gr_fecs_method_push_r(), @@ -1038,8 +1043,8 @@ int gm20b_gr_falcon_submit_fecs_sideband_method_op(struct gk20a *g, nvgpu_mutex_acquire(&gr_falcon->fecs_mutex); - nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(op.mailbox.id), - gr_fecs_ctxsw_mailbox_clear_value_f(op.mailbox.clr)); + g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, op.mailbox.id, + op.mailbox.clr); nvgpu_writel(g, gr_fecs_method_data_r(), op.method.data); nvgpu_writel(g, gr_fecs_method_push_r(), diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 3c103ed73..bdbb7c371 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -514,6 +514,8 @@ static const struct gpu_ops gm20b_ops = { .dump_stats = gm20b_gr_falcon_fecs_dump_stats, .fecs_ctxsw_mailbox_size = gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size, + .fecs_ctxsw_clear_mailbox = + gm20b_gr_falcon_fecs_ctxsw_clear_mailbox, .get_fecs_ctx_state_store_major_rev_id = gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id, .start_gpccs = gm20b_gr_falcon_start_gpccs, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 5d30b8d97..89b73ff44 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -601,6 +601,8 @@ static const struct gpu_ops gp10b_ops = { .dump_stats = gm20b_gr_falcon_fecs_dump_stats, .fecs_ctxsw_mailbox_size = gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size, + .fecs_ctxsw_clear_mailbox = + gm20b_gr_falcon_fecs_ctxsw_clear_mailbox, .get_fecs_ctx_state_store_major_rev_id = gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id, .start_gpccs = gm20b_gr_falcon_start_gpccs, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 743803c99..6bee7022b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -756,6 +756,8 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7)) .dump_stats = gm20b_gr_falcon_fecs_dump_stats, .fecs_ctxsw_mailbox_size = gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size, + .fecs_ctxsw_clear_mailbox = + gm20b_gr_falcon_fecs_ctxsw_clear_mailbox, .get_fecs_ctx_state_store_major_rev_id = gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id, .start_gpccs = gm20b_gr_falcon_start_gpccs, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 3ded697ec..24846faba 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -758,6 +758,8 @@ static const struct gpu_ops tu104_ops = { .dump_stats = gm20b_gr_falcon_fecs_dump_stats, .fecs_ctxsw_mailbox_size = gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size, + .fecs_ctxsw_clear_mailbox = + gm20b_gr_falcon_fecs_ctxsw_clear_mailbox, .get_fecs_ctx_state_store_major_rev_id = gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id, .start_gpccs = gm20b_gr_falcon_start_gpccs, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h index edc1beed1..7c1e5f228 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h @@ -253,6 +253,19 @@ struct gops_gr_falcon { u32 (*read_fecs_ctxsw_mailbox)(struct gk20a *g, u32 reg_index); + /** + * @brief Clear context switch mailbox for bitmask speciifed. + * + * @param g [in] Pointer to GPU driver struct. + * @param reg_index [in] Register Index value. + * clear_val [in] Bitmask of bits to be clear. + * + * This function clears specified bitmask of context switch mailbox + * register value. + */ + void (*fecs_ctxsw_clear_mailbox)(struct gk20a *g, + u32 reg_index, u32 clear_val); + /** * @brief Dump context switch mailbox register values. *