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gpu: nvgpu: gr: basic falcon hal functions

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Created gr falcon hal unit with moving following hal functions
from gr to gr falcon:
u32 (*fecs_base_addr)(void);
u32 (*gpccs_base_addr)(void);
void (*dump_stats)(struct gk20a *g);
u32 (*fecs_ctxsw_mailbox_size)(void);
u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g);

Modified chip hals to populate these new functions and related code
now refers to gr falcon hals.

Modified kernel headers to have following defs for
fecs/gpccs base address in gm20b/gp10b/gv11b/tu104:
static inline u32 gr_fecs_irqsset_r(void);
static inline u32 gr_gpcs_gpccs_irqsset_r(void);

Created base gm20b hals for fecs/gpccs_base_addr and
removed redundant gp106 related hals.

JIRA NVGPU-1881

Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081245
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-03-25 14:56:09 -07:00
committed by mobile promotions
parent e4313b3a15
commit b82f2075ae
25 changed files with 212 additions and 94 deletions
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2
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -654,7 +654,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
mmfault_info.access_type, mmfault_info.inst_ptr);
if (ctxsw) {
g->ops.gr.dump_gr_falcon_stats(g);
g->ops.gr.falcon.dump_stats(g);
nvgpu_err(g, " gr_status_r: 0x%x",
gk20a_readl(g, gr_status_r()));
}