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gpu: nvgpu: gr: basic falcon hal functions
Created gr falcon hal unit with moving following hal functions from gr to gr falcon: u32 (*fecs_base_addr)(void); u32 (*gpccs_base_addr)(void); void (*dump_stats)(struct gk20a *g); u32 (*fecs_ctxsw_mailbox_size)(void); u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g); Modified chip hals to populate these new functions and related code now refers to gr falcon hals. Modified kernel headers to have following defs for fecs/gpccs base address in gm20b/gp10b/gv11b/tu104: static inline u32 gr_fecs_irqsset_r(void); static inline u32 gr_gpcs_gpccs_irqsset_r(void); Created base gm20b hals for fecs/gpccs_base_addr and removed redundant gp106 related hals. JIRA NVGPU-1881 Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2081245 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -172,7 +172,7 @@ void gk20a_fifo_intr_handle_chsw_error(struct gk20a *g)
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nvgpu_report_host_error(g, 0,
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GPU_HOST_PFIFO_CHSW_ERROR, intr);
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nvgpu_err(g, "chsw: %08x", intr);
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g->ops.gr.dump_gr_falcon_stats(g);
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g->ops.gr.falcon.dump_stats(g);
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nvgpu_writel(g, fifo_intr_chsw_error_r(), intr);
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}
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