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gpu: nvgpu: Fix CERT-C Violations

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Fix the following CERT-C Violations:
gsp_runlist.c : CERT EXP34-C
channel_sync_syncpt.c : CERT ERR33-C
grmgr_ga100.c : CERT ERR33-C
grmgr_ga10b.c : CERT ERR33-C
debug.c : CERT ERR33-C
debug_fecs_trace.c : CERT EXP34-C
ioctl.c : CERT ERR33-C

CID 495110
CID 141061
CID 222881
CID 222890
CID 450994
CID 366644
CID 466529

Bug 3512546

Signed-off-by: Jinesh Parakh <jparakh@nvidia.com>
Change-Id: I318a27a6fcb8ea8f6d5d6c1f65d940c48d6f8dfc
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2723008
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Jinesh Parakh
2022-06-01 12:03:08 +05:30
committed by mobile promotions
parent dcec7f184e
commit b8b90f85ee
7 changed files with 24 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/common/gsp_scheduler/gsp_runlist.c
View File

@@ -126,6 +126,7 @@ static void gsp_get_device_info(struct gk20a *g,
* In future, more devices can be looped through and send it to the GSP.
*/
device = nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS, 0);
nvgpu_assert(device != NULL);
/* copy domain info into cmd buffer */
dev_info->device_id = NVGPU_DEVTYPE_GRAPHICS;

3
drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
View File

@@ -374,8 +374,9 @@ nvgpu_channel_sync_syncpt_create(struct nvgpu_channel *c)
sp->c = c;
sp->nvhost = c->g->nvhost;
snprintf(syncpt_name, sizeof(syncpt_name),
err = snprintf(syncpt_name, sizeof(syncpt_name),
"%s_%d", c->g->name, c->chid);
nvgpu_assert(err > 0);
sp->id = nvgpu_nvhost_get_syncpt_client_managed(sp->nvhost,
syncpt_name);

6
drivers/gpu/nvgpu/hal/grmgr/grmgr_ga100.c
View File

@@ -1,7 +1,7 @@
/*
* GA100 GR MANAGER
*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1097,9 +1097,11 @@ const struct nvgpu_mig_gpu_instance_config *ga100_grmgr_get_mig_config_ptr(
u32 start_id_of_half_partition = 0x1;
gpu_instance_config =
&ga100_gpu_instance_default_config.gpu_instance_config[num_config];
snprintf(gpu_instance_config->config_name,
err = snprintf(gpu_instance_config->config_name,
NVGPU_MIG_MAX_CONFIG_NAME_SIZE,
"2 GPU instances each with %u GPCs", gpc_count_per_gpu_instance);
nvgpu_assert(err > 0);
gpu_instance_config->num_gpu_instances = 2U;
for (index = 0U; index < 2U; index++) {

5
drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
View File

@@ -69,6 +69,7 @@ const struct nvgpu_mig_gpu_instance_config *ga10b_grmgr_get_mig_config_ptr(
static struct nvgpu_mig_gpu_instance_config ga10b_gpu_instance_default_config;
struct nvgpu_gpu_instance_config *gpu_instance_config =
&ga10b_gpu_instance_default_config.gpu_instance_config[0];
int err;
if ((g->mig.usable_gr_syspipe_count ==
ga10b_gpu_instance_config.usable_gr_syspipe_count) &&
@@ -97,9 +98,11 @@ const struct nvgpu_mig_gpu_instance_config *ga10b_grmgr_get_mig_config_ptr(
ga10b_gpu_instance_default_config.gpcgrp_gpc_count[1] =
g->mig.gpcgrp_gpc_count[1];
ga10b_gpu_instance_default_config.gpc_count = g->mig.gpc_count;
snprintf(gpu_instance_config->config_name,
err = snprintf(gpu_instance_config->config_name,
NVGPU_MIG_MAX_CONFIG_NAME_SIZE,
"1 GPU instance with %u GPCs", g->mig.gpc_count);
nvgpu_assert(err > 0);
gpu_instance_config->num_gpu_instances = 1U;
gpu_instance_config->gpu_instance_static_config[0].gpu_instance_id = 0U;
gpu_instance_config->gpu_instance_static_config[0].gr_syspipe_id = 0U;

7
drivers/gpu/nvgpu/os/linux/debug.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2021, NVIDIA Corporation. All rights reserved.
* Copyright (C) 2017-2022, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -59,9 +59,12 @@ static inline void gk20a_debug_write_to_seqfile(void *ctx, const char *str)
void gk20a_debug_output(struct nvgpu_debug_context *o, const char *fmt, ...)
{
va_list args;
int err;
va_start(args, fmt);
vsnprintf(o->buf, sizeof(o->buf), fmt, args);
err = vsnprintf(o->buf, sizeof(o->buf), fmt, args);
nvgpu_assert(err > 0);
va_end(args);
o->fn(o->ctx, o->buf);
}

6
drivers/gpu/nvgpu/os/linux/debug_fecs_trace.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -61,6 +61,10 @@ static int gk20a_fecs_trace_debugfs_ring_seq_show(
u32 tag;
u64 timestamp;
if (r == NULL) {
return -ENOMEM;
}
seq_printf(s, "record #%lld (%p)\n", *pos, r);
seq_printf(s, "\tmagic_lo=%08x\n", r->magic_lo);
seq_printf(s, "\tmagic_hi=%08x\n", r->magic_hi);

4
drivers/gpu/nvgpu/os/linux/ioctl.c
View File

@@ -435,6 +435,7 @@ static int nvgpu_prepare_mig_dev_node_class_list(struct gk20a *g, u32 *num_class
u32 i;
u32 num_instances;
struct nvgpu_cdev_class_priv_data *priv_data;
int err;
num_instances = g->mig.num_gpu_instances;
/*
@@ -446,9 +447,10 @@ static int nvgpu_prepare_mig_dev_node_class_list(struct gk20a *g, u32 *num_class
return -ENOMEM;
}
snprintf(priv_data->class_name, sizeof(priv_data->class_name),
err = snprintf(priv_data->class_name, sizeof(priv_data->class_name),
"nvidia%s-gpu-fgpu%u",
(g->pci_class != 0U) ? "-pci" : "", i);
nvgpu_assert(err > 0);
class = nvgpu_create_class(g, priv_data->class_name);
if (class == NULL) {