From b9050c51c155cd9a2d8b70e60f953c8adf2687ff Mon Sep 17 00:00:00 2001 From: mkumbar Date: Fri, 18 Sep 2020 14:33:31 +0530 Subject: [PATCH] gpu: nvgpu: bootstrap enabled GPC's from SEC2 get floorswept GPC mask and convert to ucode required index mask to bootstrap enabled GPC's using LS SEC2 RTOS ucode Bug 200657884 Change-Id: I0b111bcfb2d4b2c24f67b45e8e93954aeb03d711 Signed-off-by: mkumbar Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2416107 Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Shashank Singh Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c index 6fbd468ad..8f6c35e07 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c @@ -47,6 +47,16 @@ static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g, *command_ack = true; } +static u32 get_gpc_falcon_idx_mask(struct gk20a *g) +{ + struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g); + u32 gpc_fs_mask = 0; + + gpc_fs_mask = nvgpu_gr_config_get_gpc_mask(gr_config); + + return nvgpu_safe_sub_u32((1U << hweight32(gpc_fs_mask)), 1U); +} + static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, u32 falcon_id, u32 flags) { @@ -76,7 +86,7 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, if (falcon_id == FALCON_ID_GPCCS) { cmd.cmd.acr.bootstrap_falcon.falcon_index_mask = - nvgpu_gr_config_get_gpc_mask(nvgpu_gr_get_config_ptr(g)); + get_gpc_falcon_idx_mask(g); } nvgpu_sec2_dbg(g, "NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON : %x",