From b92e8530fcbca7673e1f93027a30228dd0dcf4a2 Mon Sep 17 00:00:00 2001
From: mkumbar <mkumbar@nvidia.com>
Date: Tue, 14 Dec 2021 00:52:11 +0530
Subject: [PATCH] gpu: nvgpu: ga10b: slcg and blcg update for PMU

Load register configuration for SLCG and BLCG for PMU.

Bug 3452217

Change-Id: Ib54077ee00d0b9247db8d792e5ed566fd4ca2efd
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2641365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c b/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
index 28c8f1f2b..65cf21135 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
@@ -395,6 +395,12 @@ int nvgpu_pmu_rtos_init(struct gk20a *g)
 		}
 #endif
 
+		if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
+			/* Load register configuration for SLCG and BLCG for PMU */
+			nvgpu_cg_slcg_pmu_load_enable(g);
+			nvgpu_cg_blcg_pmu_load_enable(g);
+		}
+
 		if (!nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
 			/*
 			 * clear halt interrupt to avoid PMU-RTOS ucode