From b9696ee6439df890319e5220b09dea3f199c8785 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 12 Aug 2021 12:09:27 +0000 Subject: [PATCH] gpu: nvgpu: ga10b: update NVRISCV LSPMU - Set NVRISCV LSPMU app version to 0. - Setting app version to 0 helps to load and boot multiple LSPMU ucode's without modifying the NVGPU driver. - Add support for PMU NVRISCV prod and dbg bin's. - This is corresponding change to LSPMU MPSK CL https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2576049 JIRA NVGPU-7061 Change-Id: I800953ca97af3badde1983aa99e09b4fe7453203 Signed-off-by: Mahantesh Kumbar Signed-off-by: mkumbar Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2575341 Reviewed-by: svc_kernel_abi Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/fw/fw.c | 22 ++++++++++++++++---- drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c | 2 +- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/fw/fw.c b/drivers/gpu/nvgpu/common/pmu/fw/fw.c index 995abb90a..e9f9da6ff 100644 --- a/drivers/gpu/nvgpu/common/pmu/fw/fw.c +++ b/drivers/gpu/nvgpu/common/pmu/fw/fw.c @@ -40,6 +40,9 @@ #define NVGPU_PMU_UCODE_NEXT_IMAGE "gpmu_ucode_next_image.bin" #define NVGPU_PMU_UCODE_NEXT_DESC "gpmu_ucode_next_desc.bin" #define NVGPU_PMU_UCODE_NEXT_SIG "pmu_pkc_sig.bin" +#define NVGPU_PMU_UCODE_NEXT_PROD_IMAGE "gpmu_ucode_next_prod_image.bin" +#define NVGPU_PMU_UCODE_NEXT_PROD_DESC "gpmu_ucode_next_prod_desc.bin" +#define NVGPU_PMU_UCODE_NEXT_PROD_SIG "pmu_pkc_prod_sig.bin" void nvgpu_pmu_fw_get_cmd_line_args_offset(struct gk20a *g, u32 *args_offset) @@ -269,6 +272,8 @@ static int pmu_fw_init_ops(struct gk20a *g, struct nvgpu_pmu *pmu) ncore_desc = (struct falcon_next_core_ucode_desc *)(void *) rtos_fw->fw_desc->data; app_version = ncore_desc->app_version; + nvgpu_pmu_dbg(g, "app version %d ", app_version); + app_version = 0; } else { desc = (struct pmu_ucode_desc *)(void *)rtos_fw->fw_desc->data; app_version = desc->app_version; @@ -304,10 +309,19 @@ int nvgpu_pmu_init_pmu_fw(struct gk20a *g, struct nvgpu_pmu *pmu, *rtos_fw_p = rtos_fw; if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) { - nvgpu_pmu_dbg(g, "FW read for RISCV/PKC\n"); - err = pmu_fw_read(g, NVGPU_PMU_UCODE_NEXT_IMAGE, - NVGPU_PMU_UCODE_NEXT_DESC, - NVGPU_PMU_UCODE_NEXT_SIG); + if (g->ops.pmu.is_debug_mode_enabled(g)) { + nvgpu_pmu_dbg(g, "FW read for DBG RISCV/PKC"); + err = pmu_fw_read(g, + NVGPU_PMU_UCODE_NEXT_IMAGE, + NVGPU_PMU_UCODE_NEXT_DESC, + NVGPU_PMU_UCODE_NEXT_SIG); + } else { + nvgpu_pmu_dbg(g, "FW read for PROD RISCV/PKC"); + err = pmu_fw_read(g, + NVGPU_PMU_UCODE_NEXT_PROD_IMAGE, + NVGPU_PMU_UCODE_NEXT_PROD_DESC, + NVGPU_PMU_UCODE_NEXT_PROD_SIG); + } } else { nvgpu_pmu_dbg(g, "FW read for Falcon/AES\n"); err = pmu_fw_read(g, NVGPU_PMU_UCODE_IMAGE, diff --git a/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c b/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c index e73f3d66e..3ee2296e5 100644 --- a/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c +++ b/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c @@ -40,7 +40,7 @@ #include /* PMU F/W version */ -#define APP_VERSION_NVGPU_NEXT_CORE 30187066U +#define APP_VERSION_NVGPU_NEXT_CORE 0U #define APP_VERSION_NVGPU_NEXT 29323513U #define APP_VERSION_TU10X 28084434U #define APP_VERSION_GV11B 25005711U