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gpu: nvgpu: add flag for non-secure gr falcon related code

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Compile-out non-secure gr falcon boot related code for safety build by
adding non-secure gr falcon related code under following flag:
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT

Added nvgpu_gr_falcon_load_ctxsw_ucode and related functions under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT flag and enabled this flag only
for non-safety builds.

JIRA NVGPU-3741

Change-Id: I817d8a7be6a675eee514faf7bb93f1382c6da5ce
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158935
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-07-22 14:11:14 -07:00
committed by mobile promotions
parent c6b6c9b3e2
commit b9dbea6d5e
8 changed files with 18 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile
View File

@@ -51,6 +51,7 @@ ccflags-y += -DCONFIG_NVGPU_FALCON_NON_FUSA
ccflags-y += -DCONFIG_NVGPU_IOCTL_NON_FUSA
ccflags-y += -DCONFIG_NVGPU_COMMON_NON_FUSA
ccflags-y += -DCONFIG_NVGPU_INJECT_HWERR
ccflags-y += -DCONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
ifeq ($(CONFIG_NVGPU_LOGGING),y)
ccflags-y += -DCONFIG_NVGPU_LOGGING=1

3
drivers/gpu/nvgpu/Makefile.shared.configs
View File

@@ -179,6 +179,9 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_FALCON_NON_FUSA
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_IOCTL_NON_FUSA
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
endif
endif

4
drivers/gpu/nvgpu/common/gr/gr_falcon.c
View File

@@ -388,6 +388,7 @@ clean_up:
return err;
}
#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
static void nvgpu_gr_falcon_load_dmem(struct gk20a *g)
{
u32 ucode_u32_size;
@@ -424,6 +425,7 @@ static void nvgpu_gr_falcon_load_imem(struct gk20a *g)
nvgpu_log_fn(g, "done");
}
#endif
static void nvgpu_gr_falcon_bind_instblk(struct gk20a *g,
struct nvgpu_gr_falcon *falcon)
@@ -481,6 +483,7 @@ static void nvgpu_gr_falcon_load_ctxsw_ucode_segments(
}
#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
static void nvgpu_gr_falcon_load_with_bootloader(struct gk20a *g,
struct nvgpu_gr_falcon *falcon)
{
@@ -532,6 +535,7 @@ int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g,
nvgpu_log_fn(g, "done");
return 0;
}
#endif
static void nvgpu_gr_falcon_load_gpccs_with_bootloader(struct gk20a *g,
struct nvgpu_gr_falcon *falcon)

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -494,8 +494,10 @@ static const struct gpu_ops gm20b_ops = {
gm20b_gr_falcon_load_ctxsw_ucode_header,
.load_ctxsw_ucode_boot =
gm20b_gr_falcon_load_ctxsw_ucode_boot,
#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
.load_ctxsw_ucode =
nvgpu_gr_falcon_load_ctxsw_ucode,
#endif
.wait_mem_scrubbing =
gm20b_gr_falcon_wait_mem_scrubbing,
.wait_ctxsw_ready = gm20b_gr_falcon_wait_ctxsw_ready,

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -561,8 +561,10 @@ static const struct gpu_ops gp10b_ops = {
gm20b_gr_falcon_load_ctxsw_ucode_header,
.load_ctxsw_ucode_boot =
gm20b_gr_falcon_load_ctxsw_ucode_boot,
#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
.load_ctxsw_ucode =
nvgpu_gr_falcon_load_ctxsw_ucode,
#endif
.wait_mem_scrubbing =
gm20b_gr_falcon_wait_mem_scrubbing,
.wait_ctxsw_ready = gm20b_gr_falcon_wait_ctxsw_ready,

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -680,8 +680,10 @@ static const struct gpu_ops gv11b_ops = {
gm20b_gr_falcon_load_ctxsw_ucode_header,
.load_ctxsw_ucode_boot =
gm20b_gr_falcon_load_ctxsw_ucode_boot,
#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
.load_ctxsw_ucode =
nvgpu_gr_falcon_load_ctxsw_ucode,
#endif
.wait_mem_scrubbing =
gm20b_gr_falcon_wait_mem_scrubbing,
.wait_ctxsw_ready = gm20b_gr_falcon_wait_ctxsw_ready,

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1572,8 +1572,10 @@ int tu104_init_hal(struct gk20a *g)
gops->cbc.alloc_comptags = NULL;
#endif
#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
gops->gr.falcon.load_ctxsw_ucode =
nvgpu_gr_falcon_load_ctxsw_ucode;
#endif
/* Disable pmu pstate, as there is no pmu support */
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);

2
drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h
View File

@@ -91,8 +91,10 @@ int nvgpu_gr_falcon_init_ctx_state(struct gk20a *g,
struct nvgpu_gr_falcon *falcon);
int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g,
struct nvgpu_gr_falcon *falcon);
#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g,
struct nvgpu_gr_falcon *falcon);
#endif
int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g,
struct nvgpu_gr_falcon *falcon);