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gpu: nvgpu: split capture_ram_dump api

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This patch splits capture_ram_dump into two parts to separate out
NV_RAMFC_TOP_LEVEL_GET/NV_RAMFC_TOP_LEVEL_GET_HI into a new api. This
split helps in reducing duplication of capture_ram_dump in future chips.

JIRA NVGPU-9325

Change-Id: I4dba2db7c08406af1569e28037b2aa2f2abfc782
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2836197
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2023-01-02 19:24:07 +00:00
committed by mobile promotions
parent 132f9bdab2
commit b9e771ecfc
2 changed files with 22 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -30,6 +30,10 @@ struct nvgpu_channel_dump_info;
int ga10b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags);
void ga10b_ramfc_capture_ram_dump_1(struct gk20a *g,
struct nvgpu_channel *ch, struct nvgpu_channel_dump_info *info);
void ga10b_ramfc_capture_ram_dump_2(struct gk20a *g,
struct nvgpu_channel *ch, struct nvgpu_channel_dump_info *info);
void ga10b_ramfc_capture_ram_dump(struct gk20a *g, struct nvgpu_channel *ch,
struct nvgpu_channel_dump_info *info);
#endif /* NVGPU_RAMFC_GA10B_H */

20
drivers/gpu/nvgpu/hal/fifo/ramfc_ga10b_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -131,14 +131,21 @@ int ga10b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
return 0;
}
void ga10b_ramfc_capture_ram_dump(struct gk20a *g, struct nvgpu_channel *ch,
struct nvgpu_channel_dump_info *info)
void ga10b_ramfc_capture_ram_dump_1(struct gk20a *g,
struct nvgpu_channel *ch, struct nvgpu_channel_dump_info *info)
{
struct nvgpu_mem *mem = &ch->inst_block;
info->inst.pb_top_level_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_top_level_get_w(),
ram_fc_pb_top_level_get_hi_w());
}
void ga10b_ramfc_capture_ram_dump_2(struct gk20a *g,
struct nvgpu_channel *ch, struct nvgpu_channel_dump_info *info)
{
struct nvgpu_mem *mem = &ch->inst_block;
info->inst.pb_put = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_put_w(),
ram_fc_pb_put_hi_w());
@@ -158,3 +165,10 @@ void ga10b_ramfc_capture_ram_dump(struct gk20a *g, struct nvgpu_channel *ch,
info->inst.sem_execute = nvgpu_mem_rd32(g, mem,
ram_fc_sem_execute_w());
}
void ga10b_ramfc_capture_ram_dump(struct gk20a *g, struct nvgpu_channel *ch,
struct nvgpu_channel_dump_info *info)
{
ga10b_ramfc_capture_ram_dump_1(g, ch, info);
ga10b_ramfc_capture_ram_dump_2(g, ch, info);
}