From ba0d76189ea350b9cbc99e3b6492acaf36d8dcd9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 29 Nov 2018 11:32:41 -0800 Subject: [PATCH] gpu: nvgpu: address alloc_blob_space physically Add NVGPU_DMA_PHYSICALLY_ADDRESSED flag for blob_space. Bug 2422486 Change-Id: I44347430ee03b473875d8e49500a08c40ef9194f Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1962057 Reviewed-by: svc-misra-checker Reviewed-by: Thomas Fleury Reviewed-by: svc-mobile-coverity Reviewed-by: Alex Waterman Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/acr_gm20b.c | 3 ++- drivers/gpu/nvgpu/common/pmu/acr_gv11b.c | 14 +------------- drivers/gpu/nvgpu/common/pmu/acr_gv11b.h | 2 -- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c index 2713eb839..efa2abd94 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c +++ b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c @@ -333,7 +333,8 @@ int gm20b_alloc_blob_space(struct gk20a *g, { int err; - err = nvgpu_dma_alloc_sys(g, size, mem); + err = nvgpu_dma_alloc_flags_sys(g, + NVGPU_DMA_PHYSICALLY_ADDRESSED, size, mem); return err; } diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c index 63dd00bd3..bbf1632a2 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c +++ b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c @@ -53,18 +53,6 @@ /*Forwards*/ -int gv11b_alloc_blob_space(struct gk20a *g, - size_t size, struct nvgpu_mem *mem) -{ - int err; - - gv11b_dbg_pmu(g, "alloc blob space: NVGPU_DMA_FORCE_CONTIGUOUS"); - err = nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_FORCE_CONTIGUOUS, - size, mem); - - return err; -} - void gv11b_setup_apertures(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -171,7 +159,7 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) gv11b_acr_default_sw_init(g, &acr->acr); acr->get_wpr_info = gm20b_wpr_info; - acr->alloc_blob_space = gv11b_alloc_blob_space; + acr->alloc_blob_space = gm20b_alloc_blob_space; acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr; acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode; acr->acr_fill_bl_dmem_desc = diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h index 99fe3ea39..5c6fafd19 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h +++ b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h @@ -28,8 +28,6 @@ int gv11b_bootstrap_hs_flcn(struct gk20a *g); int gv11b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz); void gv11b_setup_apertures(struct gk20a *g); -int gv11b_alloc_blob_space(struct gk20a *g, size_t size, - struct nvgpu_mem *mem); void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,