gpu: nvgpu: move init_pdb to ramin HAL

Replaced the following HAL
- mm.init_pdb

With
- ramin.init_pdb

Jira NVGPU-3015

Change-Id: Ie77aad5c5f83ef263b46739a52986296aca05468
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077838
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -236,6 +236,7 @@ nvgpu-y += \
 	hal/fifo/ramfc_tu104.o \
 	hal/fifo/ramin_gk20a.o \
 	hal/fifo/ramin_gm20b.o \
+	hal/fifo/ramin_gp10b.o \
 	hal/fifo/ramin_gv11b.o \
 	hal/fifo/tsg_gk20a.o \
 	hal/fifo/tsg_gv11b.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -368,6 +368,7 @@ srcs += common/sim.c \
 	hal/fifo/ramfc_tu104.c  \
 	hal/fifo/ramin_gk20a.c \
 	hal/fifo/ramin_gm20b.c \
+	hal/fifo/ramin_gp10b.c \
 	hal/fifo/ramin_gv11b.c \
 	hal/fifo/tsg_gk20a.c \
 	hal/fifo/tsg_gv11b.c \

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -26,6 +26,7 @@
 #include "hal/fifo/pbdma_gm20b.h"
 #include "hal/fifo/pbdma_gp10b.h"
 #include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/therm/therm_gm20b.h"
 #include "hal/therm/therm_gp10b.h"
@@ -504,6 +505,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	.ramin = {
 		.set_gr_ptr = NULL,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
+		.init_pdb = gp10b_ramin_init_pdb,
 	},
 	.runlist = {
 		.reschedule = NULL,
@@ -558,7 +560,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.gpu_phys_addr = gm20b_gpu_phys_addr,
 		.get_iommu_bit = gk20a_mm_get_iommu_bit,
 		.get_mmu_levels = gp10b_mm_get_mmu_levels,
-		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = NULL,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
 		.init_inst_block = gk20a_init_inst_block,

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -27,6 +27,7 @@
 #include "hal/fifo/pbdma_gp10b.h"
 #include "hal/fifo/pbdma_gv11b.h"
 #include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/fifo/userd_gv11b.h"
@@ -593,6 +594,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	.ramin = {
 		.set_gr_ptr = NULL,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
+		.init_pdb = gp10b_ramin_init_pdb,
 	},
 	.runlist = {
 		.reschedule = NULL,
@@ -647,7 +649,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.gpu_phys_addr = gm20b_gpu_phys_addr,
 		.get_iommu_bit = gk20a_mm_get_iommu_bit,
 		.get_mmu_levels = gp10b_mm_get_mmu_levels,
-		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = NULL,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
 		.init_inst_block = gv11b_init_inst_block,

drivers/gpu/nvgpu/gk20a/mm_gk20a.c

@@ -373,36 +373,16 @@ int gk20a_vm_bind_channel(struct vm_gk20a *vm, struct channel_gk20a *ch)
 	return err;
 }
 
-void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm)
-{
-	u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
-	u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
-	u32 pdb_addr_hi = u64_hi32(pdb_addr);
-
-	nvgpu_log_info(g, "pde pa=0x%llx", pdb_addr);
-
-	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
-		       nvgpu_aperture_mask(g, vm->pdb.mem,
-				ram_in_page_dir_base_target_sys_mem_ncoh_f(),
-				ram_in_page_dir_base_target_sys_mem_coh_f(),
-				ram_in_page_dir_base_target_vid_mem_f()) |
-		       ram_in_page_dir_base_vol_true_f() |
-		       ram_in_page_dir_base_lo_f(pdb_addr_lo));
-
-	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
-		ram_in_page_dir_base_hi_f(pdb_addr_hi));
-}
-
 void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
 		u32 big_page_size)
 {
 	struct gk20a *g = gk20a_from_vm(vm);
+	u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
 
 	nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
 		nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
 
-	g->ops.mm.init_pdb(g, inst_block, vm);
+	g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
 
 	nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(),
 		u64_lo32(vm->va_limit - 1U) & ~0xfffU);

drivers/gpu/nvgpu/gk20a/mm_gk20a.h

@@ -126,9 +126,6 @@ u32 gk20a_mm_get_iommu_bit(struct gk20a *g);
 
 const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g,
 						      u32 big_page_size);
-void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm);
-
 extern const struct gk20a_mmu_level gk20a_mm_levels_64k[];
 extern const struct gk20a_mmu_level gk20a_mm_levels_128k[];
 

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -699,6 +699,7 @@ static const struct gpu_ops gm20b_ops = {
 	.ramin = {
 		.set_gr_ptr = gk20a_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
+		.init_pdb = gk20a_ramin_init_pdb,
 	},
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
@@ -755,7 +756,6 @@ static const struct gpu_ops gm20b_ops = {
 		.gpu_phys_addr = gm20b_gpu_phys_addr,
 		.get_iommu_bit = gk20a_mm_get_iommu_bit,
 		.get_mmu_levels = gk20a_mm_get_mmu_levels,
-		.init_pdb = gk20a_mm_init_pdb,
 		.init_mm_setup_hw = gk20a_init_mm_setup_hw,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
 		.alloc_inst_block = gk20a_alloc_inst_block,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -71,6 +71,7 @@
 #include "hal/fifo/ramfc_gp10b.h"
 #include "hal/fifo/ramin_gk20a.h"
 #include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/tsg_gk20a.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/fifo/fifo_intr_gk20a.h"
@@ -786,6 +787,7 @@ static const struct gpu_ops gp10b_ops = {
 	.ramin = {
 		.set_gr_ptr = gk20a_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
+		.init_pdb = gp10b_ramin_init_pdb,
 	},
 	.runlist = {
 		.reschedule = gk20a_runlist_reschedule,
@@ -845,7 +847,6 @@ static const struct gpu_ops gp10b_ops = {
 		.gpu_phys_addr = gm20b_gpu_phys_addr,
 		.get_iommu_bit = gp10b_mm_get_iommu_bit,
 		.get_mmu_levels = gp10b_mm_get_mmu_levels,
-		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = gk20a_init_mm_setup_hw,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
 		.alloc_inst_block = gk20a_alloc_inst_block,

drivers/gpu/nvgpu/gp10b/mm_gp10b.c

@@ -415,29 +415,6 @@ const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g,
 	return gp10b_mm_levels;
 }
 
-void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm)
-{
-	u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
-	u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
-	u32 pdb_addr_hi = u64_hi32(pdb_addr);
-
-	nvgpu_log_info(g, "pde pa=0x%llx", pdb_addr);
-
-	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
-		nvgpu_aperture_mask(g, vm->pdb.mem,
-				ram_in_page_dir_base_target_sys_mem_ncoh_f(),
-				ram_in_page_dir_base_target_sys_mem_coh_f(),
-				ram_in_page_dir_base_target_vid_mem_f()) |
-		ram_in_page_dir_base_vol_true_f() |
-		ram_in_big_page_size_64kb_f() |
-		ram_in_page_dir_base_lo_f(pdb_addr_lo) |
-		ram_in_use_ver2_pt_format_true_f());
-
-	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
-		ram_in_page_dir_base_hi_f(pdb_addr_hi));
-}
-
 void gp10b_remove_bar2_vm(struct gk20a *g)
 {
 	struct mm_gk20a *mm = &g->mm;

drivers/gpu/nvgpu/gp10b/mm_gp10b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -33,8 +33,6 @@ u32 gp10b_mm_get_iommu_bit(struct gk20a *g);
 int gp10b_init_bar2_vm(struct gk20a *g);
 const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g,
 	u32 big_page_size);
-void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm);
 void gp10b_remove_bar2_vm(struct gk20a *g);
 
 #endif

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -59,6 +59,7 @@
 #include "hal/fifo/ramfc_gp10b.h"
 #include "hal/fifo/ramfc_gv11b.h"
 #include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/ramin_gv11b.h"
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
@@ -971,6 +972,7 @@ static const struct gpu_ops gv100_ops = {
 	.ramin = {
 		.set_gr_ptr = gv11b_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
+		.init_pdb = gp10b_ramin_init_pdb,
 	},
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
@@ -1027,7 +1029,6 @@ static const struct gpu_ops gv100_ops = {
 		.get_default_big_page_size = gp10b_mm_get_default_big_page_size,
 		.gpu_phys_addr = gv11b_gpu_phys_addr,
 		.get_mmu_levels = gp10b_mm_get_mmu_levels,
-		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = gv11b_init_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
 		.alloc_inst_block = gk20a_alloc_inst_block,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -60,6 +60,7 @@
 #include "hal/fifo/ramfc_gp10b.h"
 #include "hal/fifo/ramfc_gv11b.h"
 #include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/ramin_gv11b.h"
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
@@ -926,6 +927,7 @@ static const struct gpu_ops gv11b_ops = {
 	.ramin = {
 		.set_gr_ptr = gv11b_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
+		.init_pdb = gp10b_ramin_init_pdb,
 	},
 	.runlist = {
 		.reschedule = gv11b_runlist_reschedule,
@@ -985,7 +987,6 @@ static const struct gpu_ops gv11b_ops = {
 		.gpu_phys_addr = gv11b_gpu_phys_addr,
 		.get_iommu_bit = gp10b_mm_get_iommu_bit,
 		.get_mmu_levels = gp10b_mm_get_mmu_levels,
-		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = gv11b_init_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
 		.alloc_inst_block = gk20a_alloc_inst_block,

drivers/gpu/nvgpu/gv11b/mm_gv11b.c

@@ -1,7 +1,7 @@
 /*
  * GV11B MMU
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -49,11 +49,12 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block,
 		struct vm_gk20a *vm, u32 big_page_size)
 {
 	struct gk20a *g = gk20a_from_vm(vm);
+	u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
 
 	nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
 		nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
 
-	g->ops.mm.init_pdb(g, inst_block, vm);
+	g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
 
 	if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
 		g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);

drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c

@@ -42,3 +42,24 @@ void gk20a_ramin_set_gr_ptr(struct gk20a *g,
 	nvgpu_mem_wr32(g, inst_block, ram_in_gr_wfi_ptr_hi_w(),
 		 ram_in_gr_wfi_ptr_hi_f(addr_hi));
 }
+
+void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
+		u64 pdb_addr, struct nvgpu_mem *pdb_mem)
+{
+	u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
+	u32 pdb_addr_hi = u64_hi32(pdb_addr);
+
+	nvgpu_log_info(g, "pde pa=0x%llx", pdb_addr);
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
+		       nvgpu_aperture_mask(g, pdb_mem,
+				ram_in_page_dir_base_target_sys_mem_ncoh_f(),
+				ram_in_page_dir_base_target_sys_mem_coh_f(),
+				ram_in_page_dir_base_target_vid_mem_f()) |
+		       ram_in_page_dir_base_vol_true_f() |
+		       ram_in_page_dir_base_lo_f(pdb_addr_lo));
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
+		ram_in_page_dir_base_hi_f(pdb_addr_hi));
+}
+

drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h

@@ -29,5 +29,7 @@ struct nvgpu_mem;
 
 void gk20a_ramin_set_gr_ptr(struct gk20a *g,
 		struct nvgpu_mem *inst_block, u64 gpu_va);
+void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
+		u64 pdb_addr, struct nvgpu_mem *pdb_mem);
 
 #endif /* NVGPU_RAMIN_GK20A_H */

drivers/gpu/nvgpu/hal/fifo/ramin_gp10b.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/channel.h>
+
+#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
+
+#include "hal/fifo/ramin_gp10b.h"
+
+void gp10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
+		u64 pdb_addr, struct nvgpu_mem *pdb_mem)
+{
+	u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
+	u32 pdb_addr_hi = u64_hi32(pdb_addr);
+
+	nvgpu_log_info(g, "pde pa=0x%llx", pdb_addr);
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
+		nvgpu_aperture_mask(g, pdb_mem,
+				ram_in_page_dir_base_target_sys_mem_ncoh_f(),
+				ram_in_page_dir_base_target_sys_mem_coh_f(),
+				ram_in_page_dir_base_target_vid_mem_f()) |
+		ram_in_page_dir_base_vol_true_f() |
+		ram_in_big_page_size_64kb_f() |
+		ram_in_page_dir_base_lo_f(pdb_addr_lo) |
+		ram_in_use_ver2_pt_format_true_f());
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
+		ram_in_page_dir_base_hi_f(pdb_addr_hi));
+}

drivers/gpu/nvgpu/hal/fifo/ramin_gp10b.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef RAMIN_GP10B_H
+#define RAMIN_GP10B_H
+
+struct gk20a;
+struct nvgpu_mem;
+
+void gp10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
+		u64 pdb_addr, struct nvgpu_mem *pdb_mem);
+
+#endif

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1022,6 +1022,8 @@ struct gpu_ops {
 				struct nvgpu_mem *inst_block, u64 gpu_va);
 		void (*set_big_page_size)(struct gk20a *g,
 				struct nvgpu_mem *mem, u32 size);
+		void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block,
+				u64 pdb_addr, struct nvgpu_mem *pdb_mem);
 	} ramin;
 	struct {
 		int (*reschedule)(struct channel_gk20a *ch, bool preempt_next);
@@ -1300,8 +1302,6 @@ struct gpu_ops {
 		void (*remove_bar2_vm)(struct gk20a *g);
 		const struct gk20a_mmu_level *
 			(*get_mmu_levels)(struct gk20a *g, u32 big_page_size);
-		void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block,
-				struct vm_gk20a *vm);
 		u64 (*gpu_phys_addr)(struct gk20a *g,
 				     struct nvgpu_gmmu_attrs *attrs, u64 phys);
 		int (*alloc_inst_block)(struct gk20a *g,

drivers/gpu/nvgpu/libnvgpu-drv.export

@@ -38,7 +38,7 @@ gp10b_init_bar2_vm
 gp10b_mm_get_default_big_page_size
 gp10b_mm_get_iommu_bit
 gp10b_mm_get_mmu_levels
-gp10b_mm_init_pdb
+gp10b_ramin_init_pdb
 gp10b_remove_bar2_vm
 gv11b_channel_count
 gv11b_fb_enable_hub_intr

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -64,6 +64,7 @@
 #include "hal/fifo/ramfc_gv11b.h"
 #include "hal/fifo/ramfc_tu104.h"
 #include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/ramin_gv11b.h"
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
@@ -1009,6 +1010,7 @@ static const struct gpu_ops tu104_ops = {
 	.ramin = {
 		.set_gr_ptr = gv11b_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
+		.init_pdb = gp10b_ramin_init_pdb,
 	},
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
@@ -1065,7 +1067,6 @@ static const struct gpu_ops tu104_ops = {
 		.get_default_big_page_size = gp10b_mm_get_default_big_page_size,
 		.gpu_phys_addr = gv11b_gpu_phys_addr,
 		.get_mmu_levels = gp10b_mm_get_mmu_levels,
-		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = gv11b_init_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
 		.alloc_inst_block = gk20a_alloc_inst_block,

userspace/units/mm/gmmu/page_table/page_table.c

@@ -43,6 +43,7 @@
 
 #include <hal/fb/fb_gp10b.h>
 #include <hal/fb/fb_gm20b.h>
+#include <hal/fifo/ramin_gp10b.h>
 
 #define TEST_PA_ADDRESS     0xEFAD80000000
 #define TEST_GPU_VA         0x102040600000
@@ -297,13 +298,13 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	g->ops.mm.get_mmu_levels = gp10b_mm_get_mmu_levels;
 	g->ops.mm.alloc_inst_block = gk20a_alloc_inst_block;
 	g->ops.mm.init_inst_block = gv11b_init_inst_block;
-	g->ops.mm.init_pdb = gp10b_mm_init_pdb;
 	g->ops.mm.gmmu_map = gk20a_locked_gmmu_map;
 	g->ops.mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
 	g->ops.mm.gpu_phys_addr = gv11b_gpu_phys_addr;
 	g->ops.mm.is_bar1_supported = gv11b_mm_is_bar1_supported;
 	g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
 	g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
+	g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
 
 	if (g->ops.mm.is_bar1_supported(g)) {
 		unit_return_fail(m, "BAR1 is not supported on Volta+\n");

userspace/units/mm/page_table_faults/page_table_faults.c

@@ -47,6 +47,7 @@
 #include "hal/fb/fb_gm20b.h"
 #include "hal/fb/fb_gv11b.h"
 #include "hal/fifo/ramin_gm20b.h"
+#include "hal/fifo/ramin_gp10b.h"
 
 #define TEST_PA_ADDRESS 0xEFAD80000000
 #define TEST_COMP_TAG 0xEF
@@ -116,12 +117,12 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	g->ops.mm.get_mmu_levels = gp10b_mm_get_mmu_levels;
 	g->ops.mm.alloc_inst_block = gk20a_alloc_inst_block;
 	g->ops.mm.init_inst_block = gv11b_init_inst_block;
-	g->ops.mm.init_pdb = gp10b_mm_init_pdb;
 	g->ops.mm.gmmu_map = gk20a_locked_gmmu_map;
 	g->ops.mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
 	g->ops.mm.gpu_phys_addr = gv11b_gpu_phys_addr;
 	g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
 	g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
+	g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
 
 	/* New HALs for fault testing */
 	g->ops.mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending;