gpu: nvgpu: vgpu: retrieve gpu load

Add support to send command to RM server to retrieve
GPU load.

Bug 200261903

Change-Id: Ie3d0ba7ec91317e9a2911f71613ad78d20f9c1fb
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: http://git-master/r/1275045
(cherry picked from commit 5a6c1de1e6997bfd803b4b95b3e44e282ba32f67)
Reviewed-on: http://git-master/r/1283279
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Aparna Das
2016-12-21 12:35:08 -08:00
committed by mobile promotions
parent 4feb078717
commit bad0572cb1
5 changed files with 61 additions and 1 deletions

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@@ -115,7 +115,8 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
vgpu/gk20a/vgpu_hal_gk20a.o \ vgpu/gk20a/vgpu_hal_gk20a.o \
vgpu/gk20a/vgpu_gr_gk20a.o \ vgpu/gk20a/vgpu_gr_gk20a.o \
vgpu/gm20b/vgpu_hal_gm20b.o \ vgpu/gm20b/vgpu_hal_gm20b.o \
vgpu/gm20b/vgpu_gr_gm20b.o vgpu/gm20b/vgpu_gr_gm20b.o \
vgpu/sysfs_vgpu.o
nvgpu-$(CONFIG_TEGRA_CLK_FRAMEWORK) += gk20a/clk_gk20a.o nvgpu-$(CONFIG_TEGRA_CLK_FRAMEWORK) += gk20a/clk_gk20a.o
ifneq (,$filter y,$(CONFIG_TEGRA_CLK_FRAMEWORK),$(CONFIG_COMMON_CLK)) ifneq (,$filter y,$(CONFIG_TEGRA_CLK_FRAMEWORK),$(CONFIG_COMMON_CLK))

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@@ -0,0 +1,48 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/gk20a.h>
#include "vgpu/vgpu.h"
static ssize_t vgpu_load_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct gk20a *g = get_gk20a(dev);
struct tegra_vgpu_cmd_msg msg = {0};
struct tegra_vgpu_gpu_load_params *p = &msg.params.gpu_load;
int err;
msg.cmd = TEGRA_VGPU_CMD_GET_GPU_LOAD;
msg.handle = vgpu_get_handle(g);
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
if (err)
return err;
return snprintf(buf, PAGE_SIZE, "%u\n", p->load);
}
static DEVICE_ATTR(load, S_IRUGO, vgpu_load_show, NULL);
void vgpu_create_sysfs(struct device *dev)
{
if (device_create_file(dev, &dev_attr_load))
dev_err(dev, "Failed to create vgpu sysfs attributes!\n");
}
void vgpu_remove_sysfs(struct device *dev)
{
device_remove_file(dev, &dev_attr_load);
}

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@@ -632,6 +632,7 @@ int vgpu_probe(struct platform_device *pdev)
CONFIG_GK20A_DEFAULT_TIMEOUT; CONFIG_GK20A_DEFAULT_TIMEOUT;
gk20a->timeouts_enabled = true; gk20a->timeouts_enabled = true;
vgpu_create_sysfs(dev);
gk20a_init_gr(gk20a); gk20a_init_gr(gk20a);
return 0; return 0;
@@ -650,6 +651,7 @@ int vgpu_remove(struct platform_device *pdev)
vgpu_comm_deinit(); vgpu_comm_deinit();
gk20a_sched_ctrl_cleanup(g); gk20a_sched_ctrl_cleanup(g);
gk20a_user_deinit(dev, &nvgpu_class); gk20a_user_deinit(dev, &nvgpu_class);
vgpu_remove_sysfs(dev);
gk20a_get_platform(dev)->g = NULL; gk20a_get_platform(dev)->g = NULL;
kfree(g); kfree(g);
return 0; return 0;

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@@ -103,6 +103,9 @@ int vgpu_gk20a_init_hal(struct gk20a *g);
int vgpu_gm20b_init_hal(struct gk20a *g); int vgpu_gm20b_init_hal(struct gk20a *g);
void vgpu_init_dbg_session_ops(struct gpu_ops *gops); void vgpu_init_dbg_session_ops(struct gpu_ops *gops);
void vgpu_create_sysfs(struct device *dev);
void vgpu_remove_sysfs(struct device *dev);
#else #else
static inline int vgpu_pm_prepare_poweroff(struct device *dev) static inline int vgpu_pm_prepare_poweroff(struct device *dev)
{ {

View File

@@ -99,6 +99,7 @@ enum {
TEGRA_VGPU_CMD_GET_CONSTANTS = 62, TEGRA_VGPU_CMD_GET_CONSTANTS = 62,
TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63, TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63,
TEGRA_VGPU_CMD_TSG_OPEN = 64, TEGRA_VGPU_CMD_TSG_OPEN = 64,
TEGRA_VGPU_CMD_GET_GPU_LOAD = 65,
}; };
struct tegra_vgpu_connect_params { struct tegra_vgpu_connect_params {
@@ -454,6 +455,10 @@ struct tegra_vgpu_channel_cyclestats_snapshot_params {
u8 hw_overflow; u8 hw_overflow;
}; };
struct tegra_vgpu_gpu_load_params {
u32 load;
};
struct tegra_vgpu_cmd_msg { struct tegra_vgpu_cmd_msg {
u32 cmd; u32 cmd;
int ret; int ret;
@@ -500,6 +505,7 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate; struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate;
struct tegra_vgpu_constants_params constants; struct tegra_vgpu_constants_params constants;
struct tegra_vgpu_channel_cyclestats_snapshot_params cyclestats_snapshot; struct tegra_vgpu_channel_cyclestats_snapshot_params cyclestats_snapshot;
struct tegra_vgpu_gpu_load_params gpu_load;
char padding[192]; char padding[192];
} params; } params;
}; };