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gpu: nvgpu: unit: add nvgpu.common.init unit test
This creates the basic test and validates all interfaces besides poweron and poweroff. JIRA NVGPU-3642 Change-Id: Idd36a1d7eaa8b459500ca642c742396dea677ff2 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2182348 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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userspace/units/init/nvgpu-init.c
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263
userspace/units/init/nvgpu-init.c
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <unit/unit.h>
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#include <unit/io.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/hal_init.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
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#include "nvgpu-init.h"
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/* value for GV11B */
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#define MC_BOOT_0_GV11B ((0x15 << 24) | (0xB << 20))
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/* to set the security fuses */
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#define GP10B_FUSE_REG_BASE 0x00021000U
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#define GP10B_FUSE_OPT_PRIV_SEC_EN (GP10B_FUSE_REG_BASE+0x434U)
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/*
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* Mock I/O
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*/
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/*
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* Write callback. Forward the write access to the mock IO framework.
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*/
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static void writel_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
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}
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/*
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* Read callback. Get the register value from the mock IO framework.
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*/
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static void readl_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
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}
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static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
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/* Write APIs all can use the same accessor. */
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.writel = writel_access_reg_fn,
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.writel_check = writel_access_reg_fn,
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.bar1_writel = writel_access_reg_fn,
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.usermode_writel = writel_access_reg_fn,
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/* Likewise for the read APIs. */
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.__readl = readl_access_reg_fn,
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.readl = readl_access_reg_fn,
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.bar1_readl = readl_access_reg_fn,
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};
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/* generic replacement functions that can be assigned to function pointers */
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static void no_return(struct gk20a *g)
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{
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/* noop */
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}
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static int test_setup_env(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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/* Create mc register space */
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nvgpu_posix_io_init_reg_space(g);
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if (nvgpu_posix_io_add_reg_space(g, mc_boot_0_r(), 0xfff) != 0) {
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unit_err(m, "%s: failed to create register space\n",
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__func__);
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return UNIT_FAIL;
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}
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/* Create fuse register space */
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if (nvgpu_posix_io_add_reg_space(g, GP10B_FUSE_REG_BASE, 0xfff) != 0) {
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unit_err(m, "%s: failed to create register space\n",
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__func__);
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return UNIT_FAIL;
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}
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(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
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return UNIT_SUCCESS;
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}
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static int test_free_env(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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/* Free mc register space */
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nvgpu_posix_io_delete_reg_space(g, mc_boot_0_r());
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nvgpu_posix_io_delete_reg_space(g, GP10B_FUSE_REG_BASE);
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return UNIT_SUCCESS;
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}
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static int test_can_busy(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int ret = UNIT_SUCCESS;
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nvgpu_set_enabled(g, NVGPU_KERNEL_IS_DYING, false);
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, false);
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if (nvgpu_can_busy(g) != 1) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_can_busy() returned 0\n");
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}
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nvgpu_set_enabled(g, NVGPU_KERNEL_IS_DYING, true);
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, false);
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if (nvgpu_can_busy(g) != 0) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_can_busy() returned 1\n");
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}
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nvgpu_set_enabled(g, NVGPU_KERNEL_IS_DYING, false);
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
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if (nvgpu_can_busy(g) != 0) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_can_busy() returned 1\n");
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}
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nvgpu_set_enabled(g, NVGPU_KERNEL_IS_DYING, true);
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
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if (nvgpu_can_busy(g) != 0) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_can_busy() returned 1\n");
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}
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return ret;
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}
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static int test_get_put(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int ret = UNIT_SUCCESS;
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nvgpu_ref_init(&g->refcount);
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if (g != nvgpu_get(g)) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_get() returned NULL\n");
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}
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if (nvgpu_atomic_read(&g->refcount.refcount) != 2) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_get() did not increment refcount\n");
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}
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nvgpu_put(g);
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if (nvgpu_atomic_read(&g->refcount.refcount) != 1) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_put() did not decrement refcount\n");
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}
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/* one more to get to 0 to teardown */
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nvgpu_put(g);
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if (nvgpu_atomic_read(&g->refcount.refcount) != 0) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_put() did not decrement refcount\n");
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}
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/* This is expected to fail */
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if (nvgpu_get(g) != NULL) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_get() did not return NULL\n");
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}
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if (nvgpu_atomic_read(&g->refcount.refcount) != 0) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_get() did not increment refcount\n");
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}
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/* start over */
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nvgpu_ref_init(&g->refcount);
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/* to cover the cases where these are set */
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g->remove_support = no_return;
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g->gfree = no_return;
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if (g != nvgpu_get(g)) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_get() returned NULL\n");
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}
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if (nvgpu_atomic_read(&g->refcount.refcount) != 2) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_get() did not increment refcount\n");
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}
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nvgpu_put(g);
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if (nvgpu_atomic_read(&g->refcount.refcount) != 1) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_put() did not decrement refcount\n");
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}
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/* one more to get to 0 to teardown */
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nvgpu_put(g);
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if (nvgpu_atomic_read(&g->refcount.refcount) != 0) {
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ret = UNIT_FAIL;
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unit_err(m, "nvgpu_put() did not decrement refcount\n");
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}
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return ret;
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}
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static int test_check_gpu_state(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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/* Valid state */
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nvgpu_posix_io_writel_reg_space(g, mc_boot_0_r(), MC_BOOT_0_GV11B);
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nvgpu_check_gpu_state(g);
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/*
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* Test INVALID state. This should cause a kernel_restart() which
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* is a BUG() in posix, so verify we hit the BUG().
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*/
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nvgpu_posix_io_writel_reg_space(g, mc_boot_0_r(), U32_MAX);
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if (!EXPECT_BUG(nvgpu_check_gpu_state(g))) {
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unit_err(m, "%s: failed to detect INVALID state\n",
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__func__);
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return UNIT_FAIL;
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}
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return UNIT_SUCCESS;
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}
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static int test_hal_init(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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nvgpu_posix_io_writel_reg_space(g, mc_boot_0_r(), MC_BOOT_0_GV11B);
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nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x0);
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if (nvgpu_detect_chip(g) != 0) {
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unit_err(m, "%s: failed to init HAL\n", __func__);
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return UNIT_FAIL;
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}
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return UNIT_SUCCESS;
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}
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struct unit_module_test init_tests[] = {
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UNIT_TEST(init_setup_env, test_setup_env, NULL, 0),
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UNIT_TEST(init_can_busy, test_can_busy, NULL, 0),
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UNIT_TEST(init_get_put, test_get_put, NULL, 0),
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UNIT_TEST(init_check_gpu_state, test_check_gpu_state, NULL, 0),
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UNIT_TEST(init_hal_init, test_hal_init, NULL, 0),
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UNIT_TEST(init_free_env, test_free_env, NULL, 0),
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};
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UNIT_MODULE(init, init_tests, UNIT_PRIO_NVGPU_TEST);
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