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gpu: nvgpu: update common.gr doxygen

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Add below updates to common.gr doxygen:

- Add doxygen comments for APIs that are mentioned in RM SWAD and in
  RM-common.gr traceability document.
- Comment about valid ranges for input parameters of bunch of functions.
- Add nvgpu_assert() to ensure correct value is passed as input
  parameter to number of functions.
- Add references to relevant functions with @see.
- Update Targets field for unit tests to cover newly doxygenated
  functions.
- Update unit test test_gr_init_hal_pd_skip_table_gpc to take care of
  new asserts added into some APIs.

Jira NVGPU-6180

Change-Id: Ie889bed96b6428b1fd86dcf30b322944464e9d12
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2469397
(cherry picked from commit 5d7d7e9ce1c4efe836ab842d7962a3aee4e8972f)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2469394
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2021-01-04 17:12:50 +05:30
committed by mobile promotions
parent 27b321e1a9
commit bb43f11a61
17 changed files with 208 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
userspace/units/gr/falcon/nvgpu-gr-falcon-gm20b.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -44,7 +44,9 @@ struct gk20a;
* Input: #test_fifo_init_support() run for this GPU
*
* Targets: gm20b_gr_falcon_wait_mem_scrubbing,
* gops_gr_falcon.wait_mem_scrubbing,
* gm20b_gr_falcon_wait_ctxsw_ready,
* gops_gr_falcon.wait_ctxsw_ready,
* gm20b_gr_falcon_init_ctx_state,
* gm20b_gr_falcon_submit_fecs_method_op,
* nvgpu_gr_get_falcon_ptr,

16
userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -596,14 +596,16 @@ static int test_gr_init_hal_pd_skip_table_gpc(struct gk20a *g)
* value is reflected in each loop
*/
for (i = 0; i < gr_pd_dist_skip_table__size_1_v(); i++) {
config->gpc_skip_mask[i] = 0x1;
if (i < nvgpu_gr_config_get_gpc_count(config)) {
config->gpc_skip_mask[i] = 0x1;
g->ops.gr.init.pd_skip_table_gpc(g, config);
if (nvgpu_readl(g, gr_pd_dist_skip_table_r(i / 4)) == 0x0) {
return UNIT_FAIL;
g->ops.gr.init.pd_skip_table_gpc(g, config);
if (nvgpu_readl(g, gr_pd_dist_skip_table_r(i / 4)) == 0x0) {
return UNIT_FAIL;
}
config->gpc_skip_mask[i] = 0x0;
}
config->gpc_skip_mask[i] = 0x0;
}
/* All skip_masks are unset in above loop already */

4
userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -222,7 +222,7 @@ int test_gr_init_hal_ecc_scrub_reg(struct unit_module *m,
* size of alpha_cb and attrib_cb. Then call g->ops.gr.init.get_attrib_cb_size
* and g->ops.gr.init.get_alpha_cb_size and verify if expected size is
* returned in response.
* - Set gpc_skip_masks for all the GPCs and call g->ops.gr.init.pd_skip_table_gpc.
* - Set gpc_skip_masks for available GPCs and call g->ops.gr.init.pd_skip_table_gpc.
* Ensure that skip mask is reflected in h/w register.
* Unset all the gpc_skip_masks and ensure skip mask is unset in h/w register.
* Skip mask should be zero in h/w register only if all the skip masks are zero.