diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index e20be65e8..77f33013e 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -297,6 +297,9 @@ nvgpu-y += \
 	gm20b/mm_gm20b.o \
 	gm20b/regops_gm20b.o
 
+nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \
+	tu104/fecs_trace_tu104.o \
+
 nvgpu-$(CONFIG_GK20A_VIDMEM) += \
 	common/mm/vidmem.o
 
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
index e663a461d..68f506576 100644
--- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
@@ -603,4 +603,9 @@ void gk20a_fecs_trace_reset_buffer(struct gk20a *g)
 	gk20a_fecs_trace_set_read_index(g,
 		gk20a_fecs_trace_get_write_index(g));
 }
+
+u32 gk20a_fecs_trace_get_buffer_full_mailbox_val(void)
+{
+	return 0x26;
+}
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
index 60c5b84d1..93b03da76 100644
--- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
@@ -42,5 +42,6 @@ int gk20a_fecs_trace_disable(struct gk20a *g);
 bool gk20a_fecs_trace_is_enabled(struct gk20a *g);
 size_t gk20a_fecs_trace_buffer_size(struct gk20a *g);
 void gk20a_fecs_trace_reset_buffer(struct gk20a *g);
+u32 gk20a_fecs_trace_get_buffer_full_mailbox_val(void);
 
 #endif /* NVGPU_GK20A_FECS_TRACE_GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 9a8978000..ac388dcf2 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5064,23 +5064,27 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
 				"cannot ctxsw anymore !!", chid);
 		g->ops.gr.dump_gr_falcon_stats(g);
 	} else if ((gr_fecs_intr &
-		gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
+		    gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
 		u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
 
-		if (mailbox_value == MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL) {
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+		if (mailbox_value ==
+			      g->ops.fecs_trace.get_buffer_full_mailbox_val()) {
 			nvgpu_info(g, "ctxsw intr0 set by ucode, "
 					"timestamp buffer full");
-#ifdef CONFIG_GK20A_CTXSW_TRACE
 			gk20a_fecs_trace_reset_buffer(g);
-#else
-			ret = -1;
-#endif
 		} else {
 			nvgpu_err(g,
-			  "ctxsw intr0 set by ucode, error_code: 0x%08x",
-			  mailbox_value);
+				 "ctxsw intr0 set by ucode, error_code: 0x%08x",
+				 mailbox_value);
 			ret = -1;
 		}
+#else
+		nvgpu_err(g,
+			 "ctxsw intr0 set by ucode, error_code: 0x%08x",
+			 mailbox_value);
+		ret = -1;
+#endif
 	} else {
 		nvgpu_err(g,
 			"unhandled fecs error interrupt 0x%08x for channel %u",
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index d3df14344..453b417cb 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -69,8 +69,6 @@
 #define CTXSW_INTR0				BIT32(0)
 #define CTXSW_INTR1				BIT32(1)
 
-#define MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL	0x26
-
 struct tsg_gk20a;
 struct channel_gk20a;
 struct nvgpu_warpstate;
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index d7d5d1f55..3a21bdc56 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -630,6 +630,8 @@ static const struct gpu_ops gp10b_ops = {
 		.bind_channel = gk20a_fecs_trace_bind_channel,
 		.unbind_channel = gk20a_fecs_trace_unbind_channel,
 		.max_entries = gk20a_gr_max_entries,
+		.get_buffer_full_mailbox_val =
+			gk20a_fecs_trace_get_buffer_full_mailbox_val,
 	},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 	.mm = {
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index f76f059e2..6339130ac 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -805,6 +805,8 @@ static const struct gpu_ops gv100_ops = {
 		.bind_channel = gk20a_fecs_trace_bind_channel,
 		.unbind_channel = gk20a_fecs_trace_unbind_channel,
 		.max_entries = gk20a_gr_max_entries,
+		.get_buffer_full_mailbox_val =
+			gk20a_fecs_trace_get_buffer_full_mailbox_val,
 	},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 	.mm = {
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index f07300c11..9ff357445 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -759,6 +759,8 @@ static const struct gpu_ops gv11b_ops = {
 		.bind_channel = gk20a_fecs_trace_bind_channel,
 		.unbind_channel = gk20a_fecs_trace_unbind_channel,
 		.max_entries = gk20a_gr_max_entries,
+		.get_buffer_full_mailbox_val =
+			gk20a_fecs_trace_get_buffer_full_mailbox_val,
 	},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 	.mm = {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index c304d7173..0777710fb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1039,6 +1039,7 @@ struct gpu_ops {
 					struct vm_area_struct *vma);
 		int (*set_filter)(struct gk20a *g,
 			struct nvgpu_gpu_ctxsw_trace_filter *filter);
+		u32 (*get_buffer_full_mailbox_val)(void);
 	} fecs_trace;
 #endif
 	struct {
diff --git a/drivers/gpu/nvgpu/tu104/fecs_trace_tu104.c b/drivers/gpu/nvgpu/tu104/fecs_trace_tu104.c
new file mode 100644
index 000000000..d98f87ebe
--- /dev/null
+++ b/drivers/gpu/nvgpu/tu104/fecs_trace_tu104.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "fecs_trace_tu104.h"
+
+u32 tu104_fecs_trace_get_buffer_full_mailbox_val(void)
+{
+	return 0x32;
+}
diff --git a/drivers/gpu/nvgpu/tu104/fecs_trace_tu104.h b/drivers/gpu/nvgpu/tu104/fecs_trace_tu104.h
new file mode 100644
index 000000000..7c586a4dd
--- /dev/null
+++ b/drivers/gpu/nvgpu/tu104/fecs_trace_tu104.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FECS_TRACE_TU104_H
+#define NVGPU_FECS_TRACE_TU104_H
+
+#include <nvgpu/types.h>
+
+u32 tu104_fecs_trace_get_buffer_full_mailbox_val(void);
+
+#endif /* NVGPU_FECS_TRACE_TU104_H */
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index 1acaf4e58..810b0805e 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -125,6 +125,7 @@
 #include "tu104/ecc_tu104.h"
 #include "tu104/hal_tu104.h"
 #include "tu104/regops_tu104.h"
+#include "tu104/fecs_trace_tu104.h"
 
 #include <nvgpu/ptimer.h>
 #include <nvgpu/debug.h>
@@ -835,6 +836,8 @@ static const struct gpu_ops tu104_ops = {
 		.bind_channel = gk20a_fecs_trace_bind_channel,
 		.unbind_channel = gk20a_fecs_trace_unbind_channel,
 		.max_entries = gk20a_gr_max_entries,
+		.get_buffer_full_mailbox_val =
+			tu104_fecs_trace_get_buffer_full_mailbox_val,
 	},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 	.mm = {
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index bf147ef52..5aaef8da3 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -64,6 +64,8 @@
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/mm_gm20b.h"
 
+#include "gk20a/fecs_trace_gk20a.h"
+
 #include <nvgpu/debugger.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/vgpu/vgpu.h>
@@ -451,6 +453,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.unbind_channel = NULL,
 		.max_entries = vgpu_fecs_trace_max_entries,
 		.set_filter = vgpu_fecs_trace_set_filter,
+		.get_buffer_full_mailbox_val =
+			gk20a_fecs_trace_get_buffer_full_mailbox_val,
 	},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 	.mm = {
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 05c71f94e..c9f449df1 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -77,6 +77,8 @@
 
 #include <gv100/gr_gv100.h>
 
+#include "gk20a/fecs_trace_gk20a.h"
+
 #include <nvgpu/debugger.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/channel.h>
@@ -529,6 +531,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.unbind_channel = NULL,
 		.max_entries = vgpu_fecs_trace_max_entries,
 		.set_filter = vgpu_fecs_trace_set_filter,
+		.get_buffer_full_mailbox_val =
+			gk20a_fecs_trace_get_buffer_full_mailbox_val,
 	},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 	.mm = {