diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
index c3ef0a261..94b3a21c8 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
@@ -486,7 +486,7 @@ static int gr_gv11b_handle_warp_esr_error_mmu_nack(struct gk20a *g,
 	return err;
 }
 
-static bool gr_gv11b_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error)
+bool gv11b_gr_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error)
 {
 	u32 index = 0U;
 	bool esr_err = false;
@@ -559,7 +559,7 @@ static int gr_gv11b_handle_all_warp_esr_errors(struct gk20a *g,
 	/*
 	 * Check for an esr error
 	 */
-	is_esr_error = gr_gv11b_check_warp_esr_error(g, warp_esr_error);
+	is_esr_error = g->ops.gr.check_warp_esr_error(g, warp_esr_error);
 	if (!is_esr_error) {
 		nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
 			"No ESR error, Skip RC recovery and Trigger CILP");
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h
index 9682209b8..eaafee4e7 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h
@@ -49,6 +49,7 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
 int gv11b_gr_clear_sm_error_state(struct gk20a *g,
 		struct nvgpu_channel *ch, u32 sm_id);
 bool gv11b_gr_sm_debugger_attached(struct gk20a *g);
+bool gv11b_gr_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error);
 void gv11b_gr_suspend_single_sm(struct gk20a *g,
 		u32 gpc, u32 tpc, u32 sm,
 		u32 global_esr_mask, bool check_errors);
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 904f7f403..7746899dc 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -370,6 +370,7 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
+		.check_warp_esr_error = gv11b_gr_check_warp_esr_error,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 		.ecc = {
 			.detect = gv11b_ecc_detect_enabled_units,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 4bb8c165d..f0f30b988 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -405,6 +405,7 @@ static const struct gpu_ops tu104_ops = {
 		.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
+		.check_warp_esr_error = gv11b_gr_check_warp_esr_error,
 #endif /* CONFIG_NVGPU_DEBUGGER */
 		.ecc = {
 			.detect = NULL,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
index 39787b39c..77da395a5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
@@ -1189,6 +1189,7 @@ struct gops_gr {
 				  struct nvgpu_channel *ch, bool enable);
 	bool (*esr_bpt_pending_events)(u32 global_esr,
 				       enum nvgpu_event_id_type bpt_event);
+	bool (*check_warp_esr_error)(struct gk20a *g, u32 warp_esr_error);
 #ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
 	int (*set_boosted_ctx)(struct nvgpu_channel *ch, bool boost);
 #endif