diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c index a6e77e001..f677adb03 100644 --- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c +++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c @@ -20,8 +20,8 @@ * DEALINGS IN THE SOFTWARE. */ #include -#include -#include +#include +#include /* * Assures that unused bits (size .. (maskDataCount * 32 - 1)) are always zero. @@ -29,31 +29,7 @@ #define BOARDOBJGRPMASK_NORMALIZE(_pmask) \ ((_pmask)->data[(_pmask)->maskdatacount-1U] &= (_pmask)->lastmaskfilter) -int boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize, - struct ctrl_boardobjgrp_mask *extmask) -{ - if (mask == NULL) { - return -EINVAL; - } - if ((bitsize != CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) && - (bitsize != CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)) { - return -EINVAL; - } - - mask->bitcount = bitsize; - mask->maskdatacount = CTRL_BOARDOBJGRP_MASK_DATA_SIZE(bitsize); - mask->lastmaskfilter = U32(bitsize) % - CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE; - - mask->lastmaskfilter = (mask->lastmaskfilter == 0U) ? - 0xFFFFFFFFU : (BIT32(mask->lastmaskfilter) - 1U); - - return (extmask == NULL) ? - boardobjgrpmask_clr(mask) : - boardobjgrpmask_import(mask, bitsize, extmask); -} - -int boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize, +static int import_mask_data(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask) { u8 index; @@ -77,7 +53,64 @@ int boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize, return 0; } -int boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, + +static int clr_mask_data(struct boardobjgrpmask *mask) +{ + u8 index; + + if (mask == NULL) { + return -EINVAL; + } + for (index = 0; index < mask->maskdatacount; index++) { + mask->data[index] = 0; + } + + return 0; +} + +int nvgpu_boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize, + struct ctrl_boardobjgrp_mask *extmask) +{ + if (mask == NULL) { + return -EINVAL; + } + if ((bitsize != CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) && + (bitsize != CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)) { + return -EINVAL; + } + + mask->bitcount = bitsize; + mask->maskdatacount = CTRL_BOARDOBJGRP_MASK_DATA_SIZE(bitsize); + mask->lastmaskfilter = U32(bitsize) % + CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE; + + mask->lastmaskfilter = (mask->lastmaskfilter == 0U) ? + 0xFFFFFFFFU : (BIT32(mask->lastmaskfilter) - 1U); + + return (extmask == NULL) ? + clr_mask_data(mask) : + import_mask_data(mask, bitsize, extmask); +} + +bool nvgpu_boardobjgrpmask_bit_get(struct boardobjgrpmask *mask, u8 bitidx) +{ + u8 index; + u8 offset; + + if (mask == NULL) { + return false; + } + if (bitidx >= mask->bitcount) { + return false; + } + + index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx); + offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx); + + return (mask->data[index] & BIT32(offset)) != 0U; +} + +int nvgpu_boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask) { u8 index; @@ -99,64 +132,7 @@ int boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, return 0; } -int boardobjgrpmask_clr(struct boardobjgrpmask *mask) -{ - u8 index; - - if (mask == NULL) { - return -EINVAL; - } - for (index = 0; index < mask->maskdatacount; index++) { - mask->data[index] = 0; - } - - return 0; -} - -int boardobjgrpmask_set(struct boardobjgrpmask *mask) -{ - u8 index; - - if (mask == NULL) { - return -EINVAL; - } - for (index = 0; index < mask->maskdatacount; index++) { - mask->data[index] = 0xFFFFFFFFU; - } - BOARDOBJGRPMASK_NORMALIZE(mask); - return 0; -} - -int boardobjgrpmask_inv(struct boardobjgrpmask *mask) -{ - u8 index; - - if (mask == NULL) { - return -EINVAL; - } - for (index = 0; index < mask->maskdatacount; index++) { - mask->data[index] = ~mask->data[index]; - } - BOARDOBJGRPMASK_NORMALIZE(mask); - return 0; -} - -bool boardobjgrpmask_iszero(struct boardobjgrpmask *mask) -{ - u8 index; - - if (mask == NULL) { - return true; - } - for (index = 0; index < mask->maskdatacount; index++) { - if (mask->data[index] != 0U) { - return false; - } - } - return true; -} - -u8 boardobjgrpmask_bitsetcount(struct boardobjgrpmask *mask) +u8 nvgpu_boardobjgrpmask_bit_set_count(struct boardobjgrpmask *mask) { u8 index; u8 result = 0; @@ -175,30 +151,7 @@ u8 boardobjgrpmask_bitsetcount(struct boardobjgrpmask *mask) return result; } -u8 boardobjgrpmask_bitidxlowest(struct boardobjgrpmask *mask) -{ - u8 index; - u8 result = CTRL_BOARDOBJ_IDX_INVALID; - - if (mask == NULL) { - return result; - } - - for (index = 0; index < mask->maskdatacount; index++) { - u32 m = mask->data[index]; - - if (m != 0U) { - LOWESTBITIDX_32(m); - result = (u8)m + index * - CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE; - break; - } - } - - return result; -} - -u8 boardobjgrpmask_bitidxhighest(struct boardobjgrpmask *mask) +u8 nvgpu_boardobjgrpmask_bit_idx_highest(struct boardobjgrpmask *mask) { u8 index; u8 result = CTRL_BOARDOBJ_IDX_INVALID; @@ -221,7 +174,7 @@ u8 boardobjgrpmask_bitidxhighest(struct boardobjgrpmask *mask) return result; } -int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx) +int nvgpu_boardobjgrpmask_bit_clr(struct boardobjgrpmask *mask, u8 bitidx) { u8 index; u8 offset; @@ -241,7 +194,7 @@ int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx) return 0; } -int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx) +int nvgpu_boardobjgrpmask_bit_set(struct boardobjgrpmask *mask, u8 bitidx) { u8 index; u8 offset; @@ -261,121 +214,7 @@ int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx) return 0; } -int boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx) -{ - u8 index; - u8 offset; - - if (mask == NULL) { - return -EINVAL; - } - if (bitidx >= mask->bitcount) { - return -EINVAL; - } - - index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx); - offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx); - - mask->data[index] ^= ~BIT32(offset); - - return 0; -} - -bool boardobjgrpmask_bitget(struct boardobjgrpmask *mask, u8 bitidx) -{ - u8 index; - u8 offset; - - if (mask == NULL) { - return false; - } - if (bitidx >= mask->bitcount) { - return false; - } - - index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx); - offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx); - - return (mask->data[index] & BIT(offset)) != 0U; -} - -int boardobjgrpmask_and(struct boardobjgrpmask *dst, - struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2) -{ - u8 index; - - if (!boardobjgrpmask_sizeeq(dst, op1)) { - return -EINVAL; - } - if (!boardobjgrpmask_sizeeq(dst, op2)) { - return -EINVAL; - } - - for (index = 0; index < dst->maskdatacount; index++) { - dst->data[index] = op1->data[index] & op2->data[index]; - } - - return 0; -} - -int boardobjgrpmask_or(struct boardobjgrpmask *dst, - struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2) -{ - u8 index; - - if (!boardobjgrpmask_sizeeq(dst, op1)) { - return -EINVAL; - } - if (!boardobjgrpmask_sizeeq(dst, op2)) { - return -EINVAL; - } - - for (index = 0; index < dst->maskdatacount; index++) { - dst->data[index] = op1->data[index] | op2->data[index]; - } - - return 0; -} - -int boardobjgrpmask_xor(struct boardobjgrpmask *dst, - struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2) -{ - u8 index; - - if (!boardobjgrpmask_sizeeq(dst, op1)) { - return -EINVAL; - } - if (!boardobjgrpmask_sizeeq(dst, op2)) { - return -EINVAL; - } - - for (index = 0; index < dst->maskdatacount; index++) { - dst->data[index] = op1->data[index] ^ op2->data[index]; - } - - return 0; -} - -int boardobjgrpmask_copy(struct boardobjgrpmask *dst, - struct boardobjgrpmask *src) -{ - u8 index; - - if (!boardobjgrpmask_sizeeq(dst, src)) { - return -EINVAL; - } - - for (index = 0; index < dst->maskdatacount; index++) { - dst->data[index] = src->data[index]; - } - - return 0; -} - -bool boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1, +bool nvgpu_boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1, struct boardobjgrpmask *op2) { if (op1 == NULL) { @@ -388,23 +227,3 @@ bool boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1, return op1->bitcount == op2->bitcount; } -bool boardobjgrpmask_issubset(struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2) -{ - u8 index; - - if (!boardobjgrpmask_sizeeq(op2, op1)) { - return false; - } - - for (index = 0; index < op1->maskdatacount; index++) { - u32 op_1 = op1->data[index]; - u32 op_2 = op2->data[index]; - - if ((op_1 & op_2) != op_1) { - return false; - } - } - - return true; -} diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c index 2c83cd49f..35607ce5a 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c @@ -180,12 +180,12 @@ static int _clk_domains_pmudatainit_3x(struct gk20a *g, } else { pset->volt_rails_max = 1; } - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &pdomains->master_domains_mask.super, pdomains->master_domains_mask.super.bitcount, &pset->master_domains_mask.super); - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &pdomains->prog_domains_mask.super, pdomains->prog_domains_mask.super.bitcount, &pset->prog_domains_mask.super); @@ -230,8 +230,9 @@ int nvgpu_clk_domain_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e32(g, - &g->pmu.clk_pmu->clk_domainobjs->super); + + status = nvgpu_boardobjgrp_construct_e32(g, + &g->pmu.clk_pmu->clk_domainobjs->super); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk domain, status - 0x%x", @@ -282,7 +283,7 @@ int nvgpu_clk_domain_sw_setup(struct gk20a *g) if (pdomain->super.implements(g, &pdomain->super, CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG)) { - status = boardobjgrpmask_bitset( + status = nvgpu_boardobjgrpmask_bit_set( &pclkdomainobjs->prog_domains_mask.super, i); if (status != 0) { goto done; @@ -291,14 +292,15 @@ int nvgpu_clk_domain_sw_setup(struct gk20a *g) if (pdomain->super.implements(g, &pdomain->super, CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER)) { - status = boardobjgrpmask_bitset( + status = nvgpu_boardobjgrpmask_bit_set( &pclkdomainobjs->master_domains_mask.super, i); if (status != 0) { goto done; } pdomain_master_35 = (struct clk_domain_35_master *)pdomain; - status = boardobjgrpmask_bitset(&pdomain_master_35-> + status = nvgpu_boardobjgrpmask_bit_set( + &pdomain_master_35-> master_slave_domains_grp_mask.super, i); if (status != 0) { goto done; @@ -316,10 +318,10 @@ int nvgpu_clk_domain_sw_setup(struct gk20a *g) pdomain_slave_35->slave.master_idx)); pdomain_master_35->master.slave_idxs_mask |= BIT32(i); pdomain_slave_35->super.clk_pos = - boardobjgrpmask_bitsetcount( + nvgpu_boardobjgrpmask_bit_set_count( &pdomain_master_35-> master_slave_domains_grp_mask.super); - status = boardobjgrpmask_bitset( + status = nvgpu_boardobjgrpmask_bit_set( &pdomain_master_35-> master_slave_domains_grp_mask.super, i); if (status != 0) { @@ -602,7 +604,7 @@ static int clk_domain_construct_super(struct gk20a *g, struct nvgpu_clk_domain *ptmpdomain = (struct nvgpu_clk_domain *)pargs; int status = 0; - status = boardobj_construct_super(g, ppboardobj, + status = nvgpu_boardobj_construct_super(g, ppboardobj, (u16)size, pargs); if (status != 0) { @@ -1115,7 +1117,7 @@ static int clk_domain_pmudatainit_35_master(struct gk20a *g, pset->master.slave_idxs_mask = pclk_domain_35_master->master.slave_idxs_mask; - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &pclk_domain_35_master->master_slave_domains_grp_mask.super, pclk_domain_35_master-> master_slave_domains_grp_mask.super.bitcount, @@ -1270,7 +1272,7 @@ static int clk_domain_pmudatainit_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c index e7636db7d..c6984054a 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c @@ -84,7 +84,7 @@ static int _clk_fll_devgrp_pmudatainit_super(struct gk20a *g, pset->lut_min_voltage_uv = pfll_objs->lut_min_voltage_uv; pset->max_min_freq_mhz = pfll_objs->max_min_freq_mhz; - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &pfll_objs->lut_prog_master_mask.super, pfll_objs->lut_prog_master_mask.super.bitcount, &pset->lut_prog_master_mask.super); @@ -148,7 +148,7 @@ int nvgpu_clk_fll_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmu.clk_pmu->avfs_fllobjs->super); if (status != 0) { nvgpu_err(g, @@ -209,7 +209,7 @@ int nvgpu_clk_fll_sw_setup(struct gk20a *g) } if (pfll_master == NULL) { - status = boardobjgrpmask_bitset( + status = nvgpu_boardobjgrpmask_bit_set( &pfllobjs->lut_prog_master_mask.super, BOARDOBJ_GET_IDX(pfll)); if (status != 0) { @@ -428,7 +428,7 @@ static int lutbroadcastslaveregister(struct gk20a *g, return -EINVAL; } - return boardobjgrpmask_bitset(&pfll-> + return nvgpu_boardobjgrpmask_bit_set(&pfll-> lut_prog_broadcast_slave_mask.super, BOARDOBJ_GET_IDX(pfll_slave)); } @@ -442,7 +442,7 @@ static struct fll_device *construct_fll_device(struct gk20a *g, int status; nvgpu_log_info(g, " "); - status = boardobj_construct_super(g, &board_obj_ptr, + status = nvgpu_boardobj_construct_super(g, &board_obj_ptr, sizeof(struct fll_device), pargs); if (status != 0) { return NULL; @@ -490,7 +490,7 @@ static int fll_device_init_pmudata_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } @@ -519,7 +519,7 @@ static int fll_device_init_pmudata_super(struct gk20a *g, (u8 *)&pfll_dev->regime_desc, sizeof(struct nv_pmu_clk_regime_desc)); - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &pfll_dev->lut_prog_broadcast_slave_mask.super, pfll_dev->lut_prog_broadcast_slave_mask.super.bitcount, &perf_pmu_data->lut_prog_broadcast_slave_mask.super); diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c index 42e306837..dd1caf01e 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c @@ -70,7 +70,7 @@ static int clk_freq_controller_pmudatainit_super(struct gk20a *g, struct clk_freq_controller *pfreq_cntlr; int status = 0; - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } @@ -132,7 +132,7 @@ static int clk_freq_controller_construct_super(struct gk20a *g, struct clk_freq_controller *pfreq_cntlr_tmp = NULL; int status = 0; - status = boardobj_construct_super(g, ppboardobj, size, pargs); + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; } @@ -434,8 +434,10 @@ int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); + pclk_freq_controllers = g->pmu.clk_pmu->clk_freq_controllers; - status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super); + status = nvgpu_boardobjgrp_construct_e32(g, + &pclk_freq_controllers->super); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk FCT, status - 0x%x", @@ -483,7 +485,7 @@ int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g) break; } } - boardobjgrpmask_bitset(&pclk_freq_controllers-> + nvgpu_boardobjgrpmask_bit_set(&pclk_freq_controllers-> freq_ctrl_load_mask.super, i); } done: @@ -521,7 +523,7 @@ int nvgpu_clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx) status = boardobjgrpmask_e32_init(&isolate_cfc_mask, NULL); if (bit_idx == CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL) { - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &pclk_freq_controllers-> freq_ctrl_load_mask.super, pclk_freq_controllers-> @@ -530,18 +532,18 @@ int nvgpu_clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx) } else { - status = boardobjgrpmask_bitset(&isolate_cfc_mask.super, + status = nvgpu_boardobjgrpmask_bit_set(&isolate_cfc_mask.super, bit_idx); - status = boardobjgrpmask_export(&isolate_cfc_mask.super, + status = nvgpu_boardobjgrpmask_export(&isolate_cfc_mask.super, isolate_cfc_mask.super.bitcount, &load_mask->super); if (bload) { - status = boardobjgrpmask_bitset( + status = nvgpu_boardobjgrpmask_bit_set( &pclk_freq_controllers-> freq_ctrl_load_mask.super, bit_idx); } else { - status = boardobjgrpmask_bitclr( + status = nvgpu_boardobjgrpmask_bit_clr( &pclk_freq_controllers-> freq_ctrl_load_mask.super, bit_idx); diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c index 74aeba888..23584e714 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c @@ -73,8 +73,8 @@ static int clk_freq_domain_grp_pmudatainit(struct gk20a *g, status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); if (status != 0) { nvgpu_err(g, - "error updating pmu boardobjgrp for clk freq domain 0x%x", - status); + "error updating pmu boardobjgrp for " + "clk freq domain 0x%x", status); goto exit; } @@ -119,7 +119,7 @@ static int clk_freq_domain_pmudatainit(struct gk20a *g, nvgpu_log_fn(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if(status != 0) { nvgpu_err(g, "Failed pmudatainit freq_domain"); goto exit; @@ -157,12 +157,12 @@ int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g) pboardobjgrp = &g->pmu.clk_pmu->freq_domain_grp_objs->super.super; pfreq_domain_grp = g->pmu.clk_pmu->freq_domain_grp_objs; - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmu.clk_pmu->freq_domain_grp_objs->super); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for clk freq domain, status - 0x%x", - status); + "error creating boardobjgrp for clk freq domain, " + "status - 0x%x", status); goto exit; } @@ -180,8 +180,8 @@ int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g) clk, CLK, clk_freq_domain, CLK_FREQ_DOMAIN); if (status != 0) { nvgpu_err(g, - "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", - status); + "error constructing PMU_BOARDOBJ_CMD_GRP_SET " + "interface - 0x%x", status); goto exit; } @@ -193,23 +193,26 @@ int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g) clk_freq_domain_type[idx].clk_domain; pboardobj = NULL; - status = boardobj_construct_super(g,&pboardobj, + status = nvgpu_boardobj_construct_super(g,&pboardobj, sizeof(struct nvgpu_clk_freq_domain), (void*)&freq_domain_data); if(status != 0) { - nvgpu_err(g, "Failed to construct nvgpu_clk_freq_domain Board obj"); + nvgpu_err(g, "Failed to construct " + "nvgpu_clk_freq_domain Board obj"); goto exit; } pfreq_domain = (struct nvgpu_clk_freq_domain*)(void*) pboardobj; pfreq_domain->super.pmudatainit = clk_freq_domain_pmudatainit; - pfreq_domain->clk_domain = freq_domain_data.freq_domain.clk_domain; + pfreq_domain->clk_domain = + freq_domain_data.freq_domain.clk_domain; status = boardobjgrp_objinsert(&pfreq_domain_grp->super.super, &pfreq_domain->super, idx); if (status != 0) { nvgpu_err(g, - "unable to insert clock freq domain boardobj for %d", idx); + "unable to insert clock freq domain " + "boardobj for %d", idx); goto exit; } } diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c index 302b42b94..88da7855d 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c @@ -115,11 +115,11 @@ int nvgpu_clk_prog_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e255(g, + status = nvgpu_boardobjgrp_construct_e255(g, &g->pmu.clk_pmu->clk_progobjs->super); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for clk prog, status - 0x%x", + "error creating boardobjgrp for clk prog, status- 0x%x", status); goto done; } @@ -480,7 +480,7 @@ static int clk_prog_pmudatainit_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); return status; } @@ -668,7 +668,7 @@ static int clk_prog_construct_super(struct gk20a *g, struct clk_prog *pclkprog; int status = 0; - status = boardobj_construct_super(g, ppboardobj, + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c index 4d7c3cfd2..6b80359a6 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c @@ -130,8 +130,8 @@ int nvgpu_clk_vf_point_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e255(g, - &g->pmu.clk_pmu->clk_vf_pointobjs->super); + status = nvgpu_boardobjgrp_construct_e255(g, + &g->pmu.clk_pmu->clk_vf_pointobjs->super); if (status != 0) { nvgpu_err(g, "error creating boardobjgrp for clk vfpoint, status - 0x%x", @@ -199,7 +199,7 @@ static int clk_vf_point_construct_super(struct gk20a *g, (struct clk_vf_point *)pargs; int status = 0; - status = boardobj_construct_super(g, ppboardobj, + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; @@ -448,7 +448,7 @@ static int _clk_vf_point_pmudatainit_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c index dc5904c2b..924a6156b 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c @@ -185,7 +185,7 @@ int nvgpu_clk_vin_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmu.clk_pmu->avfs_vinobjs->super); if (status != 0) { nvgpu_err(g, @@ -383,7 +383,7 @@ static int vin_device_construct_super(struct gk20a *g, struct nvgpu_vin_device *ptmpvin_device = (struct nvgpu_vin_device *)pargs; int status = 0; - status = boardobj_construct_super(g, ppboardobj, size, pargs); + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; @@ -463,7 +463,7 @@ static int vin_device_init_pmudata_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } diff --git a/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c b/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c index 6177a93d2..8aa1ffa4a 100644 --- a/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c +++ b/drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c @@ -1303,14 +1303,6 @@ int nvgpu_pmu_init_fw_ver_ops(struct gk20a *g, pmu_get_init_msg_sw_mngd_area_off_v5; fw_ops->get_init_msg_sw_mngd_area_size = pmu_get_init_msg_sw_mngd_area_size_v5; - fw_ops->boardobj.boardobjgrp_pmucmd_construct_impl = - boardobjgrp_pmucmd_construct_impl_v1; - fw_ops->boardobj.boardobjgrp_pmuset_impl = - boardobjgrp_pmuset_impl_v1; - fw_ops->boardobj.boardobjgrp_pmugetstatus_impl = - boardobjgrp_pmugetstatus_impl_v1; - fw_ops->boardobj.is_boardobjgrp_pmucmd_id_valid = - is_boardobjgrp_pmucmd_id_valid_v1; if (app_version == APP_VERSION_GV10X) { fw_ops->clk.clk_set_boot_clk = NULL; } else { diff --git a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c index 5ccad5bad..41ede9929 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c @@ -53,7 +53,7 @@ static int perf_change_seq_sw_setup_super(struct gk20a *g, p_change_seq->version = CTRL_PERF_CHANGE_SEQ_VERSION_35; - status = boardobjgrpmask_init( + status = nvgpu_boardobjgrpmask_init( &p_change_seq->clk_domains_exclusion_mask.super, 32U, ((void*)0)); if (status != 0) { @@ -62,7 +62,7 @@ static int perf_change_seq_sw_setup_super(struct gk20a *g, goto perf_change_seq_sw_setup_super_exit; } - status = boardobjgrpmask_init( + status = nvgpu_boardobjgrpmask_init( &p_change_seq->clk_domains_inclusion_mask.super, 32U, ((void*)0)); if (status != 0) { @@ -196,18 +196,20 @@ int nvgpu_perf_change_seq_pmu_setup(struct gk20a *g) info_set.info_set.super.version = perf_change_seq_pmu->super.version; - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &perf_change_seq_pmu->super.clk_domains_exclusion_mask.super, - perf_change_seq_pmu->super.clk_domains_exclusion_mask.super.bitcount, + perf_change_seq_pmu-> + super.clk_domains_exclusion_mask.super.bitcount, &info_set.info_set.super.clk_domains_exclusion_mask.super); if ( status != 0 ) { nvgpu_err(g, "Could not export clkdomains exclusion mask"); goto perf_change_seq_pmu_setup_exit; } - status = boardobjgrpmask_export( + status = nvgpu_boardobjgrpmask_export( &perf_change_seq_pmu->super.clk_domains_inclusion_mask.super, - perf_change_seq_pmu->super.clk_domains_inclusion_mask.super.bitcount, + perf_change_seq_pmu-> + super.clk_domains_inclusion_mask.super.bitcount, &info_set.info_set.super.clk_domains_inclusion_mask.super); if ( status != 0 ) { nvgpu_err(g, "Could not export clkdomains inclusion mask"); diff --git a/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c index 6d0e04403..f4b65cba6 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c @@ -43,7 +43,7 @@ static int pstate_construct_super(struct gk20a *g, struct boardobj **ppboardobj, struct pstate *pstate; int err; - err = boardobj_construct_super(g, ppboardobj, size, args); + err = nvgpu_boardobj_construct_super(g, ppboardobj, size, args); if (err != 0) { return err; } @@ -215,7 +215,7 @@ int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g) return err; } - err = boardobjgrpconstruct_e32(g, &g->perf_pmu->pstatesobjs.super); + err = nvgpu_boardobjgrp_construct_e32(g, &g->perf_pmu->pstatesobjs.super); if (err != 0) { nvgpu_err(g, "error creating boardobjgrp for pstates, err=%d", diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c index 3584ebc55..19c8e4a6a 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c @@ -46,7 +46,7 @@ static int vfe_equs_pmudatainit(struct gk20a *g, { int status = 0; - status = boardobjgrp_pmudatainit_e255(g, pboardobjgrp, pboardobjgrppmu); + status = boardobjgrp_pmu_data_init_e255(g, pboardobjgrp, pboardobjgrppmu); if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for vfe equ 0x%x", status); @@ -86,11 +86,12 @@ int nvgpu_vfe_equ_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e255(g, &g->perf_pmu->vfe_equobjs.super); + status = nvgpu_boardobjgrp_construct_e255(g, + &g->perf_pmu->vfe_equobjs.super); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for clk domain, status - 0x%x", - status); + "error creating boardobjgrp for clk domain, " + "status - 0x%x", status); goto done; } @@ -419,7 +420,7 @@ static int vfe_equ_pmudatainit_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } @@ -446,7 +447,7 @@ static int vfe_equ_construct_super(struct gk20a *g, struct vfe_equ *ptmpequ = (struct vfe_equ *)pargs; int status = 0; - status = boardobj_construct_super(g, ppboardobj, + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c index 5b864cf40..d38ec0e4a 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c @@ -190,11 +190,12 @@ int nvgpu_vfe_var_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e32(g, &g->perf_pmu->vfe_varobjs.super); + status = nvgpu_boardobjgrp_construct_e32(g, + &g->perf_pmu->vfe_varobjs.super); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for clk domain, status - 0x%x", - status); + "error creating boardobjgrp for clk domain, " + "status - 0x%x", status); goto done; } @@ -392,7 +393,7 @@ static int vfe_var_pmudatainit_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } @@ -402,12 +403,14 @@ static int vfe_var_pmudatainit_super(struct gk20a *g, pset->out_range_min = pvfe_var->out_range_min; pset->out_range_max = pvfe_var->out_range_max; - status = boardobjgrpmask_export(&pvfe_var->mask_dependent_vars.super, - pvfe_var->mask_dependent_vars.super.bitcount, - &pset->mask_dependent_vars.super); - status = boardobjgrpmask_export(&pvfe_var->mask_dependent_equs.super, - pvfe_var->mask_dependent_equs.super.bitcount, - &pset->mask_dependent_equs.super); + status = nvgpu_boardobjgrpmask_export(&pvfe_var-> + mask_dependent_vars.super, + pvfe_var->mask_dependent_vars.super.bitcount, + &pset->mask_dependent_vars.super); + status = nvgpu_boardobjgrpmask_export(&pvfe_var-> + mask_dependent_equs.super, + pvfe_var->mask_dependent_equs.super.bitcount, + &pset->mask_dependent_equs.super); return status; } @@ -421,7 +424,7 @@ static int vfe_var_construct_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_construct_super(g, ppboardobj, size, pargs); + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c index 5acd93fa3..6eb6a4b36 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c @@ -200,10 +200,11 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g) ppwr_desc_header->ba_info.b_initialized_and_used = false; /* populate the table */ - boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)&ppwr_desc_header->super, + nvgpu_boardobjgrp_e32_hdr_set((struct nv_pmu_boardobjgrp *) + &ppwr_desc_header->super, g->pmgr_pmu->pmgr_deviceobjs.super.super.objmask); - status = boardobjgrp_pmudatainit_legacy(g, + status = nvgpu_boardobjgrp_pmu_data_init_legacy(g, &g->pmgr_pmu->pmgr_deviceobjs.super.super, (struct nv_pmu_boardobjgrp_super *)pwr_desc_table); @@ -249,13 +250,16 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) pwr_channel_hdr = &(pwr_monitor_pack->channels.hdr.data); *pwr_monitor_pack = g->pmgr_pmu->pmgr_monitorobjs.pmu_data; - boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)&pwr_channel_hdr->super, - g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super.objmask); + nvgpu_boardobjgrp_e32_hdr_set( + (struct nv_pmu_boardobjgrp *)&pwr_channel_hdr->super, + g->pmgr_pmu->pmgr_monitorobjs. + pwr_channels.super.objmask); /* Copy in each channel */ - status = boardobjgrp_pmudatainit_legacy(g, - &g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super, - (struct nv_pmu_boardobjgrp_super *)&(pwr_monitor_pack->channels)); + status = nvgpu_boardobjgrp_pmu_data_init_legacy(g,&g->pmgr_pmu-> + pmgr_monitorobjs.pwr_channels.super, + (struct nv_pmu_boardobjgrp_super *)& + (pwr_monitor_pack->channels)); if (status != 0) { nvgpu_err(g, "boardobjgrp_pmudatainit_legacy failed %x", @@ -266,16 +270,19 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) /* Copy in each channel relationship */ pwr_chrelationship_header = &(pwr_monitor_pack->ch_rels.hdr.data); - boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)&pwr_chrelationship_header->super, - g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels.super.objmask); + nvgpu_boardobjgrp_e32_hdr_set((struct nv_pmu_boardobjgrp *) + &pwr_chrelationship_header->super, + g->pmgr_pmu->pmgr_monitorobjs. + pwr_ch_rels.super.objmask); pwr_channel_hdr->physical_channel_mask = g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask; pwr_channel_hdr->type = NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING; - status = boardobjgrp_pmudatainit_legacy(g, + status = nvgpu_boardobjgrp_pmu_data_init_legacy(g, &g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels.super, - (struct nv_pmu_boardobjgrp_super *)&(pwr_monitor_pack->ch_rels)); + (struct nv_pmu_boardobjgrp_super *)& + (pwr_monitor_pack->ch_rels)); if (status != 0) { nvgpu_err(g, "boardobjgrp_pmudatainit_legacy failed %x", @@ -323,9 +330,9 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g) ppwrpack->policies.hdr.data.version = g->pmgr_pmu->pmgr_policyobjs.version; ppwrpack->policies.hdr.data.b_enabled = g->pmgr_pmu->pmgr_policyobjs.b_enabled; - boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *) - &ppwrpack->policies.hdr.data.super, - g->pmgr_pmu->pmgr_policyobjs.pwr_policies.super.objmask); + nvgpu_boardobjgrp_e32_hdr_set((struct nv_pmu_boardobjgrp *) + &ppwrpack->policies.hdr.data.super, g->pmgr_pmu-> + pmgr_policyobjs.pwr_policies.super.objmask); (void) memset(&ppwrpack->policies.hdr.data.reserved_pmu_policy_mask, 0, @@ -361,13 +368,15 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g) } BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK_END; - boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *) + nvgpu_boardobjgrp_e32_hdr_set((struct nv_pmu_boardobjgrp *) &ppwrpack->policy_rels.hdr.data.super, - g->pmgr_pmu->pmgr_policyobjs.pwr_policy_rels.super.objmask); + g->pmgr_pmu->pmgr_policyobjs. + pwr_policy_rels.super.objmask); - boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *) + nvgpu_boardobjgrp_e32_hdr_set((struct nv_pmu_boardobjgrp *) &ppwrpack->violations.hdr.data.super, - g->pmgr_pmu->pmgr_policyobjs.pwr_violations.super.objmask); + g->pmgr_pmu->pmgr_policyobjs. + pwr_violations.super.objmask); max_dmem_size = (u32)sizeof(union nv_pmu_pmgr_pwr_policy_dmem_size); diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c index 739ce727d..df44b915c 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c @@ -63,7 +63,7 @@ static int _pwr_domains_pmudatainit_ina3221(struct gk20a *g, int status = 0; u32 indx; - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for pwr domain 0x%x", @@ -100,7 +100,7 @@ static struct boardobj *construct_pwr_device(struct gk20a *g, struct pwr_device_ina3221 *pwrdev; struct pwr_device_ina3221 *ina3221 = (struct pwr_device_ina3221*)pargs; - status = boardobj_construct_super(g, &board_obj_ptr, + status = nvgpu_boardobj_construct_super(g, &board_obj_ptr, pargs_size, pargs); if (status != 0) { return NULL; @@ -296,11 +296,12 @@ int pmgr_device_sw_setup(struct gk20a *g) struct pwr_devices *ppwrdeviceobjs; /* Construct the Super Class and override the Interfaces */ - status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu->pmgr_deviceobjs.super); + status = nvgpu_boardobjgrp_construct_e32(g, + &g->pmgr_pmu->pmgr_deviceobjs.super); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for pmgr devices, status - 0x%x", - status); + "error creating boardobjgrp for pmgr devices, " + "status - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c index d6803f5d0..aa3e66641 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c @@ -117,7 +117,7 @@ static int _pwr_domains_pmudatainit_sensor(struct gk20a *g, struct pwr_channel_sensor *sensor; int status = 0; - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for pwr sensor 0x%x", @@ -152,7 +152,7 @@ static struct boardobj *construct_pwr_topology(struct gk20a *g, struct pwr_channel_sensor *pwrchannel; struct pwr_channel_sensor *sensor = (struct pwr_channel_sensor*)pargs; - status = boardobj_construct_super(g, &board_obj_ptr, + status = nvgpu_boardobj_construct_super(g, &board_obj_ptr, pargs_size, pargs); if (status != 0) { return NULL; @@ -312,12 +312,12 @@ int pmgr_monitor_sw_setup(struct gk20a *g) u8 indx = 0; /* Construct the Super Class and override the Interfaces */ - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmgr_pmu->pmgr_monitorobjs.pwr_channels); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for pmgr channel, status - 0x%x", - status); + "error creating boardobjgrp for pmgr channel, " + "status - 0x%x", status); goto done; } @@ -327,12 +327,12 @@ int pmgr_monitor_sw_setup(struct gk20a *g) pboardobjgrp->pmudatainstget = _pwr_channel_pmudata_instget; /* Construct the Super Class and override the Interfaces */ - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for pmgr channel relationship, status - 0x%x", - status); + "error creating boardobjgrp for pmgr channel " + "relationship, status - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c index 33ebf7c03..7b1f98629 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c @@ -194,7 +194,7 @@ static int _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g, struct nv_pmu_pmgr_pwr_policy *pmu_pwr_policy; int status = 0; - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for pwr sensor 0x%x", @@ -265,7 +265,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g, struct pwr_policy *pwrpolicyparams = (struct pwr_policy*)pargs; struct pwr_policy_hw_threshold *hwthreshold = (struct pwr_policy_hw_threshold*)pargs; - status = boardobj_construct_super(g, &board_obj_ptr, + status = nvgpu_boardobj_construct_super(g, &board_obj_ptr, pargs_size, pargs); if (status != 0) { return NULL; @@ -723,30 +723,30 @@ int pmgr_policy_sw_setup(struct gk20a *g) u8 indx = 0; /* Construct the Super Class and override the Interfaces */ - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmgr_pmu->pmgr_policyobjs.pwr_policies); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for pmgr policy, status - 0x%x", - status); + "error creating boardobjgrp for pmgr policy, " + "status - 0x%x", status); goto done; } - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmgr_pmu->pmgr_policyobjs.pwr_policy_rels); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for pmgr policy rels, status - 0x%x", - status); + "error creating boardobjgrp for pmgr policy rels, " + "status - 0x%x", status); goto done; } - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->pmgr_pmu->pmgr_policyobjs.pwr_violations); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for pmgr violations, status - 0x%x", - status); + "error creating boardobjgrp for pmgr violations, " + "status - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c b/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c index 81a435fe7..3dd6fd28b 100644 --- a/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c +++ b/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c @@ -39,7 +39,7 @@ static int _therm_channel_pmudatainit_device(struct gk20a *g, struct therm_channel_device *ptherm_channel; struct nv_pmu_therm_therm_channel_device_boardobj_set *pset; - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { nvgpu_err(g, "error updating pmu boardobjgrp for therm channel 0x%x", @@ -73,7 +73,7 @@ static struct boardobj *construct_channel_device(struct gk20a *g, u16 scale_shift = BIT16(8); struct therm_channel_device *therm_device = (struct therm_channel_device*)pargs; - status = boardobj_construct_super(g, &board_obj_ptr, + status = nvgpu_boardobj_construct_super(g, &board_obj_ptr, pargs_size, pargs); if (status != 0) { return NULL; @@ -221,12 +221,12 @@ int therm_channel_sw_setup(struct gk20a *g) struct therm_channels *pthermchannelobjs; /* Construct the Super Class and override the Interfaces */ - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->therm_pmu->therm_channelobjs.super); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for therm devices, status - 0x%x", - status); + "error creating boardobjgrp for therm devices, " + "status - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c b/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c index 7597bb30b..8a360f17d 100644 --- a/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c +++ b/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c @@ -59,7 +59,7 @@ static int _therm_device_pmudata_instget(struct gk20a *g, static int construct_therm_device(struct gk20a *g, struct boardobj **ppboardobj, size_t size, void *pargs) { - return boardobj_construct_super(g, ppboardobj, size, pargs); + return nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); } static int construct_therm_device_gpu(struct gk20a *g, @@ -82,7 +82,7 @@ static int therm_device_pmu_data_init_gpu_gpc_tsosc(struct gk20a *g, struct therm_device_gpu_gpc_tsosc *pdev = NULL; struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set *pset; - status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, pboard_obj, ppmudata); if (status != 0) { goto exit; } @@ -127,7 +127,7 @@ static int therm_device_pmu_data_init_hbm2_site(struct gk20a *g, struct therm_device_hbm2_site *pdev = NULL; struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set *pset; - status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, pboard_obj, ppmudata); if (status != 0) { goto exit; } @@ -340,12 +340,12 @@ int therm_device_sw_setup(struct gk20a *g) struct therm_devices *pthermdeviceobjs; /* Construct the Super Class and override the Interfaces */ - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->therm_pmu->therm_deviceobjs.super); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for therm devices, status - 0x%x", - status); + "error creating boardobjgrp for therm devices," + "status - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c index ff2613198..449d07baa 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c @@ -42,7 +42,7 @@ static int volt_device_pmu_data_init_super(struct gk20a *g, struct voltage_device *pdev; struct nv_pmu_volt_volt_device_boardobj_set *pset; - status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, pboard_obj, ppmudata); if (status != 0) { return status; } @@ -88,7 +88,7 @@ static int construct_volt_device(struct gk20a *g, struct voltage_device *pvolt_dev = NULL; int status = 0; - status = boardobj_construct_super(g, ppboardobj, size, pargs); + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs); if (status != 0) { return status; } @@ -546,12 +546,12 @@ int nvgpu_volt_dev_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->perf_pmu->volt.volt_dev_metadata.volt_devices); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for volt rail, status - 0x%x", - status); + "error creating boardobjgrp for volt rail, " + "status - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c index 7cf457ba7..def4f40ae 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c @@ -33,7 +33,7 @@ static int volt_policy_pmu_data_init_super(struct gk20a *g, struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) { - return boardobj_pmudatainit_super(g, pboardobj, ppmudata); + return nvgpu_boardobj_pmu_data_init_super(g, pboardobj, ppmudata); } static int construct_volt_policy(struct gk20a *g, @@ -42,7 +42,7 @@ static int construct_volt_policy(struct gk20a *g, struct voltage_policy *pvolt_policy = NULL; int status = 0; - status = boardobj_construct_super(g, ppboardobj, size, pArgs); + status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pArgs); if (status != 0) { return status; } @@ -497,12 +497,12 @@ int nvgpu_volt_policy_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->perf_pmu->volt.volt_policy_metadata.volt_policies); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for volt rail, status - 0x%x", - status); + "error creating boardobjgrp for volt rail, " + "status - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c index d07c47a09..985839775 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c @@ -75,7 +75,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g, nvgpu_log_info(g, " "); - status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); + status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); if (status != 0) { return status; } @@ -102,7 +102,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g, (int)g->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i]; } - status = boardobjgrpmask_export(&prail->volt_dev_mask.super, + status = nvgpu_boardobjgrpmask_export(&prail->volt_dev_mask.super, prail->volt_dev_mask.super.bitcount, &rail_pmu_data->volt_dev_mask.super); if (status != 0) { @@ -123,7 +123,7 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs) int status; nvgpu_log_info(g, " "); - status = boardobj_construct_super(g, &board_obj_ptr, + status = nvgpu_boardobj_construct_super(g, &board_obj_ptr, sizeof(struct voltage_rail), pargs); if (status != 0) { return NULL; @@ -378,12 +378,12 @@ int nvgpu_volt_rail_sw_setup(struct gk20a *g) nvgpu_log_info(g, " "); - status = boardobjgrpconstruct_e32(g, + status = nvgpu_boardobjgrp_construct_e32(g, &g->perf_pmu->volt.volt_rail_metadata.volt_rails); if (status != 0) { nvgpu_err(g, - "error creating boardobjgrp for volt rail, status - 0x%x", - status); + "error creating boardobjgrp for volt rail, " + "status - 0x%x", status); goto done; } @@ -543,7 +543,7 @@ int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail goto exit; } - status = boardobjgrpmask_bitset(&pvolt_rail->volt_dev_mask.super, + status = nvgpu_boardobjgrpmask_bit_set(&pvolt_rail->volt_dev_mask.super, volt_dev_idx); exit: diff --git a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h index 8cedeac3c..ada18541d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h +++ b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h @@ -23,8 +23,8 @@ #ifndef NVGPU_BOARDOBJGRPMASK_H #define NVGPU_BOARDOBJGRPMASK_H -#include -#include +struct ctrl_boardobjgrp_mask; + /* * Board Object Group Mask super-structure. @@ -66,54 +66,31 @@ struct boardobjgrpmask_e255 { }; /* Init and I/O operations.*/ -int boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize, +int nvgpu_boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask); -int boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize, - struct ctrl_boardobjgrp_mask *extmask); -int boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, +int nvgpu_boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask); /* Operations on all bits of a single mask.*/ -int boardobjgrpmask_clr(struct boardobjgrpmask *mask); -int boardobjgrpmask_set(struct boardobjgrpmask *mask); -int boardobjgrpmask_inv(struct boardobjgrpmask *mask); -bool boardobjgrpmask_iszero(struct boardobjgrpmask *mask); -u8 boardobjgrpmask_bitsetcount(struct boardobjgrpmask *mask); -u8 boardobjgrpmask_bitidxlowest(struct boardobjgrpmask *mask); -u8 boardobjgrpmask_bitidxhighest(struct boardobjgrpmask *mask); +u8 nvgpu_boardobjgrpmask_bit_set_count(struct boardobjgrpmask *mask); +u8 nvgpu_boardobjgrpmask_bit_idx_highest(struct boardobjgrpmask *mask); /* Operations on a single bit of a single mask */ -int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx); -int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx); -int boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx); -bool boardobjgrpmask_bitget(struct boardobjgrpmask *mask, u8 bitidx); - -/* Operations on a multiple masks */ -int boardobjgrpmask_and(struct boardobjgrpmask *dst, - struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2); -int boardobjgrpmask_or(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2); -int boardobjgrpmask_xor(struct boardobjgrpmask *dst, - struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2); +int nvgpu_boardobjgrpmask_bit_clr(struct boardobjgrpmask *mask, u8 bitidx); +int nvgpu_boardobjgrpmask_bit_set(struct boardobjgrpmask *mask, u8 bitidx); +bool nvgpu_boardobjgrpmask_bit_get(struct boardobjgrpmask *mask, u8 bitidx); /* Special interfaces */ -int boardobjgrpmask_copy(struct boardobjgrpmask *dst, - struct boardobjgrpmask *src); -bool boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1, +bool nvgpu_boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1, struct boardobjgrpmask *op2); -bool boardobjgrpmask_issubset(struct boardobjgrpmask *op1, - struct boardobjgrpmask *op2); - /* init boardobjgrpmask_e32 structure */ #define boardobjgrpmask_e32_init(pmaske32, pextmask) \ - boardobjgrpmask_init(&(pmaske32)->super, \ + nvgpu_boardobjgrpmask_init(&(pmaske32)->super, \ CTRL_BOARDOBJGRP_E32_MAX_OBJECTS, (pextmask)) /* init boardobjgrpmask_e255 structure */ #define boardobjgrpmask_e255_init(pmaske255, pextmask) \ - boardobjgrpmask_init(&(pmaske255)->super, \ + nvgpu_boardobjgrpmask_init(&(pmaske255)->super, \ CTRL_BOARDOBJGRP_E255_MAX_OBJECTS, (pextmask)) #endif /* NVGPU_BOARDOBJGRPMASK_H */ diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c b/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c index 01f5db2e9..1bb3048e8 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c +++ b/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c @@ -51,8 +51,10 @@ DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gv100_get_rate_show, NULL, "%llu\n"); static int sys_cfc_read(void *data , u64 *val) { struct gk20a *g = (struct gk20a *)data; - bool bload = boardobjgrpmask_bitget( - &g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super, + + bool bload = nvgpu_boardobjgrpmask_bit_get( + &g->pmu.clk_pmu->clk_freq_controllers-> + freq_ctrl_load_mask.super, CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS); /* val = 1 implies CLFC is loaded or enabled */ @@ -78,8 +80,10 @@ DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n"); static int ltc_cfc_read(void *data , u64 *val) { struct gk20a *g = (struct gk20a *)data; - bool bload = boardobjgrpmask_bitget( - &g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super, + + bool bload = nvgpu_boardobjgrpmask_bit_get( + &g->pmu.clk_pmu->clk_freq_controllers-> + freq_ctrl_load_mask.super, CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC); /* val = 1 implies CLFC is loaded or enabled */ @@ -105,8 +109,10 @@ DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n"); static int xbar_cfc_read(void *data , u64 *val) { struct gk20a *g = (struct gk20a *)data; - bool bload = boardobjgrpmask_bitget( - &g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super, + + bool bload = nvgpu_boardobjgrpmask_bit_get( + &g->pmu.clk_pmu->clk_freq_controllers-> + freq_ctrl_load_mask.super, CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR); /* val = 1 implies CLFC is loaded or enabled */ @@ -133,8 +139,10 @@ DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read, static int gpc_cfc_read(void *data , u64 *val) { struct gk20a *g = (struct gk20a *)data; - bool bload = boardobjgrpmask_bitget( - &g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super, + + bool bload = nvgpu_boardobjgrpmask_bit_get( + &g->pmu.clk_pmu->clk_freq_controllers-> + freq_ctrl_load_mask.super, CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0); /* val = 1 implies CLFC is loaded or enabled */