From bc379d5eed9d4b1023f3dbb5f82147e7c770a6d2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 28 Sep 2018 15:04:15 -0700 Subject: [PATCH] gpu: nvgpu: Split L2 interrupt handling to MC and L2 L2 interrupt is processed by first reading from MC which L2 triggered the interrupt and then calling a function per L2 slice to get the details. Move the outer loop to MC unit, and the inner loop and L2 accesses to LTC unit. JIRA NVGPU-954 Change-Id: I69b7bb82e4574b0519cdcd73b94d7d3e3fa6ef9e Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1851328 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c | 40 +++++++++++------------- drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h | 3 +- drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c | 20 +++--------- drivers/gpu/nvgpu/common/ltc/ltc_gp10b.h | 6 ++-- drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c | 19 +++-------- drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h | 5 ++- drivers/gpu/nvgpu/common/ltc/ltc_tu104.c | 12 ------- drivers/gpu/nvgpu/common/ltc/ltc_tu104.h | 1 - drivers/gpu/nvgpu/common/mc/mc_gm20b.c | 17 +++++++++- drivers/gpu/nvgpu/common/mc/mc_gm20b.h | 1 + drivers/gpu/nvgpu/common/mc/mc_gp10b.c | 17 +++++++++- drivers/gpu/nvgpu/common/mc/mc_gp10b.h | 1 + drivers/gpu/nvgpu/common/mc/mc_tu104.c | 11 +++++++ drivers/gpu/nvgpu/common/mc/mc_tu104.h | 1 + drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 3 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 3 +- 21 files changed, 90 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c index f4d176cb0..07dfeddf2 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c @@ -32,7 +32,6 @@ #include #include -#include #include #include #include @@ -238,30 +237,29 @@ void gm20b_ltc_init_fs_state(struct gk20a *g) gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg); } -void gm20b_ltc_isr(struct gk20a *g) +void gm20b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice) { - u32 mc_intr, ltc_intr; - unsigned int ltc, slice; + u32 ltc_intr; u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); - mc_intr = gk20a_readl(g, mc_intr_ltc_r()); - nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); - for (ltc = 0; ltc < g->ltc_count; ltc++) { - if ((mc_intr & 1U << ltc) == 0) { - continue; - } - for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { - ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + - ltc_stride * ltc + - lts_stride * slice); - nvgpu_err(g, "ltc%d, slice %d: %08x", - ltc, slice, ltc_intr); - gk20a_writel(g, ltc_ltc0_lts0_intr_r() + - ltc_stride * ltc + - lts_stride * slice, - ltc_intr); - } + ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + + ltc_stride * ltc + + lts_stride * slice); + nvgpu_err(g, "ltc%d, slice %d: %08x", + ltc, slice, ltc_intr); + gk20a_writel(g, ltc_ltc0_lts0_intr_r() + + ltc_stride * ltc + + lts_stride * slice, + ltc_intr); +} + +void gm20b_ltc_isr(struct gk20a *g, unsigned int ltc) +{ + unsigned int slice; + + for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { + gm20b_ltc_lts_isr(g, ltc, slice); } } diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h index cc92c70ac..bdc396274 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h @@ -46,7 +46,8 @@ void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled); void gm20b_ltc_init_fs_state(struct gk20a *g); int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, u32 min, u32 max); -void gm20b_ltc_isr(struct gk20a *g); +void gm20b_ltc_isr(struct gk20a *g, unsigned int ltc); +void gm20b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice); u32 gm20b_ltc_cbc_fix_config(struct gk20a *g, int base); void gm20b_flush_ltc(struct gk20a *g); int gm20b_ltc_alloc_phys_cbc(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c index 73c258f1d..6508679dc 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c @@ -31,7 +31,6 @@ #include #include -#include #include #include "ltc_gm20b.h" @@ -232,8 +231,7 @@ out: return err; } -void gp10b_ltc_lts_isr(struct gk20a *g, - unsigned int ltc, unsigned int slice) +void gp10b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice) { u32 offset; u32 ltc_intr; @@ -289,20 +287,12 @@ void gp10b_ltc_lts_isr(struct gk20a *g, ltc_intr); } -void gp10b_ltc_isr(struct gk20a *g) +void gp10b_ltc_isr(struct gk20a *g, unsigned int ltc) { - u32 mc_intr; - unsigned int ltc, slice; + unsigned int slice; - mc_intr = gk20a_readl(g, mc_intr_ltc_r()); - nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); - for (ltc = 0; ltc < g->ltc_count; ltc++) { - if ((mc_intr & 1U << ltc) == 0) { - continue; - } - for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { - gp10b_ltc_lts_isr(g, ltc, slice); - } + for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { + gp10b_ltc_lts_isr(g, ltc, slice); } } diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.h b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.h index 2be3f33ee..10b2713e1 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.h +++ b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.h @@ -25,14 +25,12 @@ struct gk20a; struct gpu_ops; -void gp10b_ltc_isr(struct gk20a *g); - int gp10b_determine_L2_size_bytes(struct gk20a *g); int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); void gp10b_ltc_init_fs_state(struct gk20a *g); int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, u32 min, u32 max); void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled); -void gp10b_ltc_lts_isr(struct gk20a *g, - unsigned int ltc, unsigned int slice); +void gp10b_ltc_isr(struct gk20a *g, unsigned int ltc); +void gp10b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice); #endif diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c index d20c963ad..0a5c9e21d 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c @@ -106,8 +106,7 @@ void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable) gk20a_writel(g, ltc_ltcs_ltss_intr_r(), val); } -void gv11b_ltc_lts_isr(struct gk20a *g, - unsigned int ltc, unsigned int slice) +void gv11b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice) { u32 offset; u32 ltc_intr3; @@ -204,19 +203,11 @@ void gv11b_ltc_lts_isr(struct gk20a *g, gp10b_ltc_lts_isr(g, ltc, slice); } -void gv11b_ltc_isr(struct gk20a *g) +void gv11b_ltc_isr(struct gk20a *g, unsigned int ltc) { - u32 mc_intr; - unsigned int ltc, slice; + unsigned int slice; - mc_intr = gk20a_readl(g, mc_intr_ltc_r()); - for (ltc = 0; ltc < g->ltc_count; ltc++) { - if ((mc_intr & 1U << ltc) == 0) { - continue; - } - - for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { - gv11b_ltc_lts_isr(g, ltc, slice); - } + for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { + gv11b_ltc_lts_isr(g, ltc, slice); } } diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h index bad686617..3ce5ee6b8 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h +++ b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h @@ -29,8 +29,7 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 index); void gv11b_ltc_init_fs_state(struct gk20a *g); void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable); -void gv11b_ltc_isr(struct gk20a *g); -void gv11b_ltc_lts_isr(struct gk20a *g, - unsigned int ltc, unsigned int slice); +void gv11b_ltc_isr(struct gk20a *g, unsigned int ltc); +void gv11b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice); #endif diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.c b/drivers/gpu/nvgpu/common/ltc/ltc_tu104.c index 500497fe6..c1be6dc4d 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.c +++ b/drivers/gpu/nvgpu/common/ltc/ltc_tu104.c @@ -229,15 +229,3 @@ out: nvgpu_mutex_release(&g->mm.l2_op_lock); return err; } - -void tu104_ltc_isr(struct gk20a *g) -{ - unsigned int ltc, slice; - - /* Go through all the LTCs explicitly */ - for (ltc = 0; ltc < g->ltc_count; ltc++) { - for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { - gv11b_ltc_lts_isr(g, ltc, slice); - } - } -} diff --git a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.h b/drivers/gpu/nvgpu/common/ltc/ltc_tu104.h index d75d75824..eca61388f 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc_tu104.h +++ b/drivers/gpu/nvgpu/common/ltc/ltc_tu104.h @@ -29,7 +29,6 @@ enum gk20a_cbc_op; struct gk20a; struct gr_gk20a; -void tu104_ltc_isr(struct gk20a *g); u64 ltc_tu104_get_cbc_base_divisor(struct gk20a *g); void ltc_tu104_init_fs_state(struct gk20a *g); int ltc_tu104_init_comptags(struct gk20a *g, struct gr_gk20a *gr); diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c index 1194be85d..1319d0b3c 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c @@ -75,7 +75,7 @@ void gm20b_mc_isr_stall(struct gk20a *g) g->ops.priv_ring.isr(g); } if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { - g->ops.ltc.isr(g); + g->ops.mc.ltc_isr(g); } if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { g->ops.bus.isr(g); @@ -341,3 +341,18 @@ void gm20b_mc_fb_reset(struct gk20a *g) | mc_elpg_enable_hub_enabled_f(); gk20a_writel(g, mc_elpg_enable_r(), val); } + +void gm20b_mc_ltc_isr(struct gk20a *g) +{ + u32 mc_intr; + unsigned int ltc; + + mc_intr = gk20a_readl(g, mc_intr_ltc_r()); + nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); + for (ltc = 0; ltc < g->ltc_count; ltc++) { + if ((mc_intr & 1U << ltc) == 0) { + continue; + } + g->ops.ltc.isr(g, ltc); + } +} diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h index fcf020775..b71884d28 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h @@ -50,5 +50,6 @@ void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit); bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit); void gm20b_mc_fb_reset(struct gk20a *g); +void gm20b_mc_ltc_isr(struct gk20a *g); #endif /* NVGPU_MC_GM20B_H */ diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c index 648884038..a9b0a31c8 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c @@ -135,7 +135,7 @@ void mc_gp10b_isr_stall(struct gk20a *g) g->ops.priv_ring.isr(g); } if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { - g->ops.ltc.isr(g); + g->ops.mc.ltc_isr(g); } if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { g->ops.bus.isr(g); @@ -222,3 +222,18 @@ void mc_gp10b_log_pending_intrs(struct gk20a *g) } } + +void mc_gp10b_ltc_isr(struct gk20a *g) +{ + u32 mc_intr; + unsigned int ltc; + + mc_intr = gk20a_readl(g, mc_intr_ltc_r()); + nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); + for (ltc = 0; ltc < g->ltc_count; ltc++) { + if ((mc_intr & 1U << ltc) == 0) { + continue; + } + g->ops.ltc.isr(g, ltc); + } +} diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.h b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h index ee3c0c3b0..cc2c7ab8f 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gp10b.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h @@ -43,5 +43,6 @@ void mc_gp10b_intr_stall_resume(struct gk20a *g); u32 mc_gp10b_intr_nonstall(struct gk20a *g); void mc_gp10b_intr_nonstall_pause(struct gk20a *g); void mc_gp10b_intr_nonstall_resume(struct gk20a *g); +void mc_gp10b_ltc_isr(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/common/mc/mc_tu104.c b/drivers/gpu/nvgpu/common/mc/mc_tu104.c index 73b9a80ec..d10a6e085 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_tu104.c +++ b/drivers/gpu/nvgpu/common/mc/mc_tu104.c @@ -410,3 +410,14 @@ void mc_tu104_fbpa_isr(struct gk20a *g) g->ops.fb.handle_fbpa_intr(g, i); } } + + +void mc_tu104_ltc_isr(struct gk20a *g) +{ + unsigned int ltc; + + /* Go through all the LTCs explicitly */ + for (ltc = 0; ltc < g->ltc_count; ltc++) { + g->ops.ltc.isr(g, ltc); + } +} diff --git a/drivers/gpu/nvgpu/common/mc/mc_tu104.h b/drivers/gpu/nvgpu/common/mc/mc_tu104.h index bfec0fa07..356be3af1 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_tu104.h +++ b/drivers/gpu/nvgpu/common/mc/mc_tu104.h @@ -61,5 +61,6 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g); bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); void intr_tu104_log_pending_intrs(struct gk20a *g); void mc_tu104_fbpa_isr(struct gk20a *g); +void mc_tu104_ltc_isr(struct gk20a *g); #endif /* NVGPU_MC_TU104_H */ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index a4227bfdc..42f845617 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -599,6 +599,7 @@ static const struct gpu_ops gm20b_ops = { .reset_mask = gm20b_mc_reset_mask, .is_enabled = gm20b_mc_is_enabled, .fb_reset = gm20b_mc_fb_reset, + .ltc_isr = gm20b_mc_ltc_isr, }, .debug = { .show_dump = gk20a_debug_show_dump, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 2f93a4a36..14f5bbc77 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -727,6 +727,7 @@ static const struct gpu_ops gp106_ops = { .reset_mask = gm20b_mc_reset_mask, .is_enabled = gm20b_mc_is_enabled, .fb_reset = NULL, + .ltc_isr = mc_gp10b_ltc_isr, }, .debug = { .show_dump = gk20a_debug_show_dump, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 3f2d27754..44fbbfb6b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -661,6 +661,7 @@ static const struct gpu_ops gp10b_ops = { .reset_mask = gm20b_mc_reset_mask, .is_enabled = gm20b_mc_is_enabled, .fb_reset = gm20b_mc_fb_reset, + .ltc_isr = mc_gp10b_ltc_isr, }, .debug = { .show_dump = gk20a_debug_show_dump, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 5bb1a067a..4a10df6bc 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -844,6 +844,7 @@ static const struct gpu_ops gv100_ops = { .reset_mask = gv100_mc_reset_mask, .is_enabled = gm20b_mc_is_enabled, .fb_reset = NULL, + .ltc_isr = mc_gp10b_ltc_isr, }, .debug = { .show_dump = gk20a_debug_show_dump, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 3613f529b..b14d9b850 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -785,6 +785,7 @@ static const struct gpu_ops gv11b_ops = { .reset_mask = gm20b_mc_reset_mask, .is_enabled = gm20b_mc_is_enabled, .fb_reset = NULL, + .ltc_isr = mc_gp10b_ltc_isr, }, .debug = { .show_dump = gk20a_debug_show_dump, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index aaed89f73..97bbe7e9b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -204,7 +204,7 @@ struct gpu_ops { void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); void (*set_enabled)(struct gk20a *g, bool enabled); void (*init_fs_state)(struct gk20a *g); - void (*isr)(struct gk20a *g); + void (*isr)(struct gk20a *g, unsigned int ltc); u32 (*cbc_fix_config)(struct gk20a *g, int base); void (*flush)(struct gk20a *g); void (*intr_en_illegal_compstat)(struct gk20a *g, bool enable); @@ -1186,6 +1186,7 @@ struct gpu_ops { void (*fbpa_isr)(struct gk20a *g); u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit); void (*fb_reset)(struct gk20a *g); + void (*ltc_isr)(struct gk20a *g); } mc; struct { void (*show_dump)(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 6849e947c..eed4f376a 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -326,7 +326,7 @@ static const struct gpu_ops tu104_ops = { .init_fs_state = ltc_tu104_init_fs_state, .init_comptags = ltc_tu104_init_comptags, .cbc_ctrl = ltc_tu104_cbc_ctrl, - .isr = tu104_ltc_isr, + .isr = gv11b_ltc_isr, .cbc_fix_config = NULL, .flush = gm20b_flush_ltc, .set_enabled = gp10b_ltc_set_enabled, @@ -821,6 +821,7 @@ static const struct gpu_ops tu104_ops = { .reset_mask = gv100_mc_reset_mask, .is_enabled = gm20b_mc_is_enabled, .fb_reset = NULL, + .ltc_isr = mc_tu104_ltc_isr, }, .debug = { .show_dump = gk20a_debug_show_dump,