From bd021a17045e3da36594538424b101f6cb364ea8 Mon Sep 17 00:00:00 2001 From: Scott Long Date: Thu, 8 Aug 2019 10:19:12 -0700 Subject: [PATCH] gpu: nvgpu: gr: fix misra 2.7 violations Advisory Rule 2.7 states that there should be no unused parameters in functions. This patch removes the unused 'post_event', 'fault_ch' and 'hww_global_esr' parameters from the following: * gv11b_gr_intr_handle_l1_tag_exception() * gv11b_gr_intr_handle_lrf_exception() * gv11b_gr_intr_handle_cbu_exception() * gv11b_gr_intr_handle_l1_data_exception() * gv11b_gr_intr_handle_icache_exception() These changes allowed the same parameters to be removed from the the gr.intr.handle_tpc_sm_ecc_exception() interface. Jira NVGPU-3178 Change-Id: I4d5dcbf2a5325e38782cdac67f9dd0b223fa1a18 Signed-off-by: Scott Long Reviewed-on: https://git-master.nvidia.com/r/2171220 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_intr.c | 3 +- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h | 4 +-- .../nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c | 34 ++++++------------- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 4 +-- 4 files changed, 14 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr.c b/drivers/gpu/nvgpu/common/gr/gr_intr.c index 04e4ec6fc..bfab536fb 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_intr.c +++ b/drivers/gpu/nvgpu/common/gr/gr_intr.c @@ -80,8 +80,7 @@ static int gr_intr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, "GPC%d TPC%d: SM exception pending", gpc, tpc); if (g->ops.gr.intr.handle_tpc_sm_ecc_exception != NULL) { - g->ops.gr.intr.handle_tpc_sm_ecc_exception(g, gpc, tpc, - post_event, fault_ch, hww_global_esr); + g->ops.gr.intr.handle_tpc_sm_ecc_exception(g, gpc, tpc); } g->ops.gr.intr.get_esr_sm_sel(g, gpc, tpc, &esr_sm_sel); diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h index fe9c53567..c65e5c053 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h @@ -92,9 +92,7 @@ void gv11b_gr_intr_enable_gpc_exceptions(struct gk20a *g, void gv11b_gr_intr_set_hww_esr_report_mask(struct gk20a *g); void gv11b_gr_intr_handle_tpc_sm_ecc_exception(struct gk20a *g, - u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr); + u32 gpc, u32 tpc); void gv11b_gr_intr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); void gv11b_gr_intr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c index 07298d159..42cc6f457 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c @@ -959,9 +959,7 @@ static void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g, } } -static void gv11b_gr_intr_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr) +static void gv11b_gr_intr_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc) { u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); @@ -1058,9 +1056,7 @@ static void gv11b_gr_intr_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f()); } -static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr) +static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc) { u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); @@ -1176,9 +1172,7 @@ static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f()); } -static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr) +static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc) { u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); @@ -1283,9 +1277,7 @@ static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f()); } -static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr) +static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc) { u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); @@ -1460,9 +1452,7 @@ static void gv11b_gr_intr_report_icache_corrected_err(struct gk20a *g, } } -static void gv11b_gr_intr_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr) +static void gv11b_gr_intr_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc) { u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); @@ -1559,24 +1549,22 @@ static void gv11b_gr_intr_handle_icache_exception(struct gk20a *g, u32 gpc, u32 } void gv11b_gr_intr_handle_tpc_sm_ecc_exception(struct gk20a *g, - u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr) + u32 gpc, u32 tpc) { /* Check for L1 tag ECC errors. */ - gv11b_gr_intr_handle_l1_tag_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + gv11b_gr_intr_handle_l1_tag_exception(g, gpc, tpc); /* Check for LRF ECC errors. */ - gv11b_gr_intr_handle_lrf_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + gv11b_gr_intr_handle_lrf_exception(g, gpc, tpc); /* Check for CBU ECC errors. */ - gv11b_gr_intr_handle_cbu_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + gv11b_gr_intr_handle_cbu_exception(g, gpc, tpc); /* Check for L1 data ECC errors. */ - gv11b_gr_intr_handle_l1_data_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + gv11b_gr_intr_handle_l1_data_exception(g, gpc, tpc); /* Check for L0 && L1 icache ECC errors. */ - gv11b_gr_intr_handle_icache_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + gv11b_gr_intr_handle_icache_exception(g, gpc, tpc); } void gv11b_gr_intr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index e1e7be653..1c8ba8e18 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -895,9 +895,7 @@ struct gpu_ops { void (*flush_channel_tlb)(struct gk20a *g); void (*set_hww_esr_report_mask)(struct gk20a *g); void (*handle_tpc_sm_ecc_exception)(struct gk20a *g, - u32 gpc, u32 tpc, - bool *post_event, struct nvgpu_channel *fault_ch, - u32 *hww_global_esr); + u32 gpc, u32 tpc); void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc,