gpu: nvgpu: move preempt code to common/fifo and hal/fifo

Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo

Remove fifo.get_preempt_timeout

Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel

Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal

Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc

JIRA NVGPU-3144

Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/channel.c

@@ -51,6 +51,7 @@
 #include <nvgpu/runlist.h>
 #include <nvgpu/fifo/userd.h>
 #include <nvgpu/fence.h>
+#include <nvgpu/preempt.h>
 
 #include "common/gr/gr_priv.h"
 #include "gk20a/gr_gk20a.h"
@@ -1175,7 +1176,7 @@ int nvgpu_channel_set_syncpt(struct channel_gk20a *ch)
 		gk20a_disable_channel_tsg(g, ch);
 
 		/* preempt the channel */
-		WARN_ON(gk20a_fifo_preempt(g, ch) != 0);
+		WARN_ON(nvgpu_preempt_channel(g, ch) != 0);
 
 		g->ops.ramfc.set_syncpt(ch, new_syncpt);
 	}
@@ -2516,7 +2517,7 @@ int nvgpu_channel_suspend_all_serviceable_ch(struct gk20a *g)
 			/* disable channel */
 			gk20a_disable_channel_tsg(g, ch);
 			/* preempt the channel */
-			gk20a_fifo_preempt(g, ch);
+			nvgpu_preempt_channel(g, ch);
 			/* wait for channel update notifiers */
 			if (g->os_channel.work_completion_cancel_sync != NULL) {
 				g->os_channel.work_completion_cancel_sync(ch);

drivers/gpu/nvgpu/common/fifo/preempt.c

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/tsg.h>
+#include <nvgpu/preempt.h>
+
+
+u32 nvgpu_preempt_get_timeout(struct gk20a *g)
+{
+	return g->ctxsw_timeout_period_ms;
+}
+
+int nvgpu_preempt_channel(struct gk20a *g, struct channel_gk20a *ch)
+{
+	int err;
+	struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch);
+
+	if (tsg != NULL) {
+		err = g->ops.fifo.preempt_tsg(ch->g, tsg);
+	} else {
+		err = g->ops.fifo.preempt_channel(ch->g, ch);
+	}
+
+	return err;
+}
+
+/* called from rc */
+void nvgpu_preempt_poll_tsg_on_pbdma(struct gk20a *g,
+		struct tsg_gk20a *tsg)
+{
+	struct fifo_gk20a *f = &g->fifo;
+	u32 runlist_id;
+	unsigned long runlist_served_pbdmas;
+	unsigned long pbdma_id_bit;
+	u32 tsgid, pbdma_id;
+
+	if (g->ops.fifo.preempt_poll_pbdma == NULL) {
+		return;
+	}
+
+	if (tsg == NULL) {
+		return;
+	}
+
+	tsgid = tsg->tsgid;
+	runlist_id = tsg->runlist_id;
+	runlist_served_pbdmas = f->runlist_info[runlist_id]->pbdma_bitmask;
+
+	for_each_set_bit(pbdma_id_bit, &runlist_served_pbdmas, f->num_pbdma) {
+		pbdma_id = U32(pbdma_id_bit);
+		/*
+		 * If pbdma preempt fails the only option is to reset
+		 * GPU. Any sort of hang indicates the entire GPU’s
+		 * memory system would be blocked.
+		 */
+		if (g->ops.fifo.preempt_poll_pbdma(g, tsgid,
+				pbdma_id) != 0) {
+			nvgpu_report_host_error(g, 0,
+					GPU_HOST_PBDMA_PREEMPT_ERROR,
+					pbdma_id);
+			nvgpu_err(g, "PBDMA preempt failed");
+		}
+	}
+}

drivers/gpu/nvgpu/common/gr/gr_setup.c

@@ -28,6 +28,7 @@
 #include <nvgpu/gr/zcull.h>
 #include <nvgpu/gr/setup.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/preempt.h>
 
 #include "gr_priv.h"
 
@@ -44,7 +45,7 @@ static int nvgpu_gr_setup_zcull(struct gk20a *g, struct channel_gk20a *c,
 		return ret;
 	}
 
-	ret = gk20a_fifo_preempt(g, c);
+	ret = nvgpu_preempt_channel(g, c);
 	if (ret != 0) {
 		if (gk20a_enable_channel_tsg(g, c) != 0) {
 			nvgpu_err(g, "failed to re-enable channel/TSG");
@@ -267,7 +268,7 @@ int nvgpu_gr_setup_set_preemption_mode(struct channel_gk20a *ch,
 		return err;
 	}
 
-	err = gk20a_fifo_preempt(g, ch);
+	err = nvgpu_preempt_channel(g, ch);
 	if (err != 0) {
 		goto enable_ch;
 	}

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -24,6 +24,7 @@
 #include "hal/bus/bus_gm20b.h"
 #include "hal/regops/regops_gv11b.h"
 #include "hal/class/class_gv11b.h"
+#include "hal/fifo/preempt_gv11b.h"
 #include "hal/fifo/engines_gv11b.h"
 #include "hal/fifo/pbdma_gm20b.h"
 #include "hal/fifo/pbdma_gp10b.h"