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gpu: nvgpu: move preempt code to common/fifo and hal/fifo

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Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo

Remove fifo.get_preempt_timeout

Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel

Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal

Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc

JIRA NVGPU-3144

Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-04-18 12:02:35 -07:00
committed by mobile promotions
parent edaddb9bb2
commit bdfc26af8b
27 changed files with 889 additions and 645 deletions
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5
drivers/gpu/nvgpu/common/gr/gr_setup.c
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@@ -28,6 +28,7 @@
#include <nvgpu/gr/zcull.h>
#include <nvgpu/gr/setup.h>
#include <nvgpu/channel.h>
#include <nvgpu/preempt.h>
#include "gr_priv.h"
@@ -44,7 +45,7 @@ static int nvgpu_gr_setup_zcull(struct gk20a *g, struct channel_gk20a *c,
return ret;
}
ret = gk20a_fifo_preempt(g, c);
ret = nvgpu_preempt_channel(g, c);
if (ret != 0) {
if (gk20a_enable_channel_tsg(g, c) != 0) {
nvgpu_err(g, "failed to re-enable channel/TSG");
@@ -267,7 +268,7 @@ int nvgpu_gr_setup_set_preemption_mode(struct channel_gk20a *ch,
return err;
}
err = gk20a_fifo_preempt(g, ch);
err = nvgpu_preempt_channel(g, ch);
if (err != 0) {
goto enable_ch;
}