nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: move preempt code to common/fifo and hal/fifo

Browse Source 
Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo

Remove fifo.get_preempt_timeout

Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel

Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal

Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc

JIRA NVGPU-3144

Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-04-18 12:02:35 -07:00
committed by mobile promotions
parent edaddb9bb2
commit bdfc26af8b
27 changed files with 889 additions and 645 deletions
Download Patch File Download Diff File Expand all files Collapse all files

182
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -119,188 +119,6 @@ int gk20a_init_fifo_setup_hw(struct gk20a *g)
return 0;
}
void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg)
{
if (is_tsg) {
gk20a_writel(g, fifo_preempt_r(),
fifo_preempt_id_f(id) |
fifo_preempt_type_tsg_f());
} else {
gk20a_writel(g, fifo_preempt_r(),
fifo_preempt_chid_f(id) |
fifo_preempt_type_channel_f());
}
}
static u32 gk20a_fifo_get_preempt_timeout(struct gk20a *g)
{
/* Use fifo_eng_timeout converted to ms for preempt
* polling. gr_idle_timeout i.e 3000 ms is and not appropriate
* for polling preempt done as context switch timeout gets
* triggered every ctxsw_timeout_period_ms.
*/
return g->ctxsw_timeout_period_ms;
}
int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
unsigned int id_type)
{
struct nvgpu_timeout timeout;
u32 delay = POLL_DELAY_MIN_US;
int ret = 0;
ret = nvgpu_timeout_init(g, &timeout, gk20a_fifo_get_preempt_timeout(g),
NVGPU_TIMER_CPU_TIMER);
if (ret != 0) {
nvgpu_err(g, "nvgpu_timeout_init failed err=%d ", ret);
return ret;
}
ret = -EBUSY;
do {
if ((gk20a_readl(g, fifo_preempt_r()) &
fifo_preempt_pending_true_f()) == 0U) {
ret = 0;
break;
}
nvgpu_usleep_range(delay, delay * 2U);
delay = min_t(u32, delay << 1, POLL_DELAY_MAX_US);
} while (nvgpu_timeout_expired(&timeout) == 0);
if (ret != 0) {
nvgpu_err(g, "preempt timeout: id: %u id_type: %d ",
id, id_type);
}
return ret;
}
int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg)
{
int ret;
unsigned int id_type;
nvgpu_log_fn(g, "id: %d is_tsg: %d", id, is_tsg);
/* issue preempt */
gk20a_fifo_issue_preempt(g, id, is_tsg);
id_type = is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL;
/* wait for preempt */
ret = g->ops.fifo.is_preempt_pending(g, id, id_type);
return ret;
}
int gk20a_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch)
{
int ret = 0;
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
int mutex_ret = 0;
int err = 0;
nvgpu_log_fn(g, "chid: %d", ch->chid);
/* we have no idea which runlist we are using. lock all */
nvgpu_fifo_lock_active_runlists(g);
mutex_ret = nvgpu_pmu_lock_acquire(g, &g->pmu,
PMU_MUTEX_ID_FIFO, &token);
ret = __locked_fifo_preempt(g, ch->chid, false);
if (mutex_ret == 0) {
err = nvgpu_pmu_lock_release(g, &g->pmu, PMU_MUTEX_ID_FIFO,
&token);
if (err != 0) {
nvgpu_err(g, "nvgpu_pmu_lock_release failed err=%d",
err);
}
}
nvgpu_fifo_unlock_active_runlists(g);
if (ret != 0) {
if (nvgpu_platform_is_silicon(g)) {
nvgpu_err(g, "preempt timed out for chid: %u, "
"ctxsw timeout will trigger recovery if needed",
ch->chid);
} else {
struct tsg_gk20a *tsg;
nvgpu_err(g, "preempt channel %d timeout", ch->chid);
tsg = tsg_gk20a_from_ch(ch);
if (tsg != NULL) {
nvgpu_rc_preempt_timeout(g, tsg);
} else {
nvgpu_err(g, "chid: %d is not bound to tsg",
ch->chid);
}
}
}
return ret;
}
int gk20a_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
{
int ret = 0;
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
int mutex_ret = 0;
int err = 0;
nvgpu_log_fn(g, "tsgid: %d", tsg->tsgid);
/* we have no idea which runlist we are using. lock all */
nvgpu_fifo_lock_active_runlists(g);
mutex_ret = nvgpu_pmu_lock_acquire(g, &g->pmu,
PMU_MUTEX_ID_FIFO, &token);
ret = __locked_fifo_preempt(g, tsg->tsgid, true);
if (mutex_ret == 0) {
err = nvgpu_pmu_lock_release(g, &g->pmu, PMU_MUTEX_ID_FIFO,
&token);
if (err != 0) {
nvgpu_err(g, "nvgpu_pmu_lock_release failed err=%d",
err);
}
}
nvgpu_fifo_unlock_active_runlists(g);
if (ret != 0) {
if (nvgpu_platform_is_silicon(g)) {
nvgpu_err(g, "preempt timed out for tsgid: %u, "
"ctxsw timeout will trigger recovery if needed",
tsg->tsgid);
} else {
nvgpu_err(g, "preempt TSG %d timeout", tsg->tsgid);
nvgpu_rc_preempt_timeout(g, tsg);
}
}
return ret;
}
int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch)
{
int err;
struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch);
if (tsg != NULL) {
err = g->ops.fifo.preempt_tsg(ch->g, tsg);
} else {
err = g->ops.fifo.preempt_channel(ch->g, ch);
}
return err;
}
u32 gk20a_fifo_default_timeslice_us(struct gk20a *g)
{
u64 slice = (((u64)(NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT <<