From bf03ffbb05d6ecc4bcdedced8145b8fb0407aa64 Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Tue, 14 May 2019 14:03:45 +0530 Subject: [PATCH] gpu: nvgpu: obj_ctx: fix CERT-C INT violations Error: CERT INT31-C: drivers/gpu/nvgpu/common/gr/obj_ctx.c:310: cert_violation: Casting "size" from "unsigned long" to "unsigned int" without checking its value may result in lost or misinterpreted data. Error: CERT INT30-C: drivers/gpu/nvgpu/common/gr/obj_ctx.c:594: cert_violation: Unsigned integer operation "(*g->ops.gr.init.get_patch_slots)(g, config) * 2U" may wrap. JIRA NVGPU-3410 Change-Id: Icae8246903693d7f5ad66635d3e81d22f6ff2df5 Signed-off-by: Nitin Kumbhar Reviewed-on: https://git-master.nvidia.com/r/2118522 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/obj_ctx.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c index b1661a60a..611717aa9 100644 --- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "obj_ctx_priv.h" @@ -283,7 +284,7 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr_config *config, struct nvgpu_gr_ctx *gr_ctx, bool patch) { u64 addr; - size_t size; + u32 size; nvgpu_log_fn(g, " "); @@ -297,15 +298,16 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g, /* global pagepool buffer */ addr = nvgpu_gr_ctx_get_global_ctx_va(gr_ctx, NVGPU_GR_CTX_PAGEPOOL_VA); - size = nvgpu_gr_global_ctx_get_size(global_ctx_buffer, - NVGPU_GR_GLOBAL_CTX_PAGEPOOL); + size = nvgpu_secure_cast_u64_to_u32(nvgpu_gr_global_ctx_get_size( + global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PAGEPOOL)); g->ops.gr.init.commit_global_pagepool(g, gr_ctx, addr, size, patch, true); /* global bundle cb */ addr = nvgpu_gr_ctx_get_global_ctx_va(gr_ctx, NVGPU_GR_CTX_CIRCULAR_VA); - size = g->ops.gr.init.get_bundle_cb_default_size(g); + size = nvgpu_secure_cast_u64_to_u32( + g->ops.gr.init.get_bundle_cb_default_size(g)); g->ops.gr.init.commit_global_bundle_cb(g, gr_ctx, addr, size, patch); @@ -591,8 +593,9 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g, nvgpu_gr_ctx_set_size(gr_ctx_desc, NVGPU_GR_CTX_PATCH_CTX, - g->ops.gr.init.get_patch_slots(g, config) * - PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY); + nvgpu_secure_mult_u32( + g->ops.gr.init.get_patch_slots(g, config), + PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY)); err = nvgpu_gr_ctx_alloc_patch_ctx(g, gr_ctx, gr_ctx_desc, vm); if (err != 0) {