From bf861813b7b678e4a92bc6cd5693ecb60ef6ee2d Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Sun, 9 Jun 2019 22:14:54 -0700 Subject: [PATCH] gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver Fixed CERT-C issues in hal ltc intr driver by replacing arithmetic operations with nvgpu safe ops. JIRA NVGPU-3623 Change-Id: I4203e7bdd02c41578cad8446f02247749c8cef5c Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2133291 Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: Alex Waterman Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Nitin Kumbhar GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/hal/ltc/intr/ltc_intr_gm20b.c | 14 ++++--- .../gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c | 42 ++++++++++++------- .../gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c | 41 +++++++++++------- 3 files changed, 61 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gm20b.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gm20b.c index 4624389b4..74f1a86cf 100644 --- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gm20b.c +++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gm20b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ltc_intr_gm20b.h" @@ -50,18 +51,21 @@ static void gm20b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); - ltc_intr = nvgpu_readl(g, ltc_ltc0_lts0_intr_r() + - ltc_stride * ltc + lts_stride * slice); + ltc_intr = nvgpu_readl(g, nvgpu_safe_add_u32(ltc_ltc0_lts0_intr_r(), + nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc), + nvgpu_safe_mult_u32(lts_stride, slice)))); nvgpu_err(g, "ltc%d, slice %d: %08x", ltc, slice, ltc_intr); - nvgpu_writel(g, ltc_ltc0_lts0_intr_r() + ltc_stride * ltc + - lts_stride * slice, ltc_intr); + nvgpu_writel(g, nvgpu_safe_add_u32(ltc_ltc0_lts0_intr_r(), + nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc), + nvgpu_safe_mult_u32(lts_stride, slice))), ltc_intr); } void gm20b_ltc_intr_isr(struct gk20a *g, u32 ltc) { u32 slice; - for (slice = 0U; slice < g->ltc->slices_per_ltc; slice++) { + for (slice = 0U; slice < g->ltc->slices_per_ltc; slice = + nvgpu_safe_add_u32(slice, 1U)) { gm20b_ltc_intr_handle_lts_interrupts(g, ltc, slice); } } diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c index 0d62f99de..b7ee37efe 100644 --- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c +++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include @@ -39,8 +40,10 @@ void gp10b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc, u32 slice) u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); - offset = ltc_stride * ltc + lts_stride * slice; - ltc_intr = nvgpu_readl(g, ltc_ltc0_lts0_intr_r() + offset); + offset = nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc), + nvgpu_safe_mult_u32(lts_stride, slice)); + ltc_intr = nvgpu_readl(g, nvgpu_safe_add_u32( + ltc_ltc0_lts0_intr_r(), offset)); /* Detect and handle ECC errors */ if ((ltc_intr & @@ -51,15 +54,18 @@ void gp10b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc, u32 slice) "Single bit error detected in GPU L2!"); ecc_stats_reg_val = - nvgpu_readl(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset); - g->ecc.ltc.ecc_sec_count[ltc][slice].counter += - ltc_ltc0_lts0_dstg_ecc_report_sec_count_v( - ecc_stats_reg_val); + nvgpu_readl(g, nvgpu_safe_add_u32( + ltc_ltc0_lts0_dstg_ecc_report_r(), offset)); + g->ecc.ltc.ecc_sec_count[ltc][slice].counter = + nvgpu_safe_add_u32( + g->ecc.ltc.ecc_sec_count[ltc][slice].counter, + ltc_ltc0_lts0_dstg_ecc_report_sec_count_v( + ecc_stats_reg_val)); ecc_stats_reg_val &= ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); nvgpu_writel_check(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset, + nvgpu_safe_add_u32( + ltc_ltc0_lts0_dstg_ecc_report_r(), offset), ecc_stats_reg_val); if (g->ops.mm.cache.l2_flush(g, true) != 0) { nvgpu_err(g, "l2_flush failed"); @@ -75,26 +81,32 @@ void gp10b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc, u32 slice) ecc_stats_reg_val = nvgpu_readl(g, ltc_ltc0_lts0_dstg_ecc_report_r() + offset); - g->ecc.ltc.ecc_ded_count[ltc][slice].counter += - ltc_ltc0_lts0_dstg_ecc_report_ded_count_v( - ecc_stats_reg_val); + g->ecc.ltc.ecc_ded_count[ltc][slice].counter = + nvgpu_safe_add_u32( + g->ecc.ltc.ecc_ded_count[ltc][slice].counter, + ltc_ltc0_lts0_dstg_ecc_report_ded_count_v( + ecc_stats_reg_val)); ecc_stats_reg_val &= ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); nvgpu_writel_check(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset, + nvgpu_safe_add_u32( + ltc_ltc0_lts0_dstg_ecc_report_r(), offset), ecc_stats_reg_val); } nvgpu_err(g, "ltc%d, slice %d: %08x", ltc, slice, ltc_intr); - nvgpu_writel_check(g, ltc_ltc0_lts0_intr_r() + - ltc_stride * ltc + lts_stride * slice, ltc_intr); + nvgpu_writel_check(g, nvgpu_safe_add_u32(ltc_ltc0_lts0_intr_r(), + nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc), + nvgpu_safe_mult_u32(lts_stride, slice))), + ltc_intr); } void gp10b_ltc_intr_isr(struct gk20a *g, u32 ltc) { u32 slice; - for (slice = 0U; slice < g->ltc->slices_per_ltc; slice++) { + for (slice = 0U; slice < g->ltc->slices_per_ltc; slice = + nvgpu_safe_add_u32(slice, 1U)) { gp10b_ltc_intr_handle_lts_interrupts(g, ltc, slice); } } diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c index 2381ead6d..32da405f6 100644 --- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c @@ -24,6 +24,7 @@ #include #include +#include #include #include "ltc_intr_gp10b.h" @@ -88,9 +89,10 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); - offset = ltc_stride * ltc + lts_stride * slice; - ltc_intr3 = nvgpu_readl(g, ltc_ltc0_lts0_intr3_r() + - offset); + offset = nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc_stride, ltc), + nvgpu_safe_mult_u32(lts_stride, slice)); + ltc_intr3 = nvgpu_readl(g, nvgpu_safe_add_u32( + ltc_ltc0_lts0_intr3_r(), offset)); /* Detect and handle ECC PARITY errors */ if ((ltc_intr3 & @@ -98,17 +100,19 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g, ltc_ltcs_ltss_intr3_ecc_corrected_m())) != 0U) { ecc_status = nvgpu_readl(g, - ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset); - ecc_addr = nvgpu_readl(g, - ltc_ltc0_lts0_l2_cache_ecc_address_r() + offset); + nvgpu_safe_add_u32( + ltc_ltc0_lts0_l2_cache_ecc_status_r(), offset)); + ecc_addr = nvgpu_readl(g, nvgpu_safe_add_u32( + ltc_ltc0_lts0_l2_cache_ecc_address_r(), offset)); dstg_ecc_addr = nvgpu_readl(g, - ltc_ltc0_lts0_dstg_ecc_address_r() + offset); - corrected_cnt = nvgpu_readl(g, - ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + - offset); - uncorrected_cnt = nvgpu_readl(g, - ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + - offset); + nvgpu_safe_add_u32( + ltc_ltc0_lts0_dstg_ecc_address_r(), offset)); + corrected_cnt = nvgpu_readl(g, nvgpu_safe_add_u32( + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(), + offset)); + uncorrected_cnt = nvgpu_readl(g, nvgpu_safe_add_u32( + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(), + offset)); corrected_delta = ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v( @@ -124,15 +128,20 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g, /* clear the interrupt */ if ((corrected_delta > 0U) || (corrected_overflow != 0U)) { nvgpu_writel_check(g, - ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); + nvgpu_safe_add_u32( + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(), + offset), 0); } if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) { nvgpu_writel_check(g, - ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); + nvgpu_safe_add_u32( + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(), + offset), 0); } nvgpu_writel_check(g, - ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, + nvgpu_safe_add_u32( + ltc_ltc0_lts0_l2_cache_ecc_status_r(), offset), ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); /* update counters per slice */