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gpu: nvgpu: Read sm error ioctl support for tsg
Add READ_SM_ERROR IOCTL support to TSG level. Moved the struct to save the sm_error details from gr to tsg as the sm_error support is context based, not global. Also corrected MISRA 21.1 error in header file. nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and nvgpu_dbg_gpu_ioctl_read_single_sm_error_state functions are modified to use the tsg struct nvgpu_tsg_sm_error_state. Bug 200412642 Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794856 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -35,6 +35,7 @@
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#include "gk20a/gk20a.h"
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#include "gk20a/gr_gk20a.h"
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#include "gk20a/tsg_gk20a.h"
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#include "gk20a/regops_gk20a.h"
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#include "gk20a/dbg_gpu_gk20a.h"
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#include "os_linux.h"
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@@ -271,20 +272,23 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state(
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u32 sm_id;
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struct channel_gk20a *ch;
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struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
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struct nvgpu_gr_sm_error_state sm_error_state;
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struct nvgpu_tsg_sm_error_state sm_error_state;
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int err = 0;
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/* Not currently supported in the virtual case */
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if (g->is_virtual)
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if (g->is_virtual) {
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return -ENOSYS;
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}
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ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
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if (!ch)
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if (ch == NULL) {
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return -EINVAL;
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}
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sm_id = args->sm_id;
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if (sm_id >= gr->no_of_sm)
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if (sm_id >= gr->no_of_sm) {
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return -EINVAL;
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}
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nvgpu_speculation_barrier();
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@@ -300,13 +304,15 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state(
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args->sm_error_state_record_mem,
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read_size);
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nvgpu_mutex_release(&g->dbg_sessions_lock);
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if (err)
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if (err != 0) {
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return -ENOMEM;
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}
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}
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err = gk20a_busy(g);
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if (err)
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if (err != 0) {
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return err;
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}
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sm_error_state.hww_global_esr =
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sm_error_state_record.hww_global_esr;
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@@ -335,18 +341,36 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
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{
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struct gk20a *g = dbg_s->g;
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struct gr_gk20a *gr = &g->gr;
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struct nvgpu_gr_sm_error_state *sm_error_state;
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struct nvgpu_tsg_sm_error_state *sm_error_state;
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struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
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struct channel_gk20a *ch;
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struct tsg_gk20a *tsg;
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u32 sm_id;
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int err = 0;
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sm_id = args->sm_id;
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if (sm_id >= gr->no_of_sm)
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ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
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if (ch == NULL) {
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return -EINVAL;
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}
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tsg = tsg_gk20a_from_ch(ch);
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if (tsg == NULL) {
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nvgpu_err(g, "no valid tsg from ch");
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return -EINVAL;
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}
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sm_id = args->sm_id;
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if (sm_id >= gr->no_of_sm) {
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return -EINVAL;
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}
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if (tsg->sm_error_states == NULL) {
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return -EINVAL;
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}
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nvgpu_speculation_barrier();
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sm_error_state = gr->sm_error_states + sm_id;
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sm_error_state = tsg->sm_error_states + sm_id;
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sm_error_state_record.hww_global_esr =
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sm_error_state->hww_global_esr;
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sm_error_state_record.hww_warp_esr =
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@@ -370,7 +394,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
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&sm_error_state_record,
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write_size);
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nvgpu_mutex_release(&g->dbg_sessions_lock);
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if (err) {
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if (err != 0) {
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nvgpu_err(g, "copy_to_user failed!");
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return err;
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}
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@@ -1500,8 +1524,9 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
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int err = 0;
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ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
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if (!ch)
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if (ch == NULL) {
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return -EINVAL;
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}
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sm_id = args->sm_id;
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if (sm_id >= gr->no_of_sm)
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@@ -1510,8 +1535,9 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
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nvgpu_speculation_barrier();
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err = gk20a_busy(g);
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if (err)
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if (err != 0) {
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return err;
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}
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err = gr_gk20a_elpg_protected_call(g,
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g->ops.gr.clear_sm_error_state(g, ch, sm_id));
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