From c07ac78d52520fb339c6b8f01acd4d979238f4eb Mon Sep 17 00:00:00 2001 From: Divya Date: Mon, 25 Jul 2022 14:52:51 +0000 Subject: [PATCH] gpu: nvgpu: add correct value for base_period_ms - Due to AELPG, threshold value gets changed as per GPU load. Thus ELPG does not get kicked in and "elpg_transitions" sysfs node does not increase. This causes ELPG test 101 in MODS to fail. - Add correct value for base_period_ms parameter in ga10b_pmu_pg_pre_init() Bug 3733077 Change-Id: I2d2d3d31379395b474f5d18355a2e16049c4a49a Signed-off-by: Divya Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2750549 (cherry picked from commit 1ab707df38fa2802ef9e4a53a0975e14ec56c19b) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2762479 Reviewed-by: svcacv Reviewed-by: Mahantesh Kumbar GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c | 2 +- drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h | 1 - drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ap.h | 18 +++++++++--------- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c index 6959762be..2bff3255a 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c @@ -53,7 +53,7 @@ static int ga10b_pmu_pg_pre_init(struct gk20a *g, struct nvgpu_pmu *pmu) sizeof(struct pmu_rpc_struct_lpwr_loading_pre_init)); rpc.arch_sf_support_mask = NV_PMU_ARCH_FEATURE_SUPPORT_MASK; - rpc.base_period_ms = NV_PMU_BASE_SAMPLING_PERIOD_MS; + rpc.base_period_ms = NV_PMU_PG_AP_BASE_PERIOD_MS; rpc.b_no_pstate_vbios = true; /* Initialize LPWR GR and MS grp data for GRAPHICS and MS_LTC engine */ diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h index 0c387e2ed..3c7484bff 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h @@ -29,7 +29,6 @@ struct gk20a; #define NV_PMU_SUB_FEATURE_SUPPORT_MASK 0xf84 #define NV_PMU_ARCH_FEATURE_SUPPORT_MASK 0x1B3 -#define NV_PMU_BASE_SAMPLING_PERIOD_MS 0xFFFF /* * Brief Identifier for each Lpwr Group Ctrl ids diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ap.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ap.h index 3b26b9677..443b02557 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ap.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ap.h @@ -38,24 +38,24 @@ #define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) #define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) +/* Centralized LPWR callback base period and multiplier */ +#define NV_PMU_PG_AP_BASE_MULTIPLIER_DEFAULT (1) +#define NV_PMU_PG_AP_BASE_PERIOD_MS (1000) + /* * Default values for AP parameters * * IDLE_FILTER_MIN_DEFAULT_US : Default minimum idle threshold value in usec - * IDLE_FILTER_MIN_DI_US : Minimum idle threshold for DI in usec * IDLE_FILTER_MAX_DEFAULT_US : Default maximum idle threshold value in usec - * IDLE_FILTER_MAX_DI_US : Maximum idle threshold for DI in usec * MIN_RESIDENCY_DEFAULT : Default minimum residency per AP sample * BREAKEVEN_RESIDENT_TIME_DEFAULT_US : Default breakeven resident time per cycle - * BREAKEVEN_RESIDENT_TIME_DI_US : Breakeven resident time per cycle for DI * CYCLES_PER_SAMPLE_MAX_DEFAULT : Maximum power feature cycles per AP sample */ -#define NV_PMU_PG_AP_BASE_MULTIPLIER_DEFAULT (1) -#define NV_PMU_PG_AP_IDLE_FILTER_MIN_DEFAULT_US (100) -#define NV_PMU_PG_AP_IDLE_FILTER_MAX_DEFAULT_US (70000) -#define NV_PMU_PG_AP_MIN_RESIDENCY_DEFAULT (1) -#define NV_PMU_PG_AP_BREAK_EVEN_RESIDENT_TIME_DEFAULT_US (1300) -#define NV_PMU_PG_AP_CYCLES_PER_SAMPLE_MAX_DEFAULT (100) +#define NV_PMU_PG_AP_IDLE_FILTER_MIN_DEFAULT_US (100) +#define NV_PMU_PG_AP_IDLE_FILTER_MAX_DEFAULT_US (70000) +#define NV_PMU_PG_AP_MIN_RESIDENCY_DEFAULT (1) +#define NV_PMU_PG_AP_BREAK_EVEN_RESIDENT_TIME_DEFAULT_US (1300) +#define NV_PMU_PG_AP_CYCLES_PER_SAMPLE_MAX_DEFAULT (100) /* Mapping between AP_CTRLs and Histograms */ #define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))