diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml
index d5964bc44..384680a84 100644
--- a/arch/nvgpu-hal-new.yaml
+++ b/arch/nvgpu-hal-new.yaml
@@ -36,7 +36,6 @@ ltc:
       sources: [ hal/ltc/ltc_gm20b.c,
                  hal/ltc/ltc_gm20b_dbg.c,
                  hal/ltc/ltc_gp10b.c,
-                 hal/ltc/ltc_gv11b.c,
                  hal/ltc/ltc_tu104.c,
                  hal/ltc/ltc_tu104.h ]
     intr_fusa:
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index a5e748478..6a39b3790 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -346,7 +346,6 @@ nvgpu-y += \
 	hal/therm/therm_tu104.o \
 	hal/gr/falcon/gr_falcon_gm20b.o \
 	hal/ltc/ltc_gp10b.o \
-	hal/ltc/ltc_gv11b.o  \
 	hal/ltc/intr/ltc_intr_gm20b.o \
 	hal/ltc/intr/ltc_intr_gp10b.o \
 	hal/fb/fb_gm20b.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index 90a8c1767..de0409a56 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -286,7 +286,6 @@ srcs += hal/init/hal_gp10b.c \
 	hal/therm/therm_gp10b.c \
 	hal/ltc/ltc_gm20b.c \
 	hal/ltc/ltc_gp10b.c \
-	hal/ltc/ltc_gv11b.c \
 	hal/ltc/intr/ltc_intr_gm20b.c \
 	hal/ltc/intr/ltc_intr_gp10b.c \
 	hal/fb/fb_gp10b.c \
diff --git a/drivers/gpu/nvgpu/common/gr/zbc.c b/drivers/gpu/nvgpu/common/gr/zbc.c
index 1a474999e..f0f6d832e 100644
--- a/drivers/gpu/nvgpu/common/gr/zbc.c
+++ b/drivers/gpu/nvgpu/common/gr/zbc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -221,7 +221,7 @@ static int nvgpu_gr_zbc_add(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
 			    struct nvgpu_gr_zbc_entry *zbc_val)
 {
 	int added = false;
-#ifdef CONFIG_NVGPU_LS_PMU
+#if defined(CONFIG_NVGPU_LS_PMU) && defined(CONFIG_NVGPU_POWER_PG)
 	u32 entries;
 #endif
 
@@ -252,7 +252,7 @@ static int nvgpu_gr_zbc_add(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
 		goto err_mutex;
 	}
 
-#ifdef CONFIG_NVGPU_LS_PMU
+#if defined(CONFIG_NVGPU_LS_PMU) && defined(CONFIG_NVGPU_POWER_PG)
 	if (added == ZBC_ENTRY_ADDED) {
 		/* update zbc for elpg only when new entry is added */
 		entries = max(
diff --git a/drivers/gpu/nvgpu/common/io/io.c b/drivers/gpu/nvgpu/common/io/io.c
index 2f541c370..91f9460ae 100644
--- a/drivers/gpu/nvgpu/common/io/io.c
+++ b/drivers/gpu/nvgpu/common/io/io.c
@@ -80,7 +80,6 @@ u32 nvgpu_readl_impl(struct gk20a *g, u32 r)
 	return v;
 }
 
-#ifdef CONFIG_NVGPU_NON_FUSA
 void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
 {
 	if (unlikely(!g->regs)) {
@@ -94,7 +93,6 @@ void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
 		nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
 	}
 }
-#endif
 
 void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
 {
diff --git a/drivers/gpu/nvgpu/hal/class/class_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/class/class_gv11b_fusa.c
index c296174d7..6323c3c11 100644
--- a/drivers/gpu/nvgpu/hal/class/class_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/class/class_gv11b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -68,7 +68,11 @@ bool gv11b_class_is_valid_gfx(u32 class_num)
 		valid = true;
 		break;
 	default:
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 		valid = gp10b_class_is_valid_gfx(class_num);
+#else
+		valid = false;
+#endif
 		break;
 	}
 	return valid;
diff --git a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c
index a8ade86b5..6681b8bf8 100644
--- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -54,18 +54,3 @@ int gm20b_gr_config_init_sm_id_table(struct gk20a *g,
 	nvgpu_gr_config_set_no_of_sm(gr_config, sm_id);
 	return 0;
 }
-
-#ifdef CONFIG_NVGPU_GRAPHICS
-u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g,
-	struct nvgpu_gr_config *config, u32 gpc_index)
-{
-	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
-	u32 tmp, tmp1, tmp2;
-
-	tmp1 = nvgpu_safe_mult_u32(gpc_stride, gpc_index);
-	tmp2 = nvgpu_safe_add_u32(gr_gpc0_fs_gpc_r(), tmp1);
-	tmp = nvgpu_readl(g, tmp2);
-
-	return gr_gpc0_fs_gpc_num_available_zculls_v(tmp);
-}
-#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h
index 65d5e07d0..9c034dfe1 100644
--- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,9 +39,9 @@ u32 gm20b_gr_config_get_gpc_mask(struct gk20a *g);
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 int gm20b_gr_config_init_sm_id_table(struct gk20a *g,
 	struct nvgpu_gr_config *gr_config);
+#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
 #ifdef CONFIG_NVGPU_GRAPHICS
 u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g,
 	struct nvgpu_gr_config *config, u32 gpc_index);
 #endif /* CONFIG_NVGPU_GRAPHICS */
-#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
 #endif /* NVGPU_GR_CONFIG_GM20B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b_fusa.c
index 4bbfbf6ea..adc17dc8f 100644
--- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -89,3 +89,18 @@ u32 gm20b_gr_config_get_gpc_mask(struct gk20a *g)
 
 	return (~val) & nvgpu_safe_sub_u32(BIT32(tpc_cnt), 1U);
 }
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g,
+	struct nvgpu_gr_config *config, u32 gpc_index)
+{
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 tmp, tmp1, tmp2;
+
+	tmp1 = nvgpu_safe_mult_u32(gpc_stride, gpc_index);
+	tmp2 = nvgpu_safe_add_u32(gr_gpc0_fs_gpc_r(), tmp1);
+	tmp = nvgpu_readl(g, tmp2);
+
+	return gr_gpc0_fs_gpc_num_available_zculls_v(tmp);
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c
index 23bb91586..a7c7151de 100644
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -37,34 +37,6 @@ void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g,
 		ctxsw_prog_main_image_preemption_options_control_cta_enabled_f());
 }
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-void gm20b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem,
-	u64 addr)
-{
-	addr = addr >> 8;
-	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_ptr_o(),
-		u64_lo32(addr));
-}
-
-void gm20b_ctxsw_prog_set_zcull(struct gk20a *g, struct nvgpu_mem *ctx_mem,
-	u32 mode)
-{
-	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_o(), mode);
-}
-
-void gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw(struct gk20a *g,
-	struct nvgpu_mem *ctx_mem)
-{
-	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_o(),
-			ctxsw_prog_main_image_zcull_mode_no_ctxsw_v());
-}
-
-bool gm20b_ctxsw_prog_is_zcull_mode_separate_buffer(u32 mode)
-{
-	return mode == ctxsw_prog_main_image_zcull_mode_separate_buffer_v();
-}
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 #ifdef CONFIG_NVGPU_FECS_TRACE
 u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void)
 {
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c
index 5703a20e8..89debb824 100644
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -100,3 +100,31 @@ void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g,
 
 	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_misc_options_o(), data);
 }
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+void gm20b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem,
+	u64 addr)
+{
+	addr = addr >> 8;
+	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_ptr_o(),
+		u64_lo32(addr));
+}
+
+void gm20b_ctxsw_prog_set_zcull(struct gk20a *g, struct nvgpu_mem *ctx_mem,
+	u32 mode)
+{
+	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_o(), mode);
+}
+
+void gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem)
+{
+	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_o(),
+			ctxsw_prog_main_image_zcull_mode_no_ctxsw_v());
+}
+
+bool gm20b_ctxsw_prog_is_zcull_mode_separate_buffer(u32 mode)
+{
+	return mode == ctxsw_prog_main_image_zcull_mode_separate_buffer_v();
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c
index 9ed0df80f..b6aa5d15b 100644
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,24 +29,6 @@
 
 #include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h>
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-void gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp(struct gk20a *g,
-	struct nvgpu_mem *ctx_mem)
-{
-	nvgpu_mem_wr(g, ctx_mem,
-		ctxsw_prog_main_image_graphics_preemption_options_o(),
-		ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f());
-}
-
-void gp10b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g,
-	struct nvgpu_mem *ctx_mem, u64 addr)
-{
-	addr = addr >> 8;
-	nvgpu_mem_wr(g, ctx_mem,
-		ctxsw_prog_main_image_full_preemption_ptr_o(), u64_lo32(addr));
-}
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 #ifdef CONFIG_NVGPU_CILP
 void gp10b_ctxsw_prog_set_compute_preemption_mode_cilp(struct gk20a *g,
 	struct nvgpu_mem *ctx_mem)
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c
index 04c1ab390..49142ecc4 100644
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -59,3 +59,21 @@ void gp10b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g,
 
 	gm20b_ctxsw_prog_init_ctxsw_hdr_data(g, ctx_mem);
 }
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+void gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem)
+{
+	nvgpu_mem_wr(g, ctx_mem,
+		ctxsw_prog_main_image_graphics_preemption_options_o(),
+		ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f());
+}
+
+void gp10b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem, u64 addr)
+{
+	addr = addr >> 8;
+	nvgpu_mem_wr(g, ctx_mem,
+		ctxsw_prog_main_image_full_preemption_ptr_o(), u64_lo32(addr));
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c
index 1339f16c8..53dfd7d27 100644
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,42 +29,6 @@
 
 #include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h>
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-void gv11b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem,
-	u64 addr)
-{
-	addr = addr >> 8;
-	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_ptr_o(),
-		u64_lo32(addr));
-	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_ptr_hi_o(),
-		u64_hi32(addr));
-}
-
-void gv11b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g,
-	struct nvgpu_mem *ctx_mem, u64 addr)
-{
-	addr = addr >> 8;
-	nvgpu_mem_wr(g, ctx_mem,
-		ctxsw_prog_main_image_full_preemption_ptr_o(),
-		u64_lo32(addr));
-	nvgpu_mem_wr(g, ctx_mem,
-		ctxsw_prog_main_image_full_preemption_ptr_hi_o(),
-		u64_hi32(addr));
-}
-
-void gv11b_ctxsw_prog_set_full_preemption_ptr_veid0(struct gk20a *g,
-	struct nvgpu_mem *ctx_mem, u64 addr)
-{
-	addr = addr >> 8;
-	nvgpu_mem_wr(g, ctx_mem,
-		ctxsw_prog_main_image_full_preemption_ptr_veid0_o(),
-		u64_lo32(addr));
-	nvgpu_mem_wr(g, ctx_mem,
-		ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(),
-		u64_hi32(addr));
-}
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 #ifdef CONFIG_NVGPU_DEBUGGER
 void gv11b_ctxsw_prog_set_pm_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem,
 	u64 addr)
diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c
index cbb17de62..615ff4377 100644
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -47,3 +47,39 @@ void gv11b_ctxsw_prog_set_type_per_veid_header(struct gk20a *g,
 		ctxsw_prog_main_image_ctl_o(),
 		ctxsw_prog_main_image_ctl_type_per_veid_header_v());
 }
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+void gv11b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem,
+	u64 addr)
+{
+	addr = addr >> 8;
+	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_ptr_o(),
+		u64_lo32(addr));
+	nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_zcull_ptr_hi_o(),
+		u64_hi32(addr));
+}
+
+void gv11b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem, u64 addr)
+{
+	addr = addr >> 8;
+	nvgpu_mem_wr(g, ctx_mem,
+		ctxsw_prog_main_image_full_preemption_ptr_o(),
+		u64_lo32(addr));
+	nvgpu_mem_wr(g, ctx_mem,
+		ctxsw_prog_main_image_full_preemption_ptr_hi_o(),
+		u64_hi32(addr));
+}
+
+void gv11b_ctxsw_prog_set_full_preemption_ptr_veid0(struct gk20a *g,
+	struct nvgpu_mem *ctx_mem, u64 addr)
+{
+	addr = addr >> 8;
+	nvgpu_mem_wr(g, ctx_mem,
+		ctxsw_prog_main_image_full_preemption_ptr_veid0_o(),
+		u64_lo32(addr));
+	nvgpu_mem_wr(g, ctx_mem,
+		ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(),
+		u64_hi32(addr));
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
index f7188f4e9..c50ae6a05 100644
--- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
@@ -572,7 +572,7 @@ defined(CONFIG_NVGPU_CTXSW_FW_ERROR_CODE_TESTING)
 	nvgpu_log(g, gpu_dbg_gr, "PM CTXSW image size = %u", sizes->pm_ctxsw_image_size);
 #endif
 
-#ifdef CONFIG_NVGPU_GRAPHICS
+#ifdef CONFIG_NVGPU_NON_FUSA
 	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
 		ret = g->ops.gr.falcon.ctrl_ctxsw(g,
 			NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE,
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c
index d58c1282b..92df7731f 100644
--- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c
@@ -38,7 +38,7 @@ int gp10b_gr_falcon_init_ctx_state(struct gk20a *g,
 
 	err = gm20b_gr_falcon_init_ctx_state(g, sizes);
 
-#ifdef CONFIG_NVGPU_GRAPHICS
+#ifdef CONFIG_NVGPU_NON_FUSA
 	if (err != 0) {
 		return err;
 	}
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
index c94610f30..2d7b0cc7e 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
@@ -277,7 +277,6 @@ void gp10b_gr_init_commit_global_attrib_cb(struct gk20a *g,
 		gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch);
 }
 
-#ifdef CONFIG_NVGPU_GRAPHICS
 void gp10b_gr_init_commit_cbes_reserve(struct gk20a *g,
 	struct nvgpu_gr_ctx *gr_ctx, bool patch)
 {
@@ -318,13 +317,6 @@ u32 gp10b_gr_init_get_ctx_spill_size(struct gk20a *g)
 		 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v());
 }
 
-u32 gp10b_gr_init_get_ctx_pagepool_size(struct gk20a *g)
-{
-	return nvgpu_safe_mult_u32(
-		 g->ops.gr.init.pagepool_default_size(g),
-		 gr_scc_pagepool_total_pages_byte_granularity_v());
-}
-
 u32 gp10b_gr_init_get_ctx_betacb_size(struct gk20a *g)
 {
 	return nvgpu_safe_add_u32(
@@ -351,4 +343,3 @@ void gp10b_gr_init_commit_ctxsw_spill(struct gk20a *g,
 			gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size),
 			patch);
 }
-#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
index 4e358e120..efb795214 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -73,19 +73,20 @@ void gp10b_gr_init_commit_global_attrib_cb(struct gk20a *g,
 void gp10b_gr_init_commit_cbes_reserve(struct gk20a *g,
 	struct nvgpu_gr_ctx *gr_ctx, bool patch);
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-u32 gp10b_gr_init_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size,
-	u32 tpc_count, u32 max_tpc);
 u32 gp10b_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g);
 u32 gp10b_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g);
 
 u32 gp10b_gr_init_get_ctx_spill_size(struct gk20a *g);
-u32 gp10b_gr_init_get_ctx_pagepool_size(struct gk20a *g);
 u32 gp10b_gr_init_get_ctx_betacb_size(struct gk20a *g);
 
 void gp10b_gr_init_commit_ctxsw_spill(struct gk20a *g,
 	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch);
-#endif /* CONFIG_NVGPU_GRAPHICS */
 #endif /* CONFIG_NVGPU_HAL_NON_FUSA */
 
+#ifdef CONFIG_NVGPU_GRAPHICS
+u32 gp10b_gr_init_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size,
+	u32 tpc_count, u32 max_tpc);
+u32 gp10b_gr_init_get_ctx_pagepool_size(struct gk20a *g);
+#endif /* CONFIG_NVGPU_GRAPHICS */
+
 #endif /* NVGPU_GR_INIT_GP10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b_fusa.c
index 1f1ad3de3..a919a4fae 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b_fusa.c
@@ -361,4 +361,11 @@ u32 gp10b_gr_init_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size,
 
 	return NVGPU_ALIGN(size, 128U);
 }
-#endif
+
+u32 gp10b_gr_init_get_ctx_pagepool_size(struct gk20a *g)
+{
+	return nvgpu_safe_mult_u32(
+		 g->ops.gr.init.pagepool_default_size(g),
+		 gr_scc_pagepool_total_pages_byte_granularity_v());
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
index e1f78e593..1336dec04 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -50,185 +50,6 @@
 
 #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100U
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-void gv11b_gr_init_rop_mapping(struct gk20a *g,
-			      struct nvgpu_gr_config *gr_config)
-{
-	u32 map;
-	u32 i, j = 1U;
-	u32 base = 0U;
-	u32 mapreg_num, offset, mapregs, tile_cnt, tpc_cnt;
-	u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
-	u32 num_tpc_per_gpc = nvgpu_get_litter_value(g,
-				GPU_LIT_NUM_TPC_PER_GPC);
-	u32 num_tpcs = nvgpu_safe_mult_u32(num_gpcs, num_tpc_per_gpc);
-
-	nvgpu_log_fn(g, " ");
-
-	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
-		nvgpu_log_fn(g, " MIG is enabled, skipped rop mapping");
-		return;
-	}
-
-	nvgpu_writel(g, gr_crstr_map_table_cfg_r(),
-		gr_crstr_map_table_cfg_row_offset_f(
-			nvgpu_gr_config_get_map_row_offset(gr_config)) |
-		gr_crstr_map_table_cfg_num_entries_f(
-			nvgpu_gr_config_get_tpc_count(gr_config)));
-	/*
-	 * 6 tpc can be stored in one map register.
-	 * But number of tpcs are not always multiple of six,
-	 * so adding additional check for valid number of
-	 * tpcs before programming map register.
-	 */
-	mapregs = DIV_ROUND_UP(num_tpcs, GR_TPCS_INFO_FOR_MAPREGISTER);
-
-	for (mapreg_num = 0U; mapreg_num < mapregs; mapreg_num++) {
-		map = 0U;
-		offset = 0U;
-		while ((offset < GR_TPCS_INFO_FOR_MAPREGISTER)
-			&& (num_tpcs > 0U)) {
-			tile_cnt = nvgpu_gr_config_get_map_tile_count(
-						gr_config, base + offset);
-			if (offset == 0U) {
-				map = map | gr_crstr_gpc_map_tile0_f(tile_cnt);
-			} else if (offset == 1U) {
-				map = map | gr_crstr_gpc_map_tile1_f(tile_cnt);
-			} else if (offset == 2U) {
-				map = map | gr_crstr_gpc_map_tile2_f(tile_cnt);
-			} else if (offset == 3U) {
-				map = map | gr_crstr_gpc_map_tile3_f(tile_cnt);
-			} else if (offset == 4U) {
-				map = map | gr_crstr_gpc_map_tile4_f(tile_cnt);
-			} else if (offset == 5U) {
-				map = map | gr_crstr_gpc_map_tile5_f(tile_cnt);
-			} else {
-				nvgpu_err(g, "incorrect rop mapping %x",
-					  offset);
-			}
-			num_tpcs--;
-			offset++;
-		}
-
-		nvgpu_writel(g, gr_crstr_gpc_map_r(mapreg_num), map);
-		nvgpu_writel(g, gr_ppcs_wwdx_map_gpc_map_r(mapreg_num), map);
-		nvgpu_writel(g, gr_rstr2d_gpc_map_r(mapreg_num), map);
-
-		base = nvgpu_safe_add_u32(base, GR_TPCS_INFO_FOR_MAPREGISTER);
-	}
-
-	nvgpu_writel(g, gr_ppcs_wwdx_map_table_cfg_r(),
-		gr_ppcs_wwdx_map_table_cfg_row_offset_f(
-			nvgpu_gr_config_get_map_row_offset(gr_config)) |
-		gr_ppcs_wwdx_map_table_cfg_num_entries_f(
-			nvgpu_gr_config_get_tpc_count(gr_config)));
-
-	for (i = 0U; i < gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(); i++) {
-		tpc_cnt = nvgpu_gr_config_get_tpc_count(gr_config);
-		nvgpu_writel(g, gr_ppcs_wwdx_map_table_cfg_coeff_r(i),
-			gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(
-			   (BIT32(j) % tpc_cnt)) |
-			gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(
-			   (BIT32(nvgpu_safe_add_u32(j, 1U)) % tpc_cnt)) |
-			gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(
-			   (BIT32(nvgpu_safe_add_u32(j, 2U)) % tpc_cnt)) |
-			gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(
-			   (BIT32(nvgpu_safe_add_u32(j, 3U)) % tpc_cnt)));
-			j = nvgpu_safe_add_u32(j, 4U);
-	}
-
-	nvgpu_writel(g, gr_rstr2d_map_table_cfg_r(),
-		gr_rstr2d_map_table_cfg_row_offset_f(
-			nvgpu_gr_config_get_map_row_offset(gr_config)) |
-		gr_rstr2d_map_table_cfg_num_entries_f(
-			nvgpu_gr_config_get_tpc_count(gr_config)));
-}
-
-u32 gv11b_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g)
-{
-	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
-}
-
-u32 gv11b_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g)
-{
-	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
-}
-
-u32 gv11b_gr_init_get_ctx_spill_size(struct gk20a *g)
-{
-	return  nvgpu_safe_mult_u32(
-		  gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(),
-		  gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v());
-}
-
-u32 gv11b_gr_init_get_ctx_betacb_size(struct gk20a *g)
-{
-	return nvgpu_safe_add_u32(
-		g->ops.gr.init.get_attrib_cb_default_size(g),
-		nvgpu_safe_sub_u32(
-			gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(),
-			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()));
-}
-
-void gv11b_gr_init_commit_ctxsw_spill(struct gk20a *g,
-	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch)
-{
-
-	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
-		nvgpu_log_fn(g, " MIG is enabled, skipped commit ctxsw spill");
-		return;
-	}
-
-	addr = addr >> gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v();
-
-	size /=	gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
-
-	nvgpu_assert(u64_hi32(addr) == 0U);
-	nvgpu_gr_ctx_patch_write(g, gr_ctx,
-			gr_gpc0_swdx_rm_spill_buffer_addr_r(),
-			gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f((u32)addr),
-			patch);
-	nvgpu_gr_ctx_patch_write(g, gr_ctx,
-			gr_gpc0_swdx_rm_spill_buffer_size_r(),
-			gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size),
-			patch);
-}
-
-void gv11b_gr_init_commit_gfxp_wfi_timeout(struct gk20a *g,
-	struct nvgpu_gr_ctx *gr_ctx, bool patch)
-{
-
-	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
-		nvgpu_log_fn(g, " MIG is enabled, skipped gfxp wfi timeout");
-		return;
-	}
-
-	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_fe_gfxp_wfi_timeout_r(),
-		GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT, patch);
-}
-
-int gv11b_gr_init_preemption_state(struct gk20a *g)
-{
-	u32 debug_2;
-
-	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
-
-	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
-		nvgpu_log_fn(g,
-			" MIG is enabled, skipped init gfxp wfi timeout");
-		return 0;
-	}
-
-	debug_2 = nvgpu_readl(g, gr_debug_2_r());
-	debug_2 = set_field(debug_2,
-		gr_debug_2_gfxp_wfi_timeout_unit_m(),
-		gr_debug_2_gfxp_wfi_timeout_unit_usec_f());
-	nvgpu_writel(g, gr_debug_2_r(), debug_2);
-
-	return 0;
-}
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 void gv11b_gr_init_get_access_map(struct gk20a *g,
 				   u32 **whitelist, u32 *num_entries)
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
index b67ff6fa7..073b91f7d 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
@@ -1047,3 +1047,182 @@ void gv11b_gr_init_restore_stats_counter_bundle_data(struct gk20a *g,
 
 }
 #endif
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+void gv11b_gr_init_rop_mapping(struct gk20a *g,
+			      struct nvgpu_gr_config *gr_config)
+{
+	u32 map;
+	u32 i, j = 1U;
+	u32 base = 0U;
+	u32 mapreg_num, offset, mapregs, tile_cnt, tpc_cnt;
+	u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
+	u32 num_tpc_per_gpc = nvgpu_get_litter_value(g,
+				GPU_LIT_NUM_TPC_PER_GPC);
+	u32 num_tpcs = nvgpu_safe_mult_u32(num_gpcs, num_tpc_per_gpc);
+
+	nvgpu_log_fn(g, " ");
+
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_log_fn(g, " MIG is enabled, skipped rop mapping");
+		return;
+	}
+
+	nvgpu_writel(g, gr_crstr_map_table_cfg_r(),
+		gr_crstr_map_table_cfg_row_offset_f(
+			nvgpu_gr_config_get_map_row_offset(gr_config)) |
+		gr_crstr_map_table_cfg_num_entries_f(
+			nvgpu_gr_config_get_tpc_count(gr_config)));
+	/*
+	 * 6 tpc can be stored in one map register.
+	 * But number of tpcs are not always multiple of six,
+	 * so adding additional check for valid number of
+	 * tpcs before programming map register.
+	 */
+	mapregs = DIV_ROUND_UP(num_tpcs, GR_TPCS_INFO_FOR_MAPREGISTER);
+
+	for (mapreg_num = 0U; mapreg_num < mapregs; mapreg_num++) {
+		map = 0U;
+		offset = 0U;
+		while ((offset < GR_TPCS_INFO_FOR_MAPREGISTER)
+			&& (num_tpcs > 0U)) {
+			tile_cnt = nvgpu_gr_config_get_map_tile_count(
+						gr_config, base + offset);
+			if (offset == 0U) {
+				map = map | gr_crstr_gpc_map_tile0_f(tile_cnt);
+			} else if (offset == 1U) {
+				map = map | gr_crstr_gpc_map_tile1_f(tile_cnt);
+			} else if (offset == 2U) {
+				map = map | gr_crstr_gpc_map_tile2_f(tile_cnt);
+			} else if (offset == 3U) {
+				map = map | gr_crstr_gpc_map_tile3_f(tile_cnt);
+			} else if (offset == 4U) {
+				map = map | gr_crstr_gpc_map_tile4_f(tile_cnt);
+			} else if (offset == 5U) {
+				map = map | gr_crstr_gpc_map_tile5_f(tile_cnt);
+			} else {
+				nvgpu_err(g, "incorrect rop mapping %x",
+					  offset);
+			}
+			num_tpcs--;
+			offset++;
+		}
+
+		nvgpu_writel(g, gr_crstr_gpc_map_r(mapreg_num), map);
+		nvgpu_writel(g, gr_ppcs_wwdx_map_gpc_map_r(mapreg_num), map);
+		nvgpu_writel(g, gr_rstr2d_gpc_map_r(mapreg_num), map);
+
+		base = nvgpu_safe_add_u32(base, GR_TPCS_INFO_FOR_MAPREGISTER);
+	}
+
+	nvgpu_writel(g, gr_ppcs_wwdx_map_table_cfg_r(),
+		gr_ppcs_wwdx_map_table_cfg_row_offset_f(
+			nvgpu_gr_config_get_map_row_offset(gr_config)) |
+		gr_ppcs_wwdx_map_table_cfg_num_entries_f(
+			nvgpu_gr_config_get_tpc_count(gr_config)));
+
+	for (i = 0U; i < gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(); i++) {
+		tpc_cnt = nvgpu_gr_config_get_tpc_count(gr_config);
+		nvgpu_writel(g, gr_ppcs_wwdx_map_table_cfg_coeff_r(i),
+			gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(
+			   (BIT32(j) % tpc_cnt)) |
+			gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(
+			   (BIT32(nvgpu_safe_add_u32(j, 1U)) % tpc_cnt)) |
+			gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(
+			   (BIT32(nvgpu_safe_add_u32(j, 2U)) % tpc_cnt)) |
+			gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(
+			   (BIT32(nvgpu_safe_add_u32(j, 3U)) % tpc_cnt)));
+			j = nvgpu_safe_add_u32(j, 4U);
+	}
+
+	nvgpu_writel(g, gr_rstr2d_map_table_cfg_r(),
+		gr_rstr2d_map_table_cfg_row_offset_f(
+			nvgpu_gr_config_get_map_row_offset(gr_config)) |
+		gr_rstr2d_map_table_cfg_num_entries_f(
+			nvgpu_gr_config_get_tpc_count(gr_config)));
+}
+
+u32 gv11b_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
+}
+
+u32 gv11b_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g)
+{
+	return gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
+}
+
+u32 gv11b_gr_init_get_ctx_spill_size(struct gk20a *g)
+{
+	return  nvgpu_safe_mult_u32(
+		  gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(),
+		  gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v());
+}
+
+u32 gv11b_gr_init_get_ctx_betacb_size(struct gk20a *g)
+{
+	return nvgpu_safe_add_u32(
+		g->ops.gr.init.get_attrib_cb_default_size(g),
+		nvgpu_safe_sub_u32(
+			gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(),
+			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()));
+}
+
+void gv11b_gr_init_commit_ctxsw_spill(struct gk20a *g,
+	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch)
+{
+
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_log_fn(g, " MIG is enabled, skipped commit ctxsw spill");
+		return;
+	}
+
+	addr = addr >> gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v();
+
+	size /=	gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
+
+	nvgpu_assert(u64_hi32(addr) == 0U);
+	nvgpu_gr_ctx_patch_write(g, gr_ctx,
+			gr_gpc0_swdx_rm_spill_buffer_addr_r(),
+			gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f((u32)addr),
+			patch);
+	nvgpu_gr_ctx_patch_write(g, gr_ctx,
+			gr_gpc0_swdx_rm_spill_buffer_size_r(),
+			gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size),
+			patch);
+}
+
+void gv11b_gr_init_commit_gfxp_wfi_timeout(struct gk20a *g,
+	struct nvgpu_gr_ctx *gr_ctx, bool patch)
+{
+
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_log_fn(g, " MIG is enabled, skipped gfxp wfi timeout");
+		return;
+	}
+
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_fe_gfxp_wfi_timeout_r(),
+		GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT, patch);
+}
+
+int gv11b_gr_init_preemption_state(struct gk20a *g)
+{
+	u32 debug_2;
+
+	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
+
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_log_fn(g,
+			" MIG is enabled, skipped init gfxp wfi timeout");
+		return 0;
+	}
+
+	debug_2 = nvgpu_readl(g, gr_debug_2_r());
+	debug_2 = set_field(debug_2,
+		gr_debug_2_gfxp_wfi_timeout_unit_m(),
+		gr_debug_2_gfxp_wfi_timeout_unit_usec_f());
+	nvgpu_writel(g, gr_debug_2_r(), debug_2);
+
+	return 0;
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
index f7c07866e..35910e8a3 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B L2
  *
- * Copyright (c) 2014-2020 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2021 NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -112,41 +112,6 @@ u64 gm20b_determine_L2_size_bytes(struct gk20a *g)
 	return cache_size;
 }
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-/*
- * Sets the ZBC color for the passed index.
- */
-void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
-					  u32 *color_l2,
-					  u32 index)
-{
-	u32 i;
-
-	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
-		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
-
-	for (i = 0;
-	     i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
-		nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
-			color_l2[i]);
-	}
-}
-
-/*
- * Sets the ZBC depth for the passed index.
- */
-void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
-					  u32 depth_val,
-					  u32 index)
-{
-	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
-		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
-
-	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
-		depth_val);
-}
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled)
 {
 	u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b_fusa.c
index 6ee106f83..c267a7524 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b_fusa.c
@@ -1,7 +1,7 @@
 /*
  * GM20B L2
  *
- * Copyright (c) 2014-2020 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2021 NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -160,14 +160,37 @@ void gm20b_flush_ltc(struct gk20a *g)
 	}
 }
 
+#ifdef CONFIG_NVGPU_GRAPHICS
 /*
  * Sets the ZBC color for the passed index.
  */
+void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
+					  u32 *color_l2,
+					  u32 index)
+{
+	u32 i;
+
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	for (i = 0;
+	     i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
+		nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
+			color_l2[i]);
+	}
+}
 
 /*
  * Sets the ZBC depth for the passed index.
  */
+void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
+					  u32 depth_val,
+					  u32 index)
+{
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
 
-/*
- * LTC pri addressing
- */
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
+		depth_val);
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c
deleted file mode 100644
index 088ffe3ec..000000000
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * GV11B LTC
- *
- * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/io.h>
-#include <nvgpu/gk20a.h>
-#include <nvgpu/nvgpu_err.h>
-#include <nvgpu/static_analysis.h>
-#include <nvgpu/gr/zbc.h>
-
-#include "ltc_gv11b.h"
-
-#include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
-
-#include <nvgpu/utils.h>
-
-#ifdef CONFIG_NVGPU_GRAPHICS
-/*
- * Sets the ZBC stencil for the passed index.
- */
-void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
-					  u32 stencil_depth,
-					  u32 index)
-{
-	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
-		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
-
-	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
-			stencil_depth);
-}
-#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c
index 4b13a4f20..6e0ab1d04 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c
@@ -1,7 +1,7 @@
 /*
  * GV11B LTC
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -78,3 +78,19 @@ done:
 
 	return err;
 }
+
+#ifdef CONFIG_NVGPU_GRAPHICS
+/*
+ * Sets the ZBC stencil for the passed index.
+ */
+void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
+					  u32 stencil_depth,
+					  u32 index)
+{
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
+			stencil_depth);
+}
+#endif /* CONFIG_NVGPU_GRAPHICS */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/io.h b/drivers/gpu/nvgpu/include/nvgpu/io.h
index de53b825c..c246902f8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/io.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/io.h
@@ -154,7 +154,6 @@ u32 nvgpu_readl_impl(struct gk20a *g, u32 r);
  */
 void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v);
 
-#ifdef CONFIG_NVGPU_NON_FUSA
 /**
  * @brief Ensure write to a GPU register.
  *
@@ -168,7 +167,6 @@ void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v);
  * @return None.
  */
 void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v);
-#endif
 
 /**
  * @brief Write a value to an already mapped bar1 io-region.
diff --git a/userspace/required_tests.ini b/userspace/required_tests.ini
index 150e94580..d7d7f2c71 100644
--- a/userspace/required_tests.ini
+++ b/userspace/required_tests.ini
@@ -665,7 +665,7 @@ test_gr_obj_ctx_error_injection.gr_obj_ctx_alloc_errors=0
 test_gr_init_setup_cleanup.gr_setup_cleanup=0
 test_gr_init_setup_ready.gr_setup_setup=0
 test_gr_setup_alloc_obj_ctx.gr_setup_alloc_obj_ctx=0
-test_gr_setup_alloc_obj_ctx_error_injections.gr_setup_alloc_obj_ctx_error_injections=0
+test_gr_setup_alloc_obj_ctx_error_injections.gr_setup_alloc_obj_ctx_error_injections=2
 test_gr_setup_free_obj_ctx.gr_setup_free_obj_ctx=0
 test_gr_setup_preemption_mode_errors.gr_setup_preemption_mode_errors=2
 test_gr_setup_set_preemption_mode.gr_setup_set_preemption_mode=0
diff --git a/userspace/units/class/nvgpu-class.c b/userspace/units/class/nvgpu-class.c
index 7420772fd..18f314c9b 100644
--- a/userspace/units/class/nvgpu-class.c
+++ b/userspace/units/class/nvgpu-class.c
@@ -59,11 +59,11 @@ u32 valid_classes[] = {
 	0xC3C0U, /* VOLTA_COMPUTE_A */
 	0xC3B5U, /* VOLTA_DMA_COPY_A */
 	0xC36FU, /* VOLTA_CHANNEL_GPFIFO_A */
+	0xC397U, /* VOLTA_A */
 };
 
 u32 invalid_classes[] = {
 	0x1234U, /* random value */
-	0xC397U, /* VOLTA_A */
 	0xC097U, /* PASCAL_A */
 	0xC0C0U, /* PASCAL_COMPUTE_A */
 	0xB1C0U, /* MAXWELL_COMPUTE_B */
diff --git a/userspace/units/gr/setup/nvgpu-gr-setup.c b/userspace/units/gr/setup/nvgpu-gr-setup.c
index f08ca0a74..ff70f3714 100644
--- a/userspace/units/gr/setup/nvgpu-gr-setup.c
+++ b/userspace/units/gr/setup/nvgpu-gr-setup.c
@@ -698,7 +698,7 @@ struct unit_module_test nvgpu_gr_setup_tests[] = {
 			test_gr_setup_preemption_mode_errors, NULL, 2),
 	UNIT_TEST(gr_setup_free_obj_ctx, test_gr_setup_free_obj_ctx, NULL, 0),
 	UNIT_TEST(gr_setup_alloc_obj_ctx_error_injections,
-			test_gr_setup_alloc_obj_ctx_error_injections, NULL, 0),
+			test_gr_setup_alloc_obj_ctx_error_injections, NULL, 2),
 	UNIT_TEST(gr_setup_cleanup, test_gr_init_setup_cleanup, NULL, 0),
 };