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gpu: nvgpu: fifo: fix MISRA 10.3 violations

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MISRA Rule 10.3 prohibits assigning objects of different essential or
narrower type. This fixes MISRA 10.3 violations in the common/fifo unit.

JIRA NVGPU-3023

Change-Id: Ibab6704e8d3cffd37c6c0e31ba6fc6c0bb7b517b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087812
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-04-01 11:07:04 -04:00
committed by mobile promotions
parent 295ff82fc9
commit c0b65e8b05
13 changed files with 23 additions and 12 deletions
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2
drivers/gpu/nvgpu/common/mm/mm.c
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@@ -362,7 +362,7 @@ void nvgpu_init_mm_ce_context(struct gk20a *g)
(g->mm.vidmem.ce_ctx_id == NVGPU_CE_INVAL_CTX_ID)) {
g->mm.vidmem.ce_ctx_id =
gk20a_ce_create_context(g,
(int)nvgpu_engine_get_fast_ce_runlist_id(g),
nvgpu_engine_get_fast_ce_runlist_id(g),
-1,
-1);