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gpu: nvgpu: fifo: fix MISRA 10.3 violations
MISRA Rule 10.3 prohibits assigning objects of different essential or narrower type. This fixes MISRA 10.3 violations in the common/fifo unit. JIRA NVGPU-3023 Change-Id: Ibab6704e8d3cffd37c6c0e31ba6fc6c0bb7b517b Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2087812 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -35,6 +35,7 @@
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#include <nvgpu/firmware.h>
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#include <nvgpu/os_sched.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/runlist.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/string.h>
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@@ -1339,7 +1340,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
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ch = gk20a_open_new_channel_with_cb(g, gk20a_cde_finished_ctx_cb,
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cde_ctx,
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-1,
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RUNLIST_INVALID_ID,
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false);
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if (!ch) {
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nvgpu_warn(g, "cde: gk20a channel not available");
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