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gpu: nvgpu: move load_smid_config and program_sm_id_numbering hals

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Move load_smid_config and program_sm_id_numbering hal functions to
corresponding hal files in hal.gr.init.

Add new hal for get_sm_id_size and new static function in common.gr
init code for gr_load_sm_id_config.

JIRA NVGPU-2951

Change-Id: I27755306d278db9fcd5ab60169a64057b2989ea8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075875
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-03-18 16:05:57 -07:00
committed by mobile promotions
parent d466ab8007
commit c0c06f0307
21 changed files with 241 additions and 215 deletions
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23
drivers/gpu/nvgpu/common/gr/gr.c
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@@ -25,6 +25,25 @@
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/config.h>
static int gr_load_sm_id_config(struct gk20a *g)
{
int err;
u32 *tpc_sm_id;
u32 sm_id_size = g->ops.gr.init.get_sm_id_size();
struct nvgpu_gr_config *gr_config = g->gr.config;
tpc_sm_id = nvgpu_kcalloc(g, sm_id_size, sizeof(u32));
if (tpc_sm_id == NULL) {
return -ENOMEM;
}
err = g->ops.gr.init.sm_id_config(g, tpc_sm_id, gr_config);
nvgpu_kfree(g, tpc_sm_id);
return err;
}
static void gr_load_tpc_mask(struct gk20a *g)
{
u32 pes_tpc_mask = 0, fuse_tpc_mask;
@@ -98,7 +117,7 @@ int nvgpu_gr_init_fs_state(struct gk20a *g)
tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index;
gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index;
g->ops.gr.program_sm_id_numbering(g, gpc_index, tpc_index, sm_id);
g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id);
}
g->ops.gr.init.pd_tpc_per_gpc(g, gr_config);
@@ -123,7 +142,7 @@ int nvgpu_gr_init_fs_state(struct gk20a *g)
gr_load_tpc_mask(g);
err = g->ops.gr.load_smid_config(g);
err = gr_load_sm_id_config(g);
if (err != 0) {
nvgpu_err(g, "load_smid_config failed err=%d", err);
}