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gpu: nvgpu: post bpt events after processing

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Receive hww_global_esr in gr_gp10b_handle_sm_exception() and
pass it to gr_gk20a_handle_sm_exception()

Bug 200209410

Change-Id: I467355aa57dd3cf03c4ea2134fbc8691f8e76369
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1194986
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-08-01 14:26:21 +05:30
parent 0e1758a723
commit c0cbc337ca
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
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@@ -98,7 +98,8 @@ static void gr_gp10b_sm_lrf_ecc_overcount_war(int single_err,
}
static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct channel_gk20a *fault_ch)
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr)
{
int ret = 0;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -108,7 +109,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
u32 lrf_single_count_delta, lrf_double_count_delta;
u32 shm_ecc_status;
gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch);
gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
/* Check for LRF ECC errors. */
lrf_ecc_status = gk20a_readl(g,