diff --git a/drivers/gpu/nvgpu/common/fifo/fifo.c b/drivers/gpu/nvgpu/common/fifo/fifo.c
index a2056f993..3f127f26e 100644
--- a/drivers/gpu/nvgpu/common/fifo/fifo.c
+++ b/drivers/gpu/nvgpu/common/fifo/fifo.c
@@ -256,3 +256,27 @@ void nvgpu_report_host_error(struct gk20a *g, u32 inst,
 				inst, err_id, intr_info, ret);
 	}
 }
+
+static const char * const pbdma_ch_eng_status_str[] = {
+	"invalid",
+	"valid",
+	"NA",
+	"NA",
+	"NA",
+	"load",
+	"save",
+	"switch",
+};
+
+static const char * const not_found_str[] = {
+	"NOT FOUND"
+};
+
+const char *nvgpu_fifo_decode_pbdma_ch_eng_status(u32 index)
+{
+	if (index >= ARRAY_SIZE(pbdma_ch_eng_status_str)) {
+		return not_found_str[0];
+	} else {
+		return pbdma_ch_eng_status_str[index];
+	}
+}
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index d9597aa93..51dddf3a3 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -890,30 +890,6 @@ int gk20a_fifo_suspend(struct gk20a *g)
 	return 0;
 }
 
-static const char * const pbdma_chan_eng_ctx_status_str[] = {
-	"invalid",
-	"valid",
-	"NA",
-	"NA",
-	"NA",
-	"load",
-	"save",
-	"switch",
-};
-
-static const char * const not_found_str[] = {
-	"NOT FOUND"
-};
-
-const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index)
-{
-	if (index >= ARRAY_SIZE(pbdma_chan_eng_ctx_status_str)) {
-		return not_found_str[0];
-	} else {
-		return pbdma_chan_eng_ctx_status_str[index];
-	}
-}
-
 int gk20a_fifo_init_pbdma_map(struct gk20a *g, u32 *pbdma_map, u32 num_pbdma)
 {
 	u32 id;
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index d19c671c0..fcf7ed1d1 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -263,8 +263,6 @@ static inline void gk20a_fifo_profile_snapshot(
 }
 #endif
 
-const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index);
-
 int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
 			unsigned int id_type);
 int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg);
diff --git a/drivers/gpu/nvgpu/hal/fifo/engine_status_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/engine_status_gm20b.c
index 2135df782..b79d693fa 100644
--- a/drivers/gpu/nvgpu/hal/fifo/engine_status_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/fifo/engine_status_gm20b.c
@@ -193,7 +193,7 @@ void gm20b_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o)
 			nvgpu_engine_status_is_next_ctx_type_tsg(
 				&engine_status) ?
 				"[tsg]" : "[channel]",
-			gk20a_decode_pbdma_chan_eng_ctx_status(
+			nvgpu_fifo_decode_pbdma_ch_eng_status(
 				engine_status.ctxsw_state));
 
 		if (engine_status.is_faulted) {
diff --git a/drivers/gpu/nvgpu/hal/fifo/engine_status_gv100.c b/drivers/gpu/nvgpu/hal/fifo/engine_status_gv100.c
index 0382fe70a..8738f6a81 100644
--- a/drivers/gpu/nvgpu/hal/fifo/engine_status_gv100.c
+++ b/drivers/gpu/nvgpu/hal/fifo/engine_status_gv100.c
@@ -66,7 +66,7 @@ void gv100_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o)
 			nvgpu_engine_status_is_next_ctx_type_tsg(
 				&engine_status) ?
 				"tsg" : "channel",
-			gk20a_decode_pbdma_chan_eng_ctx_status(
+			nvgpu_fifo_decode_pbdma_ch_eng_status(
 				engine_status.ctxsw_state));
 
 		if (engine_status.in_reload_status) {
diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
index 7185facb7..ecdbc6a63 100644
--- a/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
@@ -333,7 +333,7 @@ void gm20b_pbdma_dump_status(struct gk20a *g, struct gk20a_debug_output *o)
 			nvgpu_pbdma_status_is_next_id_type_tsg(
 				&pbdma_status) ?
 				   "[tsg]" : "[channel]",
-			gk20a_decode_pbdma_chan_eng_ctx_status(
+			nvgpu_fifo_decode_pbdma_ch_eng_status(
 				pbdma_status.pbdma_channel_status));
 		gk20a_debug_output(o,
 			"  PBDMA_PUT %016llx PBDMA_GET %016llx",
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
index 0edeb1bc6..fcecfcfdc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
@@ -47,4 +47,6 @@ int nvgpu_fifo_setup_sw_common(struct gk20a *g);
 void nvgpu_fifo_cleanup_sw(struct gk20a *g);
 void nvgpu_fifo_cleanup_sw_common(struct gk20a *g);
 
+const char *nvgpu_fifo_decode_pbdma_ch_eng_status(u32 index);
+
 #endif /* NVGPU_FIFO_COMMON_H */