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gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert. nvgpu_assert is warning on linux but a system halt on safety builds. nvgpu_preempt_channel JIRA NVGPU-3388 Change-Id: Id60d10c0d1593a6b798a037b9ec0efe6c4d20dd5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115762 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1176,7 +1176,7 @@ int nvgpu_channel_set_syncpt(struct nvgpu_channel *ch)
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gk20a_disable_channel_tsg(g, ch);
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/* preempt the channel */
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WARN_ON(nvgpu_preempt_channel(g, ch) != 0);
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nvgpu_assert(nvgpu_preempt_channel(g, ch) == 0);
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g->ops.ramfc.set_syncpt(ch, new_syncpt);
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}
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@@ -2382,8 +2382,6 @@ clean_up_mutex:
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return err;
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}
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/* in this context the "channel" is the host1x channel which
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* maps to *all* gk20a channels */
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int nvgpu_channel_suspend_all_serviceable_ch(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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@@ -2407,7 +2405,7 @@ int nvgpu_channel_suspend_all_serviceable_ch(struct gk20a *g)
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/* disable channel */
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gk20a_disable_channel_tsg(g, ch);
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/* preempt the channel */
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nvgpu_preempt_channel(g, ch);
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nvgpu_assert(nvgpu_preempt_channel(g, ch) == 0);
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/* wait for channel update notifiers */
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if (g->os_channel.work_completion_cancel_sync != NULL) {
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g->os_channel.work_completion_cancel_sync(ch);
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